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annotate modules/bluespec/Pygar/core/audioCorePipeline.bsv @ 51:9fe5ed4af92d pygar svn.52

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[svn r52] tested having multiple cores
author punk
date Wed, 05 May 2010 17:01:04 -0400
parents a139cc07b773
children 49049f97312c
rev   line source
punk@13 1 // The MIT License
punk@13 2
punk@13 3 // Copyright (c) 2009 Massachusetts Institute of Technology
punk@13 4
punk@13 5 // Permission is hereby granted, free of charge, to any person obtaining a copy
punk@13 6 // of this software and associated documentation files (the "Software"), to deal
punk@13 7 // in the Software without restriction, including without limitation the rights
punk@13 8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
punk@13 9 // copies of the Software, and to permit persons to whom the Software is
punk@13 10 // furnished to do so, subject to the following conditions:
punk@13 11
punk@13 12 // The above copyright notice and this permission notice shall be included in
punk@13 13 // all copies or substantial portions of the Software.
punk@13 14
punk@13 15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
punk@13 16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
punk@13 17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
punk@13 18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
punk@13 19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
punk@13 20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
punk@13 21 // THE SOFTWARE.
punk@13 22
punk@13 23 // Author: Kermin Fleming kfleming@mit.edu
punk@13 24
punk@13 25 import Connectable::*;
punk@13 26 import GetPut::*;
punk@13 27 import ClientServer::*;
punk@13 28 import FIFO::*;
punk@15 29 import SpecialFIFOs::*;
punk@13 30
punk@13 31 //AWB includes
punk@13 32 `include "asim/provides/low_level_platform_interface.bsh"
punk@13 33 `include "asim/provides/soft_connections.bsh"
punk@13 34 `include "asim/provides/common_services.bsh"
punk@13 35
punk@13 36 //Local includes
punk@13 37 `include "asim/provides/audio_pipe_types.bsh" //provides Audio Pipeline interface
punk@33 38 `include "asim/provides/path_types.bsh"
punk@13 39 `include "asim/provides/core.bsh"
punk@43 40 `include "asim/provides/mixer.bsh"
punk@15 41 `include "asim/provides/processor_library.bsh"
punk@15 42 `include "asim/provides/fpga_components.bsh"
punk@51 43 `include "asim/dict/VDEV_SCRATCH.bsh"
punk@33 44
punk@13 45 `include "asim/rrr/remote_client_stub_AUDIOCORERRR.bsh"
punk@36 46 `include "asim/rrr/remote_server_stub_AUDIOCORERRR.bsh"
punk@13 47
punk@13 48 module [CONNECTED_MODULE] mkConnectedApplication ();
punk@51 49 Core core <- mkCore(`VDEV_SCRATCH_MEMORYA);
punk@51 50 Core anotherCore <- mkCore(`VDEV_SCRATCH_MEMORYB);
rlm@47 51 // RLM::
rlm@47 52 // the simple existance of this additional core causes the dreaded
rlm@47 53 // beast to emerge --- the ASSERTION FAILURE: sw/model/stats-device.cpp:317 Cycle:0
rlm@47 54 //stats device: Duplicate entry DATA_CACHE_NUM_WRITEBACKS, postion 0
rlm@47 55 //Core core1 <- mkCore;
punk@13 56 Reg#(int) cycle <- mkReg(0);
punk@13 57
punk@39 58 // Reg#(Bit#(32)) ac_fini <- mkReg(0);
punk@39 59
punk@13 60 //External memory
punk@13 61 // I'm not comfortable assuming that the memory subsystem is in order
punk@33 62 // So I'll insert a completion buffer here.
punk@33 63
punk@33 64 // Services Samples
punk@15 65 ClientStub_AUDIOCORERRR client_stub <- mkClientStub_AUDIOCORERRR();
punk@48 66
punk@13 67
punk@36 68 //-----------------------------------------------------------
punk@36 69 // Debug port
punk@36 70
punk@36 71 ServerStub_AUDIOCORERRR server_stub <- mkServerStub_AUDIOCORERRR();
punk@36 72
punk@36 73
punk@13 74 // this is for the tracing
punk@13 75 rule printCycles;
punk@13 76 cycle <= cycle+1;
punk@13 77 $fdisplay(stderr, " => Cycle = %d", cycle);
punk@13 78 endrule
punk@13 79
punk@48 80 rule feedOutput;
punk@13 81 let pipelineData <- core.sampleOutput.get();
punk@13 82 AudioProcessorControl endOfFileTag = EndOfFile;
punk@13 83 AudioProcessorControl sampleTag = Data;
punk@13 84
punk@25 85 case (pipelineData) matches
punk@25 86 tagged EndOfFile:
punk@15 87 client_stub.makeRequest_SendProcessedStream(zeroExtend(pack(endOfFileTag)),?);
punk@25 88 tagged Sample .sample:client_stub.makeRequest_SendProcessedStream(zeroExtend(pack(sampleTag)), zeroExtend(pack(sample)));
punk@25 89 endcase
punk@13 90 endrule
punk@13 91
punk@36 92 //***** SERVER Side *****
punk@36 93
punk@39 94 /* (* conservative_implicit_conditions *)
punk@37 95 rule handleCPUToHost;
punk@37 96 let req <- server_stub.acceptRequest_ReadCPUToHost();
punk@37 97 case (req)
punk@37 98 0: server_stub.sendResponse_ReadCPUToHost(cp0_tohost);
punk@37 99 endcase
punk@37 100 endrule
punk@39 101 */
punk@36 102 rule feedInput;
punk@36 103 let command <- server_stub.acceptRequest_SendUnprocessedStream();
punk@36 104 AudioProcessorControl ctrl = unpack(truncate(command.ctrl));
rlm@41 105
rlm@41 106 Bit#(32) test = unpack(truncate(command.channel));
punk@48 107 // $display("rlm: %x", test);
rlm@41 108
rlm@41 109
rlm@41 110 if(ctrl == EndOfFile)
punk@36 111 begin
punk@43 112 $display("lsp: PIPE received EOF ");
punk@43 113 core.sampleInput.put(tagged EndOfFile);
punk@36 114 end
punk@36 115 else
punk@36 116 begin
punk@43 117 // $display("lsp: PIPE received Data ");
punk@43 118 core.sampleInput.put(tagged Sample unpack(truncate(command.sample)));
punk@36 119 end
punk@36 120 endrule
punk@13 121 endmodule