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annotate modules/bluespec/Pygar/core/audioCorePipeline.bsv @ 36:99519a031813 pygar svn.37

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[svn r37] moved the server into audioCorePipeline
author punk
date Tue, 04 May 2010 18:54:54 -0400
parents 2c8166d205d5
children 0475235d1513
rev   line source
punk@13 1 // The MIT License
punk@13 2
punk@13 3 // Copyright (c) 2009 Massachusetts Institute of Technology
punk@13 4
punk@13 5 // Permission is hereby granted, free of charge, to any person obtaining a copy
punk@13 6 // of this software and associated documentation files (the "Software"), to deal
punk@13 7 // in the Software without restriction, including without limitation the rights
punk@13 8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
punk@13 9 // copies of the Software, and to permit persons to whom the Software is
punk@13 10 // furnished to do so, subject to the following conditions:
punk@13 11
punk@13 12 // The above copyright notice and this permission notice shall be included in
punk@13 13 // all copies or substantial portions of the Software.
punk@13 14
punk@13 15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
punk@13 16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
punk@13 17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
punk@13 18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
punk@13 19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
punk@13 20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
punk@13 21 // THE SOFTWARE.
punk@13 22
punk@13 23 // Author: Kermin Fleming kfleming@mit.edu
punk@13 24
punk@13 25 import Connectable::*;
punk@13 26 import GetPut::*;
punk@13 27 import ClientServer::*;
punk@13 28 import FIFO::*;
punk@15 29 import SpecialFIFOs::*;
punk@13 30
punk@13 31 //AWB includes
punk@13 32 `include "asim/provides/low_level_platform_interface.bsh"
punk@13 33 `include "asim/provides/soft_connections.bsh"
punk@13 34 `include "asim/provides/common_services.bsh"
punk@13 35
punk@13 36 //Local includes
punk@13 37 `include "asim/provides/audio_pipe_types.bsh" //provides Audio Pipeline interface
punk@33 38 `include "asim/provides/path_types.bsh"
punk@13 39 `include "asim/provides/core.bsh"
punk@15 40 `include "asim/provides/processor_library.bsh"
punk@15 41 `include "asim/provides/fpga_components.bsh"
punk@33 42 `include "asim/provides/scratchpad_memory.bsh"
punk@33 43 `include "asim/provides/mem_services.bsh"
punk@33 44 `include "asim/dict/VDEV_SCRATCH.bsh"
punk@33 45
punk@13 46 `include "asim/rrr/remote_client_stub_AUDIOCORERRR.bsh"
punk@36 47 `include "asim/rrr/remote_server_stub_AUDIOCORERRR.bsh"
punk@13 48
punk@13 49 module [CONNECTED_MODULE] mkConnectedApplication ();
punk@13 50 Core core <- mkCore;
punk@13 51 Reg#(int) cycle <- mkReg(0);
punk@13 52
punk@13 53 //External memory
punk@13 54 // I'm not comfortable assuming that the memory subsystem is in order
punk@33 55 // So I'll insert a completion buffer here.
punk@33 56 MEMORY_IFC#(Bit#(18), Bit#(32)) memory <- mkScratchpad(`VDEV_SCRATCH_MEMORY, SCRATCHPAD_CACHED); //Services Memory items
punk@33 57
punk@33 58 // Services Samples
punk@15 59 ClientStub_AUDIOCORERRR client_stub <- mkClientStub_AUDIOCORERRR();
punk@13 60 // Make this big enough so that several outstanding requests may be supported
punk@13 61 FIFO#(Bit#(MainMemTagSz)) tags <- mkSizedFIFO(8);
punk@13 62
punk@36 63 //-----------------------------------------------------------
punk@36 64 // Debug port
punk@36 65
punk@36 66 ServerStub_AUDIOCORERRR server_stub <- mkServerStub_AUDIOCORERRR();
punk@36 67
punk@36 68
punk@13 69 // this is for the tracing
punk@13 70 rule printCycles;
punk@13 71 cycle <= cycle+1;
punk@13 72 $fdisplay(stderr, " => Cycle = %d", cycle);
punk@13 73 endrule
punk@13 74
punk@13 75 rule sendMemReq;
punk@13 76 let coreReq <- core.mmem_client.request.get;
punk@13 77 case (coreReq) matches
punk@13 78 tagged LoadReq .load: begin
punk@13 79 //Allocate ROB space
punk@33 80 memory.readReq(truncate(load.addr>>2));
punk@13 81 tags.enq(load.tag);
punk@13 82 end
punk@13 83 tagged StoreReq .store: begin
punk@33 84 memory.write(truncate(store.addr>>2),store.data);
punk@13 85 end
punk@13 86 endcase
punk@13 87 endrule
punk@13 88
punk@13 89 rule receiveMemResp;
punk@33 90 let memResp <- memory.readRsp();
punk@13 91 tags.deq;
punk@13 92 core.mmem_client.response.put(tagged LoadResp {data:memResp,
punk@13 93 tag: tags.first});
punk@13 94 endrule
punk@13 95
punk@13 96 rule feedOutput;
punk@13 97 let pipelineData <- core.sampleOutput.get();
punk@13 98 AudioProcessorControl endOfFileTag = EndOfFile;
punk@13 99 AudioProcessorControl sampleTag = Data;
punk@13 100
punk@25 101 case (pipelineData) matches
punk@25 102 tagged EndOfFile:
punk@15 103 client_stub.makeRequest_SendProcessedStream(zeroExtend(pack(endOfFileTag)),?);
punk@25 104 tagged Sample .sample:client_stub.makeRequest_SendProcessedStream(zeroExtend(pack(sampleTag)), zeroExtend(pack(sample)));
punk@25 105 endcase
punk@13 106 endrule
punk@13 107
punk@36 108 //***** SERVER Side *****
punk@36 109
punk@36 110 rule feedInput;
punk@36 111 let command <- server_stub.acceptRequest_SendUnprocessedStream();
punk@36 112 AudioProcessorControl ctrl = unpack(truncate(command.ctrl));
punk@36 113 if(ctrl == EndOfFile)
punk@36 114 begin
punk@36 115 $display("lsp: PROCESSOR received EOF ");
punk@36 116 core.sampleInput.put(tagged EndOfFile);
punk@36 117 end
punk@36 118 else
punk@36 119 begin
punk@36 120 $display("lsp: PROCESSOR received Data ");
punk@36 121 core.sampleInput.put(tagged Sample unpack(truncate(command.sample)));
punk@36 122 end
punk@36 123 endrule
punk@13 124 endmodule