Mercurial > pygar

annotate modules/bluespec/Pygar/core/audioCorePipeline.bsv @ 15:a1833d9f6e3d pygar svn.16

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
[svn r16] Recent
author punk
date Tue, 27 Apr 2010 13:11:45 -0400
parents 6d461680c6d9
children 220c14f5963c
rev   line source
punk@13 1 // The MIT License
punk@13 2
punk@13 3 // Copyright (c) 2009 Massachusetts Institute of Technology
punk@13 4
punk@13 5 // Permission is hereby granted, free of charge, to any person obtaining a copy
punk@13 6 // of this software and associated documentation files (the "Software"), to deal
punk@13 7 // in the Software without restriction, including without limitation the rights
punk@13 8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
punk@13 9 // copies of the Software, and to permit persons to whom the Software is
punk@13 10 // furnished to do so, subject to the following conditions:
punk@13 11
punk@13 12 // The above copyright notice and this permission notice shall be included in
punk@13 13 // all copies or substantial portions of the Software.
punk@13 14
punk@13 15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
punk@13 16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
punk@13 17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
punk@13 18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
punk@13 19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
punk@13 20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
punk@13 21 // THE SOFTWARE.
punk@13 22
punk@13 23 // Author: Kermin Fleming kfleming@mit.edu
punk@13 24
punk@13 25 import Connectable::*;
punk@13 26 import GetPut::*;
punk@13 27 import ClientServer::*;
punk@13 28 import FIFO::*;
punk@15 29 import SpecialFIFOs::*;
punk@13 30
punk@13 31 //AWB includes
punk@13 32 `include "asim/provides/low_level_platform_interface.bsh"
punk@13 33 `include "asim/provides/soft_connections.bsh"
punk@13 34 `include "asim/provides/common_services.bsh"
punk@13 35
punk@13 36 //Local includes
punk@13 37 `include "asim/provides/audio_pipe_types.bsh" //provides Audio Pipeline interface
punk@13 38 `include "asim/provides/core.bsh"
punk@15 39 `include "asim/provides/processor_library.bsh"
punk@15 40 `include "asim/provides/fpga_components.bsh"
punk@13 41 `include "asim/rrr/remote_client_stub_AUDIOCORERRR.bsh"
punk@15 42 //`include "asim/rrr/remote_server_stub_AUDIOCORERRR.bsh"
punk@13 43
punk@13 44 module [CONNECTED_MODULE] mkConnectedApplication ();
punk@13 45 Core core <- mkCore;
punk@13 46 Reg#(int) cycle <- mkReg(0);
punk@13 47
punk@13 48 //External memory
punk@13 49 // I'm not comfortable assuming that the memory subsystem is in order
punk@13 50 // So I'll insert a completion buffer here.
punk@15 51 ClientStub_AUDIOCORERRR client_stub <- mkClientStub_AUDIOCORERRR();
punk@13 52 // Make this big enough so that several outstanding requests may be supported
punk@13 53 FIFO#(Bit#(MainMemTagSz)) tags <- mkSizedFIFO(8);
punk@13 54
punk@13 55 // this is for the tracing
punk@13 56 rule printCycles;
punk@13 57 cycle <= cycle+1;
punk@13 58 $fdisplay(stderr, " => Cycle = %d", cycle);
punk@13 59 endrule
punk@13 60
punk@13 61 rule sendMemReq;
punk@13 62 let coreReq <- core.mmem_client.request.get;
punk@13 63 case (coreReq) matches
punk@13 64 tagged LoadReq .load: begin
punk@13 65 //Allocate ROB space
punk@13 66 client_stub.makeRequest_MemoryRequestLoad(load.addr);
punk@13 67 tags.enq(load.tag);
punk@13 68 end
punk@13 69 tagged StoreReq .store: begin
punk@13 70 client_stub.makeRequest_MemoryRequestStore(store.addr,store.data);
punk@13 71 end
punk@13 72 endcase
punk@13 73 endrule
punk@13 74
punk@13 75 rule receiveMemResp;
punk@13 76 let memResp <- client_stub.getResponse_MemoryRequestLoad();
punk@13 77 tags.deq;
punk@13 78 core.mmem_client.response.put(tagged LoadResp {data:memResp,
punk@13 79 tag: tags.first});
punk@13 80 endrule
punk@13 81
punk@13 82 // this isn't particularly correct as it doesn't actually connect the processor interfaces, but this should allow me to verify the data path before fully blending the two items together.
punk@13 83
punk@13 84 rule feedOutput;
punk@13 85 let pipelineData <- core.sampleOutput.get();
punk@13 86 AudioProcessorControl endOfFileTag = EndOfFile;
punk@13 87 AudioProcessorControl sampleTag = Data;
punk@13 88
punk@15 89 // case (pipelineData) matches
punk@15 90 // tagged EndOfFile:
punk@15 91 client_stub.makeRequest_SendProcessedStream(zeroExtend(pack(endOfFileTag)),?);
punk@15 92 // tagged Sample .sample:client_stub.makeRequest_SendProcessedStream(zeroExtend(pack(sampleTag)), zeroExtend(pack(sample)));
punk@15 93 // endcase
punk@13 94 endrule
punk@13 95
punk@13 96 endmodule