diff modules/bluespec/Pygar/core/audioCorePipeline.bsv @ 36:99519a031813 pygar svn.37

[svn r37] moved the server into audioCorePipeline
author punk
date Tue, 04 May 2010 18:54:54 -0400
parents 2c8166d205d5
children 0475235d1513
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line diff
     1.1 --- a/modules/bluespec/Pygar/core/audioCorePipeline.bsv	Tue May 04 12:14:24 2010 -0400
     1.2 +++ b/modules/bluespec/Pygar/core/audioCorePipeline.bsv	Tue May 04 18:54:54 2010 -0400
     1.3 @@ -44,7 +44,7 @@
     1.4  `include "asim/dict/VDEV_SCRATCH.bsh"
     1.5  
     1.6  `include "asim/rrr/remote_client_stub_AUDIOCORERRR.bsh"
     1.7 -//`include "asim/rrr/remote_server_stub_AUDIOCORERRR.bsh"
     1.8 +`include "asim/rrr/remote_server_stub_AUDIOCORERRR.bsh"
     1.9  
    1.10  module [CONNECTED_MODULE] mkConnectedApplication ();
    1.11     Core core <- mkCore;
    1.12 @@ -60,6 +60,12 @@
    1.13    // Make this big enough so that several outstanding requests may be supported
    1.14    FIFO#(Bit#(MainMemTagSz)) tags <- mkSizedFIFO(8);
    1.15  
    1.16 +   //-----------------------------------------------------------
    1.17 +   // Debug port
    1.18 +   
    1.19 +   ServerStub_AUDIOCORERRR server_stub <- mkServerStub_AUDIOCORERRR();   
    1.20 +
    1.21 +   
    1.22    // this is for the tracing
    1.23    rule printCycles;
    1.24      cycle <= cycle+1;
    1.25 @@ -99,4 +105,20 @@
    1.26       endcase
    1.27     endrule
    1.28  
    1.29 +   //*****  SERVER Side  *****
    1.30 +
    1.31 +   rule feedInput;
    1.32 +     let command <- server_stub.acceptRequest_SendUnprocessedStream();
    1.33 +     AudioProcessorControl ctrl = unpack(truncate(command.ctrl));
    1.34 +     if(ctrl == EndOfFile)
    1.35 +	begin
    1.36 +	  $display("lsp: PROCESSOR received EOF   ");
    1.37 +          core.sampleInput.put(tagged EndOfFile);
    1.38 +       end
    1.39 +     else 
    1.40 +	begin
    1.41 +	  $display("lsp: PROCESSOR received Data   ");
    1.42 +          core.sampleInput.put(tagged Sample unpack(truncate(command.sample)));
    1.43 +       end
    1.44 +   endrule     
    1.45  endmodule