Mercurial > pygar
changeset 33:2c8166d205d5 pygar svn.34
[svn r34] uses scratchpad, set up for audio through c
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1.1 --- a/config/pm/Pygar/audio_core/audio_core_exe.apm Mon May 03 09:53:56 2010 -0400 1.2 +++ b/config/pm/Pygar/audio_core/audio_core_exe.apm Tue May 04 10:13:53 2010 -0400 1.3 @@ -87,6 +87,7 @@ 1.4 core=Audio Processor Core 1.5 funcp_base_types=Functional Partition Base Types 1.6 audio_pipe_types=Simple Audio Processor Control Types 1.7 +path_types=Audio Path Types 1.8 1.9 [Audio Processor Core/Requires] 1.10 processor_library=External Trace Processor Library 1.11 @@ -95,12 +96,9 @@ 1.12 instruction_cache=Blocking Instruction Cache 1.13 mem_arb=Round-robin memory arbiter 1.14 1.15 - 1.16 - 1.17 [Simple Audio Processor Control Types] 1.18 File=modules/bluespec/Pygar/core/audio_pipe_types.awb 1.19 1.20 - 1.21 [Trace Functions] 1.22 File=modules/bluespec/Pygar/core/trace.awb 1.23 1.24 @@ -109,3 +107,6 @@ 1.25 1.26 [External Trace Processor Library] 1.27 File=modules/bluespec/Pygar/lab4/audio_processor_library.awb 1.28 + 1.29 +[Audio Path Types] 1.30 +File=modules/bluespec/Pygar/core/path_types.awb
2.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 2.2 +++ b/modules/bluespec/Pygar/core/AudioCore.dic Tue May 04 10:13:53 2010 -0400 2.3 @@ -0,0 +1,4 @@ 2.4 +def VDEV.SCRATCH.MEMORY "program.0/program.vmh"; 2.5 + 2.6 + 2.7 +
3.1 --- a/modules/bluespec/Pygar/core/AudioCoreRRR.cpp Mon May 03 09:53:56 2010 -0400 3.2 +++ b/modules/bluespec/Pygar/core/AudioCoreRRR.cpp Tue May 04 10:13:53 2010 -0400 3.3 @@ -62,6 +62,7 @@ 3.4 // RRR service methods 3.5 // 3.6 3.7 +/* Not used by scratchpad 3.8 UINT32 3.9 AUDIOCORERRR_SERVER_CLASS::MemoryRequestLoad (UINT32 address) 3.10 { 3.11 @@ -86,6 +87,7 @@ 3.12 3.13 memory->Write(0,(UINT64) address, sizeof(UINT32), &data); 3.14 } 3.15 +*/ 3.16 3.17 void 3.18
4.1 --- a/modules/bluespec/Pygar/core/AudioCoreRRR.h Mon May 03 09:53:56 2010 -0400 4.2 +++ b/modules/bluespec/Pygar/core/AudioCoreRRR.h Tue May 04 10:13:53 2010 -0400 4.3 @@ -41,8 +41,10 @@ 4.4 // RRR service methods 4.5 // 4.6 4.7 + /* Not Used by ScratchPad 4.8 UINT32 MemoryRequestLoad (UINT32 address); 4.9 void MemoryRequestStore (UINT32 address, UINT32 data); 4.10 + */ 4.11 4.12 void SendProcessedStream(UINT16 control, UINT16 data0); 4.13 };
5.1 --- a/modules/bluespec/Pygar/core/AudioCoreRRR.rrr Mon May 03 09:53:56 2010 -0400 5.2 +++ b/modules/bluespec/Pygar/core/AudioCoreRRR.rrr Tue May 04 10:13:53 2010 -0400 5.3 @@ -9,8 +9,10 @@ 5.4 server sw (cpp, method) <- hw (bsv, connection) 5.5 { 5.6 method SendProcessedStream (in UINT32[32] ctrl, in UINT32[32] sample); 5.7 - method MemoryRequestLoad (in UINT32[32] address, out UINT32[32] value); 5.8 - method MemoryRequestStore (in UINT32[32] address, in UINT32[32] value); 5.9 + 5.10 +// Not used by SCRATCHPAD 5.11 +// method MemoryRequestLoad (in UINT32[32] address, out UINT32[32] value); 5.12 +// method MemoryRequestStore (in UINT32[32] address, in UINT32[32] value); 5.13 }; 5.14 5.15 };
6.1 --- a/modules/bluespec/Pygar/core/PathTypes.bsv Mon May 03 09:53:56 2010 -0400 6.2 +++ b/modules/bluespec/Pygar/core/PathTypes.bsv Tue May 04 10:13:53 2010 -0400 6.3 @@ -1,6 +1,8 @@ 6.4 import Trace::*; 6.5 import Vector::*; 6.6 6.7 +`include "asim/provides/audio_pipe_types.bsh" 6.8 + 6.9 `define MAX_VOICES 4 6.10 `define MAX_CORES 16 6.11 `define MAX_PATH_IDS 18 6.12 @@ -10,9 +12,9 @@ 6.13 6.14 typedef Bit#(32) MemAddr; 6.15 typedef Int#(TLog#(`MAX_PATH_IDS)) PathId; 6.16 -typedef Int#(24) Sample; 6.17 +//typedef Int#(16) Sample; 6.18 typedef Int#(TLog#(`MAX_VOICES)) VoiceId; 6.19 - 6.20 +typedef Bit#(8) Volume; // This is arbitrarily set to 8 bits or max val 256 6.21 6.22 //The mixer is identified as PathId 0, path end is max 6.23 PathId mixerId = 0; 6.24 @@ -27,5 +29,13 @@ 6.25 VoiceId voice; 6.26 MemAddr startAddr; 6.27 CorePath route; 6.28 + Volume outVol; 6.29 } FullPath deriving (Bits, Eq); 6.30 6.31 +typedef Maybe#(AudioProcessorUnit) AudioPipeUnit; // deriving (Bits, Eq); 6.32 + 6.33 +typedef struct 6.34 +{ 6.35 + VoiceId voice; 6.36 + AudioPipeUnit data; 6.37 +} AudioStream deriving (Bits, Eq);
7.1 --- a/modules/bluespec/Pygar/core/Processor.bsv Mon May 03 09:53:56 2010 -0400 7.2 +++ b/modules/bluespec/Pygar/core/Processor.bsv Tue May 04 10:13:53 2010 -0400 7.3 @@ -250,10 +250,13 @@ 7.4 FIFO#(PCStat) pcQ <-mkSizedFIFO(3); 7.5 SFIFO#(WBResult, Rindx) wbQ <-mkSFIFO(findwbf); 7.6 7.7 + // NEED TO ADD CAPABILITY FOR RESET (should be able to just say if I get valid in and these are flagged, clear them. 7.8 Reg#(Bit#(32)) cp0_tohost <- mkReg(0); 7.9 Reg#(Bit#(32)) cp0_fromhost <- mkReg(0); 7.10 Reg#(Bool) cp0_statsEn <- mkReg(False); 7.11 - 7.12 + Reg#(Bool) cp0_audioEOF <- mkReg(False); // Register to let code that EOF is reached 7.13 + Reg#(Bool) cp0_progComp <- mkReg(False); // Register to let processor know that the program is complete (as this terminates) 7.14 + 7.15 // Memory request/response state 7.16 7.17 FIFO#(InstReq) instReqQ <- mkBFIFO1(); 7.18 @@ -488,11 +491,14 @@ 7.19 7.20 // -- Cop0 ------------------------------------------------------ 7.21 7.22 - tagged MTC0 .it : 7.23 + tagged MTC0 .it : //Recieve things from host computer 7.24 begin 7.25 + $display( " PROCESSOR MTC0 call\n"); 7.26 case ( it.cop0dst ) 7.27 5'd10 : cp0_statsEn <= unpack(truncate(rf.rd1(it.rsrc))); 7.28 5'd21 : cp0_tohost <= truncate(rf.rd1(it.rsrc)); 7.29 + 5'd26 : cp0_progComp <= unpack(truncate(rf.rd1(it.rsrc))); //states audio program completed and termination okay 7.30 + 5'd27 : outAudioFifo.enq(tagged Sample unpack(truncate(rf.rd1(it.rsrc)))); //Bit size is 16 not 32 7.31 default : 7.32 $display( " RTL-ERROR : %m : Illegal MTC0 cop0dst register!" ); 7.33 endcase 7.34 @@ -500,13 +506,27 @@ 7.35 end 7.36 7.37 //this is host stuff? 7.38 - tagged MFC0 .it : 7.39 + tagged MFC0 .it : //Things out 7.40 begin 7.41 + $display( " PROCESSOR MFC0 call\n"); 7.42 case ( it.cop0src ) 7.43 // not actually an ALU instruction but don't have the format otherwise 7.44 5'd10 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(cp0_statsEn)) }); 7.45 5'd20 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_fromhost }); 7.46 5'd21 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_tohost }); 7.47 + 5'd25 : begin 7.48 + $display( "**** EOF Requested\n "); 7.49 + wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(cp0_audioEOF)) }); // Reading clears bit 7.50 + cp0_audioEOF <= False; 7.51 + end 7.52 + 5'd28 : begin 7.53 + $display( "***** Reqesting Sample \n"); 7.54 + let sample = inAudioFifo.first(); // is this going to cause perf. delay? 7.55 + if (sample matches tagged Sample .audio) // if it is EOF another rule sets the cp0_audioEOF 7.56 + wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(audio)) }); // do I need pack? 7.57 + else $display ( "Audio File EOF Reached. Invalid sample request."); 7.58 + inAudioFifo.deq(); 7.59 + end 7.60 default : 7.61 $display( " RTL-ERROR : %m : Illegal MFC0 cop0src register!" ); 7.62 endcase 7.63 @@ -572,10 +592,22 @@ 7.64 endrule 7.65 7.66 // for now, we don't do anything. 7.67 - rule connectAudioReqResp; 7.68 +// rule connectAudioReqResp; 7.69 // $display("rlm: PROCESSOR copies a datum\n"); 7.70 - outAudioFifo.enq(inAudioFifo.first()); 7.71 - inAudioFifo.deq; 7.72 +// outAudioFifo.enq(inAudioFifo.first()); 7.73 +// inAudioFifo.deq; 7.74 +// endrule 7.75 + 7.76 + rule flagAudioEnd (inAudioFifo.first() matches tagged EndOfFile); 7.77 + $display (" Proc Says End Audio Flag Set "); 7.78 + cp0_audioEOF <= True; 7.79 + inAudioFifo.deq; 7.80 + endrule 7.81 + 7.82 + rule sendAudioEnd (cp0_progComp); 7.83 + $display (" PROCESSOR Says Program Complete "); 7.84 + outAudioFifo.enq(tagged EndOfFile); 7.85 + cp0_progComp <= False; //only send one. And functions to reset 7.86 endrule 7.87 7.88 // Server items & rules: 7.89 @@ -585,12 +617,12 @@ 7.90 AudioProcessorControl ctrl = unpack(truncate(command.ctrl)); 7.91 if(ctrl == EndOfFile) 7.92 begin 7.93 -// $display("lsp: PROCESSOR received EOF "); 7.94 + $display("lsp: PROCESSOR received EOF "); 7.95 inAudioFifo.enq(tagged EndOfFile); 7.96 end 7.97 else 7.98 begin 7.99 -// $display("lsp: PROCESSOR received Data "); 7.100 + $display("lsp: PROCESSOR received Data "); 7.101 inAudioFifo.enq(tagged Sample unpack(truncate(command.sample))); 7.102 end 7.103 endrule
8.1 --- a/modules/bluespec/Pygar/core/RoutingTable.bsv Mon May 03 09:53:56 2010 -0400 8.2 +++ b/modules/bluespec/Pygar/core/RoutingTable.bsv Tue May 04 10:13:53 2010 -0400 8.3 @@ -3,12 +3,13 @@ 8.4 import PathTypes::*; 8.5 8.6 function FullPath genEmptyPaths (Integer a) ; 8.7 - FullPath empt = FullPath {voice: fromInteger(a), startAddr: 0, route: emptyCore}; 8.8 + FullPath empt = FullPath {voice: fromInteger(a), startAddr: 0, route: emptyCore, outVol: 0}; 8.9 return (empt); 8.10 endfunction 8.11 8.12 interface RoutingTable; 8.13 method FullPath getPath(Integer voiceNo); 8.14 + method Vector#(`MAX_VOICES, Volume) getMixerScalars(); 8.15 endinterface 8.16 8.17 module mkRoutingTable(RoutingTable); 8.18 @@ -25,9 +26,10 @@ 8.19 routeTable[0].startAddr = 0; //where is this really going to come from? 8.20 routeTable[0].route[0] = 3; 8.21 routeTable[0].route[1] = mixerId; 8.22 + routeTable[0].outVol = 200; 8.23 //rest are already initialized toinvalid 8.24 8.25 - // or if you just want to update a straight list, this longer emplate works. 8.26 + // or if you just want to update a straight list, this longer template works. 8.27 function CorePath createVoice1Route(); 8.28 CorePath outPath = emptyCore; 8.29 8.30 @@ -40,13 +42,21 @@ 8.31 return outPath; 8.32 endfunction 8.33 routeTable[1].route = createVoice1Route; 8.34 - routeTable[1].startAddr = 0; 8.35 + routeTable[1].startAddr = 0; 8.36 + routeTable[1].outVol = 200; 8.37 8.38 //remaining voices are all initialized to empty. 8.39 8.40 - method FullPath getPath(Integer a); 8.41 + method FullPath getPath(Integer a); 8.42 return routeTable[a]; 8.43 endmethod 8.44 + 8.45 + method Vector#(`MAX_VOICES, Volume) getMixerScalars(); 8.46 + Vector#(`MAX_VOICES, Volume) scalars = newVector(); 8.47 + for(Integer i = 0; i < `MAX_VOICES; i = i+1) 8.48 + scalars[i] = routeTable[i].outVol; 8.49 + return scalars; 8.50 + endmethod 8.51 8.52 endmodule 8.53
9.1 --- a/modules/bluespec/Pygar/core/audioCorePipeline.bsv Mon May 03 09:53:56 2010 -0400 9.2 +++ b/modules/bluespec/Pygar/core/audioCorePipeline.bsv Tue May 04 10:13:53 2010 -0400 9.3 @@ -35,9 +35,14 @@ 9.4 9.5 //Local includes 9.6 `include "asim/provides/audio_pipe_types.bsh" //provides Audio Pipeline interface 9.7 +`include "asim/provides/path_types.bsh" 9.8 `include "asim/provides/core.bsh" 9.9 `include "asim/provides/processor_library.bsh" 9.10 `include "asim/provides/fpga_components.bsh" 9.11 +`include "asim/provides/scratchpad_memory.bsh" 9.12 +`include "asim/provides/mem_services.bsh" 9.13 +`include "asim/dict/VDEV_SCRATCH.bsh" 9.14 + 9.15 `include "asim/rrr/remote_client_stub_AUDIOCORERRR.bsh" 9.16 //`include "asim/rrr/remote_server_stub_AUDIOCORERRR.bsh" 9.17 9.18 @@ -47,7 +52,10 @@ 9.19 9.20 //External memory 9.21 // I'm not comfortable assuming that the memory subsystem is in order 9.22 - // So I'll insert a completion buffer here. 9.23 + // So I'll insert a completion buffer here. 9.24 + MEMORY_IFC#(Bit#(18), Bit#(32)) memory <- mkScratchpad(`VDEV_SCRATCH_MEMORY, SCRATCHPAD_CACHED); //Services Memory items 9.25 + 9.26 + // Services Samples 9.27 ClientStub_AUDIOCORERRR client_stub <- mkClientStub_AUDIOCORERRR(); 9.28 // Make this big enough so that several outstanding requests may be supported 9.29 FIFO#(Bit#(MainMemTagSz)) tags <- mkSizedFIFO(8); 9.30 @@ -63,24 +71,22 @@ 9.31 case (coreReq) matches 9.32 tagged LoadReq .load: begin 9.33 //Allocate ROB space 9.34 - client_stub.makeRequest_MemoryRequestLoad(load.addr); 9.35 + memory.readReq(truncate(load.addr>>2)); 9.36 tags.enq(load.tag); 9.37 end 9.38 tagged StoreReq .store: begin 9.39 - client_stub.makeRequest_MemoryRequestStore(store.addr,store.data); 9.40 + memory.write(truncate(store.addr>>2),store.data); 9.41 end 9.42 endcase 9.43 endrule 9.44 9.45 rule receiveMemResp; 9.46 - let memResp <- client_stub.getResponse_MemoryRequestLoad(); 9.47 + let memResp <- memory.readRsp(); 9.48 tags.deq; 9.49 core.mmem_client.response.put(tagged LoadResp {data:memResp, 9.50 tag: tags.first}); 9.51 endrule 9.52 9.53 - // this isn't particularly correct as it doesn't actually connect the processor interfaces, but this should allow me to verify the data path before fully blending the two items together. 9.54 - 9.55 rule feedOutput; 9.56 let pipelineData <- core.sampleOutput.get(); 9.57 AudioProcessorControl endOfFileTag = EndOfFile;
10.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 10.2 +++ b/modules/bluespec/Pygar/core/audioPipe.bsv Tue May 04 10:13:53 2010 -0400 10.3 @@ -0,0 +1,106 @@ 10.4 +// The MIT License 10.5 + 10.6 +// Copyright (c) 2009 Massachusetts Institute of Technology 10.7 + 10.8 +// Permission is hereby granted, free of charge, to any person obtaining a copy 10.9 +// of this software and associated documentation files (the "Software"), to deal 10.10 +// in the Software without restriction, including without limitation the rights 10.11 +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10.12 +// copies of the Software, and to permit persons to whom the Software is 10.13 +// furnished to do so, subject to the following conditions: 10.14 + 10.15 +// The above copyright notice and this permission notice shall be included in 10.16 +// all copies or substantial portions of the Software. 10.17 + 10.18 +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 10.19 +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 10.20 +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 10.21 +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 10.22 +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 10.23 +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 10.24 +// THE SOFTWARE. 10.25 + 10.26 +// Author: Kermin Fleming kfleming@mit.edu 10.27 + 10.28 +import Connectable::*; 10.29 +import GetPut::*; 10.30 +import ClientServer::*; 10.31 +import FIFO::*; 10.32 +import SpecialFIFOs::*; 10.33 + 10.34 +//AWB includes 10.35 +`include "asim/provides/low_level_platform_interface.bsh" 10.36 +`include "asim/provides/soft_connections.bsh" 10.37 +`include "asim/provides/common_services.bsh" 10.38 + 10.39 +//Local includes 10.40 +`include "asim/provides/audio_pipe_types.bsh" //provides Audio Pipeline interface 10.41 +`include "asim/provides/core.bsh" 10.42 +`include "asim/provides/processor_library.bsh" 10.43 +`include "asim/provides/fpga_components.bsh" 10.44 +`include "asim/provides/scratchpad_memory.bsh" 10.45 +`include "asim/provides/mem_services.bsh" 10.46 +`include "asim/dict/VDEV_SCRATCH.bsh" 10.47 + 10.48 +`include "asim/rrr/remote_client_stub_AUDIOCORERRR.bsh" 10.49 +//`include "asim/rrr/remote_server_stub_AUDIOCORERRR.bsh" 10.50 + 10.51 +function 10.52 +module [CONNECTED_MODULE] mkConnectedApplication (); 10.53 + Core core <- mkCore; 10.54 + Reg#(int) cycle <- mkReg(0); 10.55 + 10.56 + 10.57 + //get volumes 10.58 + //mkMixer(); 10.59 + 10.60 + //External memory 10.61 + // I'm not comfortable assuming that the memory subsystem is in order 10.62 + // So I'll insert a completion buffer here. 10.63 + MEMORY_IFC#(Bit#(18), Bit#(32)) memory <- mkScratchpad(`VDEV_SCRATCH_MEMORY, SCRATCHPAD_CACHED); //Services Memory items 10.64 + 10.65 + // Services Samples 10.66 + ClientStub_AUDIOCORERRR client_stub <- mkClientStub_AUDIOCORERRR(); 10.67 + // Make this big enough so that several outstanding requests may be supported 10.68 + FIFO#(Bit#(MainMemTagSz)) tags <- mkSizedFIFO(8); 10.69 + 10.70 + // this is for the tracing 10.71 + rule printCycles; 10.72 + cycle <= cycle+1; 10.73 + $fdisplay(stderr, " => Cycle = %d", cycle); 10.74 + endrule 10.75 + 10.76 + rule sendMemReq; 10.77 + let coreReq <- core.mmem_client.request.get; 10.78 + case (coreReq) matches 10.79 + tagged LoadReq .load: begin 10.80 + //Allocate ROB space 10.81 + memory.readReq(truncate(load.addr>>2)); 10.82 + tags.enq(load.tag); 10.83 + end 10.84 + tagged StoreReq .store: begin 10.85 + memory.write(truncate(store.addr>>2),store.data); 10.86 + end 10.87 + endcase 10.88 + endrule 10.89 + 10.90 + rule receiveMemResp; 10.91 + let memResp <- memory.readRsp(); 10.92 + tags.deq; 10.93 + core.mmem_client.response.put(tagged LoadResp {data:memResp, 10.94 + tag: tags.first}); 10.95 + endrule 10.96 + 10.97 + rule feedOutput; 10.98 + let pipelineData <- core.sampleOutput.get(); 10.99 + AudioProcessorControl endOfFileTag = EndOfFile; 10.100 + AudioProcessorControl sampleTag = Data; 10.101 + 10.102 + case (pipelineData) matches 10.103 + tagged EndOfFile: 10.104 + client_stub.makeRequest_SendProcessedStream(zeroExtend(pack(endOfFileTag)),?); 10.105 + tagged Sample .sample:client_stub.makeRequest_SendProcessedStream(zeroExtend(pack(sampleTag)), zeroExtend(pack(sample))); 10.106 + endcase 10.107 + endrule 10.108 + 10.109 +endmodule
11.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 11.2 +++ b/modules/bluespec/Pygar/core/audioPipe.bsv~ Tue May 04 10:13:53 2010 -0400 11.3 @@ -0,0 +1,103 @@ 11.4 +// The MIT License 11.5 + 11.6 +// Copyright (c) 2009 Massachusetts Institute of Technology 11.7 + 11.8 +// Permission is hereby granted, free of charge, to any person obtaining a copy 11.9 +// of this software and associated documentation files (the "Software"), to deal 11.10 +// in the Software without restriction, including without limitation the rights 11.11 +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11.12 +// copies of the Software, and to permit persons to whom the Software is 11.13 +// furnished to do so, subject to the following conditions: 11.14 + 11.15 +// The above copyright notice and this permission notice shall be included in 11.16 +// all copies or substantial portions of the Software. 11.17 + 11.18 +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 11.19 +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 11.20 +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 11.21 +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 11.22 +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 11.23 +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 11.24 +// THE SOFTWARE. 11.25 + 11.26 +// Author: Kermin Fleming kfleming@mit.edu 11.27 + 11.28 +import Connectable::*; 11.29 +import GetPut::*; 11.30 +import ClientServer::*; 11.31 +import FIFO::*; 11.32 +import SpecialFIFOs::*; 11.33 + 11.34 +//AWB includes 11.35 +`include "asim/provides/low_level_platform_interface.bsh" 11.36 +`include "asim/provides/soft_connections.bsh" 11.37 +`include "asim/provides/common_services.bsh" 11.38 + 11.39 +//Local includes 11.40 +`include "asim/provides/audio_pipe_types.bsh" //provides Audio Pipeline interface 11.41 +`include "asim/provides/core.bsh" 11.42 +`include "asim/provides/processor_library.bsh" 11.43 +`include "asim/provides/fpga_components.bsh" 11.44 +`include "asim/provides/scratchpad_memory.bsh" 11.45 +`include "asim/provides/mem_services.bsh" 11.46 +`include "asim/dict/VDEV_SCRATCH.bsh" 11.47 + 11.48 +`include "asim/rrr/remote_client_stub_AUDIOCORERRR.bsh" 11.49 +//`include "asim/rrr/remote_server_stub_AUDIOCORERRR.bsh" 11.50 + 11.51 +module [CONNECTED_MODULE] mkConnectedApplication (); 11.52 + Core core <- mkCore; 11.53 + Reg#(int) cycle <- mkReg(0); 11.54 + 11.55 + //mkMixer(); 11.56 + 11.57 + //External memory 11.58 + // I'm not comfortable assuming that the memory subsystem is in order 11.59 + // So I'll insert a completion buffer here. 11.60 + MEMORY_IFC#(Bit#(18), Bit#(32)) memory <- mkScratchpad(`VDEV_SCRATCH_MEMORY, SCRATCHPAD_CACHED); //Services Memory items 11.61 + 11.62 + // Services Samples 11.63 + ClientStub_AUDIOCORERRR client_stub <- mkClientStub_AUDIOCORERRR(); 11.64 + // Make this big enough so that several outstanding requests may be supported 11.65 + FIFO#(Bit#(MainMemTagSz)) tags <- mkSizedFIFO(8); 11.66 + 11.67 + // this is for the tracing 11.68 + rule printCycles; 11.69 + cycle <= cycle+1; 11.70 + $fdisplay(stderr, " => Cycle = %d", cycle); 11.71 + endrule 11.72 + 11.73 + rule sendMemReq; 11.74 + let coreReq <- core.mmem_client.request.get; 11.75 + case (coreReq) matches 11.76 + tagged LoadReq .load: begin 11.77 + //Allocate ROB space 11.78 + memory.readReq(truncate(load.addr>>2)); 11.79 + tags.enq(load.tag); 11.80 + end 11.81 + tagged StoreReq .store: begin 11.82 + memory.write(truncate(store.addr>>2),store.data); 11.83 + end 11.84 + endcase 11.85 + endrule 11.86 + 11.87 + rule receiveMemResp; 11.88 + let memResp <- memory.readRsp(); 11.89 + tags.deq; 11.90 + core.mmem_client.response.put(tagged LoadResp {data:memResp, 11.91 + tag: tags.first}); 11.92 + endrule 11.93 + 11.94 + rule feedOutput; 11.95 + let pipelineData <- core.sampleOutput.get(); 11.96 + AudioProcessorControl endOfFileTag = EndOfFile; 11.97 + AudioProcessorControl sampleTag = Data; 11.98 + 11.99 + case (pipelineData) matches 11.100 + tagged EndOfFile: 11.101 + client_stub.makeRequest_SendProcessedStream(zeroExtend(pack(endOfFileTag)),?); 11.102 + tagged Sample .sample:client_stub.makeRequest_SendProcessedStream(zeroExtend(pack(sampleTag)), zeroExtend(pack(sample))); 11.103 + endcase 11.104 + endrule 11.105 + 11.106 +endmodule
12.1 --- a/modules/bluespec/Pygar/core/audio_core_pipe.awb Mon May 03 09:53:56 2010 -0400 12.2 +++ b/modules/bluespec/Pygar/core/audio_core_pipe.awb Tue May 04 10:13:53 2010 -0400 12.3 @@ -4,6 +4,7 @@ 12.4 %provides connected_application 12.5 12.6 %requires audio_pipe_types 12.7 +%requires path_types 12.8 %requires core 12.9 %requires funcp_simulated_memory 12.10 %requires funcp_base_types 12.11 @@ -18,6 +19,8 @@ 12.12 %sources -t CPP -v PRIVATE AudioCoreRRR.cpp 12.13 %sources -t H -v PUBLIC AudioCoreRRR.h 12.14 %sources -t RRR -v PUBLIC AudioCoreRRR.rrr 12.15 +%sources -t DICT -v PUBLIC AudioCore.dic 12.16 + 12.17 %sources -t CPP -v PRIVATE SndfileWavUtil.cpp 12.18 %sources -t H -v PUBLIC SndfileWavUtil.h 12.19 %library /usr/lib/libsndfile.so
13.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 13.2 +++ b/modules/bluespec/Pygar/core/mixer.bsv Tue May 04 10:13:53 2010 -0400 13.3 @@ -0,0 +1,69 @@ 13.4 +// The MIT License 13.5 + 13.6 +// Copyright (c) 2009 Massachusetts Institute of Technology 13.7 + 13.8 +// Permission is hereby granted, free of charge, to any person obtaining a copy 13.9 +// of this software and associated documentation files (the "Software"), to deal 13.10 +// in the Software without restriction, including without limitation the rights 13.11 +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 13.12 +// copies of the Software, and to permit persons to whom the Software is 13.13 +// furnished to do so, subject to the following conditions: 13.14 + 13.15 +// The above copyright notice and this permission notice shall be included in 13.16 +// all copies or substantial portions of the Software. 13.17 + 13.18 +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 13.19 +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 13.20 +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 13.21 +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 13.22 +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 13.23 +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 13.24 +// THE SOFTWARE. 13.25 + 13.26 +import Connectable::*; 13.27 +import GetPut::*; 13.28 +import ClientServer::*; 13.29 +import Processor::*; 13.30 +import MemArb::*; 13.31 +import MemTypes::*; 13.32 + 13.33 +//AWB includes 13.34 +`include "asim/provides/low_level_platform_interface.bsh" 13.35 +`include "asim/provides/soft_connections.bsh" 13.36 +`include "asim/provides/common_services.bsh" 13.37 + 13.38 +// Local includes 13.39 +`include "asim/provides/processor_library.bsh" 13.40 +`include "asim/provides/audio_pipe_types.bsh" 13.41 +`include "asim/provides/path_types.bsh" 13.42 + 13.43 +interface PutMixerIn; 13.44 + method Action sendVoiceIn(AudioStream voiceInput); 13.45 +endinterface 13.46 + 13.47 +interface Mixer#(Vector#(`MAX_VOICES, Volume)); 13.48 + interface PutMixerIn toMixer; 13.49 + interface Get#(AudioProcessorUnit) mixerOut; 13.50 +endinterface 13.51 + 13.52 + 13.53 +module [CONNECTED_MODULE] mkMixer( Mixer#(Vector(`MAX_VOICES, Volume))); 13.54 + // Instantiate the modules 13.55 + Vector#(`MAX_VOICES, FIFO#(AudioPipeUnit)) voicesIn <- newVector(); 13.56 + Vector#(`MAX_VOICES, Bool) voiceEnded <- replicate(False); 13.57 + 13.58 + FIFO#(AudioProcessorUnit) masterFifo <- mkFIFO(); 13.59 + 13.60 + rule processSample //implicit on all voiceFifos having data 13.61 + endrule 13.62 + 13.63 + // Internal connections 13.64 + 13.65 + interface PutMixerIn toMixer; 13.66 + method Action sendVoiceIn(AudioStream voiceInput); 13.67 + voicesIn[voiceInput.voice].enq(voiceInput.data); 13.68 + endmethod 13.69 + 13.70 + interface Get mixerOut = fifoToGet(masterFifo); 13.71 + 13.72 +endmodule
14.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 14.2 +++ b/modules/bluespec/Pygar/core/mixer.bsv~ Tue May 04 10:13:53 2010 -0400 14.3 @@ -0,0 +1,62 @@ 14.4 +// The MIT License 14.5 + 14.6 +// Copyright (c) 2009 Massachusetts Institute of Technology 14.7 + 14.8 +// Permission is hereby granted, free of charge, to any person obtaining a copy 14.9 +// of this software and associated documentation files (the "Software"), to deal 14.10 +// in the Software without restriction, including without limitation the rights 14.11 +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 14.12 +// copies of the Software, and to permit persons to whom the Software is 14.13 +// furnished to do so, subject to the following conditions: 14.14 + 14.15 +// The above copyright notice and this permission notice shall be included in 14.16 +// all copies or substantial portions of the Software. 14.17 + 14.18 +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14.19 +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 14.20 +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 14.21 +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 14.22 +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 14.23 +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 14.24 +// THE SOFTWARE. 14.25 + 14.26 +import Connectable::*; 14.27 +import GetPut::*; 14.28 +import ClientServer::*; 14.29 +import Processor::*; 14.30 +import MemArb::*; 14.31 +import MemTypes::*; 14.32 + 14.33 +//AWB includes 14.34 +`include "asim/provides/low_level_platform_interface.bsh" 14.35 +`include "asim/provides/soft_connections.bsh" 14.36 +`include "asim/provides/common_services.bsh" 14.37 + 14.38 +// Local includes 14.39 +`include "asim/provides/processor_library.bsh" 14.40 +`include "asim/provides/processor.bsh" 14.41 +`include "asim/provides/audio_pipe_types.bsh" 14.42 + 14.43 +interface Core; 14.44 + 14.45 + // Interface from core to main memory 14.46 + interface Client#(MainMemReq,MainMemResp) mmem_client; 14.47 + 14.48 + interface Get#(AudioProcessorUnit) sampleOutput; 14.49 + 14.50 +endinterface 14.51 + 14.52 +module [CONNECTED_MODULE] mkCore( Core ); 14.53 + 14.54 + // Instantiate the modules 14.55 + 14.56 + Proc proc <- mkProc(); 14.57 + ICache#(InstReq,InstResp) icache <- mkInstCache(); 14.58 + DCache#(DataReq,DataResp) dcache <- mkDataCache(); 14.59 + MemArb marb <- mkMemArb(); 14.60 + 14.61 + // Internal connections 14.62 + 14.63 + interface sampleOutput = proc.sampleOutput; 14.64 + 14.65 +endmodule
15.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 15.2 +++ b/modules/bluespec/Pygar/core/path_types.awb Tue May 04 10:13:53 2010 -0400 15.3 @@ -0,0 +1,10 @@ 15.4 +%name Audio Path Types 15.5 +%desc Provides definitions for audio portion of pipeline definitions 15.6 + 15.7 +%provides path_types 15.8 + 15.9 +%attributes PYGAR 15.10 + 15.11 +%public PathTypes.bsv 15.12 + 15.13 +
16.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 16.2 +++ b/modules/bluespec/Pygar/core/route_table.awb Tue May 04 10:13:53 2010 -0400 16.3 @@ -0,0 +1,12 @@ 16.4 +%name Routing Table 16.5 +%desc Outlines a set up for routes and mixing scalars 16.6 + 16.7 +%provides route_table 16.8 + 16.9 +%requires path_types 16.10 + 16.11 +%attributes PYGAR 16.12 + 16.13 +%public RouteTable.bsv 16.14 + 16.15 +
17.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 17.2 +++ b/modules/bluespec/Pygar/lab4/#Processor.bsv# Tue May 04 10:13:53 2010 -0400 17.3 @@ -0,0 +1,591 @@ 17.4 +/// The MIT License 17.5 + 17.6 +// Copyright (c) 2009 Massachusetts Institute of Technology 17.7 + 17.8 +// Permission is hereby granted, free of charge, to any person obtaining a copy 17.9 +// of this software and associated documentation files (the "Software"), to deal 17.10 +// in the Software without restriction, including without limitation the rights 17.11 +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 17.12 +// copies of the Software, and to permit persons to whom the Software is 17.13 +// furnished to do so, subject to the following conditions: 17.14 + 17.15 +// The above copyright notice and this permission notice shall be included in 17.16 +// all copies or substantial portions of the Software. 17.17 + 17.18 +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17.19 +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17.20 +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17.21 +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17.22 +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 17.23 +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 17.24 +// THE SOFTWARE. 17.25 + 17.26 +import Connectable::*; 17.27 +import GetPut::*; 17.28 +import ClientServer::*; 17.29 +import RegFile::*; 17.30 + 17.31 +import FIFO::*; 17.32 +import FIFOF::*; 17.33 +import SFIFO::*; 17.34 +import RWire::*; 17.35 + 17.36 +import BFIFO::*; 17.37 +import MemTypes::*; 17.38 +import ProcTypes::*; 17.39 +import BRegFile::*; 17.40 +import BranchPred::*; 17.41 +//import PathTypes::*; This is only there to force the debugging 17.42 + 17.43 +import Trace::*; 17.44 + 17.45 +//AWB includes 17.46 +`include "asim/provides/low_level_platform_interface.bsh" 17.47 +`include "asim/provides/soft_connections.bsh" 17.48 +`include "asim/provides/common_services.bsh" 17.49 + 17.50 +// Local includes 17.51 +`include "asim/provides/processor_library.bsh" 17.52 +`include "asim/rrr/remote_server_stub_PROCESSORSYSTEMRRR.bsh" 17.53 +`include "asim/provides/common_services.bsh" 17.54 +`include "asim/dict/STATS_PROCESSOR.bsh" 17.55 + 17.56 +interface ProcStats; 17.57 + interface Get#(Stat) num_cycles; 17.58 + interface Get#(Stat) num_inst; 17.59 +endinterface 17.60 + 17.61 +interface CPUToHost; 17.62 + method Bit#(32) cpuToHost(int req); 17.63 +endinterface 17.64 + 17.65 +interface Proc; 17.66 + 17.67 + // Interface from processor to caches 17.68 + interface Client#(DataReq,DataResp) dmem_client; 17.69 + interface Client#(InstReq,InstResp) imem_client; 17.70 + 17.71 + // Interface for enabling/disabling statistics on the rest of the core 17.72 + interface Get#(Bool) statsEn_get; 17.73 + 17.74 + // Interface for collecting statistics. 17.75 + interface ProcStats stats; 17.76 + 17.77 + // Interface to host 17.78 + interface CPUToHost tohost; 17.79 + 17.80 +endinterface 17.81 + 17.82 + 17.83 +typedef enum { PCgen, Exec, Writeback } Stage deriving(Eq,Bits); 17.84 + 17.85 +//----------------------------------------------------------- 17.86 +// Register file module 17.87 +//----------------------------------------------------------- 17.88 + 17.89 +interface BRFile; 17.90 + method Action wr( Rindx rindx, Bit#(32) data ); 17.91 + method Bit#(32) rd1( Rindx rindx ); 17.92 + method Bit#(32) rd2( Rindx rindx ); 17.93 +endinterface 17.94 + 17.95 +module mkBRFile( BRFile ); 17.96 + 17.97 + RegFile#(Rindx,Bit#(32)) rfile <- mkBRegFile(); 17.98 + 17.99 + method Action wr( Rindx rindx, Bit#(32) data ); 17.100 + rfile.upd( rindx, data ); 17.101 + endmethod 17.102 + 17.103 + method Bit#(32) rd1( Rindx rindx ); 17.104 + return ( rindx == 0 ) ? 0 : rfile.sub(rindx); 17.105 + endmethod 17.106 + 17.107 + method Bit#(32) rd2( Rindx rindx ); 17.108 + return ( rindx == 0 ) ? 0 : rfile.sub(rindx); 17.109 + endmethod 17.110 + 17.111 +endmodule 17.112 + 17.113 +//----------------------------------------------------------- 17.114 +// Helper functions 17.115 +//----------------------------------------------------------- 17.116 + 17.117 +function Bit#(32) slt( Bit#(32) val1, Bit#(32) val2 ); 17.118 + return zeroExtend( pack( signedLT(val1,val2) ) ); 17.119 +endfunction 17.120 + 17.121 +function Bit#(32) sltu( Bit#(32) val1, Bit#(32) val2 ); 17.122 + return zeroExtend( pack( val1 < val2 ) ); 17.123 +endfunction 17.124 + 17.125 +function Bit#(32) rshft( Bit#(32) val ); 17.126 + return zeroExtend(val[4:0]); 17.127 +endfunction 17.128 + 17.129 + 17.130 +//----------------------------------------------------------- 17.131 +// Find funct for wbQ 17.132 +//----------------------------------------------------------- 17.133 +function Bool findwbf(Rindx fVal, WBResult cmpVal); 17.134 + case (cmpVal) matches 17.135 + tagged WB_ALU {data:.res, dest:.rd} : 17.136 + return (fVal == rd); 17.137 + tagged WB_Load .rd : 17.138 + return (fVal == rd); 17.139 + tagged WB_Store .st : 17.140 + return False; 17.141 + tagged WB_Host .x : 17.142 + return False; 17.143 + endcase 17.144 +endfunction 17.145 + 17.146 + 17.147 +//----------------------------------------------------------- 17.148 +// Stall funct for wbQ 17.149 +//----------------------------------------------------------- 17.150 +function Bool stall(Instr inst, SFIFO#(WBResult, Rindx) f); 17.151 + case (inst) matches 17.152 + // -- Memory Ops ------------------------------------------------ 17.153 + tagged LW .it : 17.154 + return f.find(it.rbase); 17.155 + tagged SW {rsrc:.dreg, rbase:.addr, offset:.o} : 17.156 + return (f.find(addr) || f.find2(dreg)); 17.157 + 17.158 + // -- Simple Ops ------------------------------------------------ 17.159 + tagged ADDIU .it : return f.find(it.rsrc); 17.160 + tagged SLTI .it : return f.find(it.rsrc); 17.161 + tagged SLTIU .it : return f.find(it.rsrc); 17.162 + tagged ANDI .it : return f.find(it.rsrc); 17.163 + tagged ORI .it : return f.find(it.rsrc); 17.164 + tagged XORI .it : return f.find(it.rsrc); 17.165 + 17.166 + tagged LUI .it : return f.find(it.rdst); //this rds/wrs itself 17.167 + tagged SLL .it : return f.find(it.rsrc); 17.168 + tagged SRL .it : return f.find(it.rsrc); 17.169 + tagged SRA .it : return f.find(it.rsrc); 17.170 + tagged SLLV .it : return (f.find(it.rsrc) || f.find(it.rshamt)); 17.171 + tagged SRLV .it : return (f.find(it.rsrc) || f.find(it.rshamt)); 17.172 + tagged SRAV .it : return (f.find(it.rsrc) || f.find(it.rshamt)); 17.173 + tagged ADDU .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); 17.174 + tagged SUBU .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); 17.175 + tagged AND .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); 17.176 + tagged OR .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); 17.177 + tagged XOR .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); 17.178 + tagged NOR .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); 17.179 + tagged SLT .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); 17.180 + tagged SLTU .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); 17.181 + 17.182 + 17.183 + // -- Branches -------------------------------------------------- 17.184 + 17.185 + tagged BLEZ .it : return (f.find(it.rsrc)); 17.186 + tagged BGTZ .it : return (f.find(it.rsrc)); 17.187 + tagged BLTZ .it : return (f.find(it.rsrc)); 17.188 + tagged BGEZ .it : return (f.find(it.rsrc)); 17.189 + tagged BEQ .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); 17.190 + tagged BNE .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); 17.191 + 17.192 + // -- Jumps ----------------------------------------------------- 17.193 + 17.194 + tagged J .it : return False; 17.195 + tagged JR .it : return f.find(it.rsrc); 17.196 + tagged JALR .it : return f.find(it.rsrc); 17.197 + tagged JAL .it : return False; 17.198 + 17.199 + // -- Cop0 ------------------------------------------------------ 17.200 + 17.201 + tagged MTC0 .it : return f.find(it.rsrc); 17.202 + tagged MFC0 .it : return False; 17.203 + 17.204 + // -- Illegal --------------------------------------------------- 17.205 + 17.206 + default : return False; 17.207 + 17.208 + endcase 17.209 +endfunction 17.210 +//----------------------------------------------------------- 17.211 +// Reference processor 17.212 +//----------------------------------------------------------- 17.213 + 17.214 + 17.215 +//(* doc = "synthesis attribute ram_style mkProc distributed;" *) 17.216 +//(* synthesize *) 17.217 + 17.218 +module [CONNECTED_MODULE] mkProc( Proc ); 17.219 + 17.220 + //----------------------------------------------------------- 17.221 + // Debug port 17.222 + 17.223 + ServerStub_PROCESSORSYSTEMRRR server_stub <- mkServerStub_PROCESSORSYSTEMRRR(); 17.224 + 17.225 + 17.226 + //----------------------------------------------------------- 17.227 + // State 17.228 + 17.229 + // Standard processor state 17.230 + 17.231 + Reg#(Addr) pc <- mkReg(32'h00001000); 17.232 + Reg#(Epoch) epoch <- mkReg(0); 17.233 + Reg#(Stage) stage <- mkReg(PCgen); 17.234 + BRFile rf <- mkBRFile; 17.235 + 17.236 + // Branch Prediction 17.237 + BranchPred bp <- mkBranchPred(); 17.238 + FIFO#(PCStat) execpc <- mkLFIFO(); 17.239 + 17.240 + // Pipelines 17.241 + FIFO#(PCStat) pcQ <-mkSizedFIFO(3); 17.242 + SFIFO#(WBResult, Rindx) wbQ <-mkSFIFO(findwbf); 17.243 + 17.244 + Reg#(Bit#(32)) cp0_tohost <- mkReg(0); 17.245 + Reg#(Bit#(32)) cp0_fromhost <- mkReg(0); 17.246 + Reg#(Bool) cp0_statsEn <- mkReg(False); 17.247 + 17.248 + // Memory request/response state 17.249 + 17.250 + FIFO#(InstReq) instReqQ <- mkBFIFO1(); 17.251 + FIFO#(InstResp) instRespQ <- mkFIFO(); 17.252 + 17.253 + FIFO#(DataReq) dataReqQ <- mkBFIFO1(); 17.254 + FIFO#(DataResp) dataRespQ <- mkFIFO(); 17.255 + 17.256 + // Statistics state 17.257 + Reg#(Stat) num_cycles <- mkReg(0); 17.258 + Reg#(Stat) num_inst <- mkReg(0); 17.259 + 17.260 + //Or: 17.261 + // Statistics state 17.262 + //STAT num_cycles <- mkStatCounter(`STATS_PROCESSOR_CYCLE_COUNT); 17.263 + //STAT num_inst <- mkStatCounter(`STATS_PROCESSOR_INST_COUNT); 17.264 + 17.265 + //----------------------------------------------------------- 17.266 + // Rules 17.267 + 17.268 + (* descending_urgency = "exec, pcgen" *) 17.269 + rule pcgen; //( stage == PCgen ); 17.270 + let pc_plus4 = pc + 4; 17.271 + 17.272 + traceTiny("mkProc", "pc",pc); 17.273 + traceTiny("mkProc", "pcgen","P"); 17.274 + instReqQ.enq( LoadReq{ addr:pc, tag:epoch} ); 17.275 + 17.276 + let next_pc = bp.get(pc); 17.277 + if (next_pc matches tagged Valid .npc) 17.278 + begin 17.279 + pcQ.enq(PCStat {qpc:pc, qnxtpc:npc, qepoch:epoch}); 17.280 + pc <= npc; 17.281 + end 17.282 + else 17.283 + begin 17.284 + pcQ.enq(PCStat {qpc:pc, qnxtpc:pc_plus4, qepoch:epoch}); 17.285 + pc <= pc_plus4; 17.286 + end 17.287 + 17.288 + endrule 17.289 + 17.290 + rule discard (instRespQ.first() matches tagged LoadResp .ld 17.291 + &&& ld.tag != epoch); 17.292 + traceTiny("mkProc", "stage", "D"); 17.293 + instRespQ.deq(); 17.294 + endrule 17.295 + 17.296 + (* conflict_free = "exec, writeback" *) 17.297 + rule exec (instRespQ.first() matches tagged LoadResp.ld 17.298 + &&& (ld.tag == epoch) 17.299 + &&& unpack(ld.data) matches .inst 17.300 + &&& !stall(inst, wbQ)); 17.301 + 17.302 + // Some abbreviations 17.303 + let sext = signExtend; 17.304 + let zext = zeroExtend; 17.305 + let sra = signedShiftRight; 17.306 + 17.307 + // Get the instruction 17.308 + 17.309 + instRespQ.deq(); 17.310 + Instr inst 17.311 + = case ( instRespQ.first() ) matches 17.312 + tagged LoadResp .ld : return unpack(ld.data); 17.313 + tagged StoreResp .st : return ?; 17.314 + endcase; 17.315 + 17.316 + // Get the PC info 17.317 + let instrpc = pcQ.first().qpc; 17.318 + let pc_plus4 = instrpc + 4; 17.319 + 17.320 + Bool branchTaken = False; 17.321 + Addr newPC = pc_plus4; 17.322 + 17.323 + // Tracing 17.324 + traceTiny("mkProc", "exec","X"); 17.325 + traceTiny("mkProc", "exInstTiny",inst); 17.326 + traceFull("mkProc", "exInstFull",inst); 17.327 + 17.328 + case ( inst ) matches 17.329 + 17.330 + // -- Memory Ops ------------------------------------------------ 17.331 + 17.332 + tagged LW .it : 17.333 + begin 17.334 + Addr addr = rf.rd1(it.rbase) + sext(it.offset); 17.335 + dataReqQ.enq( LoadReq{ addr:addr, tag:zeroExtend(it.rdst) } ); 17.336 + wbQ.enq(tagged WB_Load it.rdst); 17.337 + end 17.338 + 17.339 + tagged SW .it : 17.340 + begin 17.341 + Addr addr = rf.rd1(it.rbase) + sext(it.offset); 17.342 + dataReqQ.enq( StoreReq{ tag:0, addr:addr, data:rf.rd2(it.rsrc) } ); 17.343 + wbQ.enq(tagged WB_Store); 17.344 + end 17.345 + 17.346 + // -- Simple Ops ------------------------------------------------ 17.347 + 17.348 + tagged ADDIU .it : 17.349 + begin 17.350 + Bit#(32) result = rf.rd1(it.rsrc) + sext(it.imm); 17.351 + wbQ.enq(tagged WB_ALU {data:result, dest:it.rdst}); 17.352 + end 17.353 + tagged SLTI .it : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:slt( rf.rd1(it.rsrc), sext(it.imm) )}); 17.354 + tagged SLTIU .it : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:sltu( rf.rd1(it.rsrc), sext(it.imm) ) }); 17.355 + tagged ANDI .it : 17.356 + begin 17.357 + Bit#(32) zext_it_imm = zext(it.imm); 17.358 + wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(rf.rd1(it.rsrc) & zext_it_imm)} ); 17.359 + end 17.360 + tagged ORI .it : 17.361 + begin 17.362 + Bit#(32) zext_it_imm = zext(it.imm); 17.363 + wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(rf.rd1(it.rsrc) | zext_it_imm)} ); 17.364 + end 17.365 + tagged XORI .it : 17.366 + begin 17.367 + Bit#(32) zext_it_imm = zext(it.imm); 17.368 + wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) ^ zext_it_imm )}); 17.369 + end 17.370 + tagged LUI .it : 17.371 + begin 17.372 + Bit#(32) zext_it_imm = zext(it.imm); 17.373 + wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(zext_it_imm << 32'd16) }); 17.374 + end 17.375 + 17.376 + tagged SLL .it : 17.377 + begin 17.378 + Bit#(32) zext_it_shamt = zext(it.shamt); 17.379 + wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) << zext_it_shamt )} ); 17.380 + end 17.381 + tagged SRL .it : 17.382 + begin 17.383 + Bit#(32) zext_it_shamt = zext(it.shamt); 17.384 + wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) >> zext_it_shamt )}); 17.385 + end 17.386 + tagged SRA .it : 17.387 + begin 17.388 + Bit#(32) zext_it_shamt = zext(it.shamt); 17.389 + wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( rf.rd1(it.rsrc), zext_it_shamt )}); 17.390 + end 17.391 + tagged SLLV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) << rshft(rf.rd2(it.rshamt)) )}); 17.392 + tagged SRLV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) >> rshft(rf.rd2(it.rshamt)) )} ); 17.393 + tagged SRAV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( rf.rd1(it.rsrc), rshft(rf.rd2(it.rshamt)) ) }); 17.394 + tagged ADDU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) + rf.rd2(it.rsrc2) )} ); 17.395 + tagged SUBU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) - rf.rd2(it.rsrc2) )} ); 17.396 + tagged AND .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) & rf.rd2(it.rsrc2) )} ); 17.397 + tagged OR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) | rf.rd2(it.rsrc2) )} ); 17.398 + tagged XOR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) ^ rf.rd2(it.rsrc2) )} ); 17.399 + tagged NOR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(~(rf.rd1(it.rsrc1) | rf.rd2(it.rsrc2)) )} ); 17.400 + tagged SLT .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:slt( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) }); 17.401 + tagged SLTU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sltu( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) }); 17.402 + 17.403 + // -- Branches -------------------------------------------------- 17.404 + 17.405 + tagged BLEZ .it : 17.406 + if ( signedLE( rf.rd1(it.rsrc), 0 ) ) 17.407 + begin 17.408 + newPC = pc_plus4 + (sext(it.offset) << 2); 17.409 + branchTaken = True; 17.410 + end 17.411 + 17.412 + tagged BGTZ .it : 17.413 + if ( signedGT( rf.rd1(it.rsrc), 0 ) ) 17.414 + begin 17.415 + newPC = pc_plus4 + (sext(it.offset) << 2); 17.416 + branchTaken = True; 17.417 + end 17.418 + 17.419 + tagged BLTZ .it : 17.420 + if ( signedLT( rf.rd1(it.rsrc), 0 ) ) 17.421 + begin 17.422 + newPC = pc_plus4 + (sext(it.offset) << 2); 17.423 + branchTaken = True; 17.424 + end 17.425 + 17.426 + tagged BGEZ .it : 17.427 + if ( signedGE( rf.rd1(it.rsrc), 0 ) ) 17.428 + begin 17.429 + newPC = pc_plus4 + (sext(it.offset) << 2); 17.430 + branchTaken = True; 17.431 + end 17.432 + 17.433 + tagged BEQ .it : 17.434 + if ( rf.rd1(it.rsrc1) == rf.rd2(it.rsrc2) ) 17.435 + begin 17.436 + newPC = pc_plus4 + (sext(it.offset) << 2); 17.437 + branchTaken = True; 17.438 + end 17.439 + 17.440 + tagged BNE .it : 17.441 + if ( rf.rd1(it.rsrc1) != rf.rd2(it.rsrc2) ) 17.442 + begin 17.443 + newPC = pc_plus4 + (sext(it.offset) << 2); 17.444 + branchTaken = True; 17.445 + end 17.446 + 17.447 + // -- Jumps ----------------------------------------------------- 17.448 + 17.449 + tagged J .it : 17.450 + begin 17.451 + newPC = { pc_plus4[31:28], it.target, 2'b0 }; 17.452 + branchTaken = True; 17.453 + end 17.454 + 17.455 + tagged JR .it : 17.456 + begin 17.457 + newPC = rf.rd1(it.rsrc); 17.458 + branchTaken = True; 17.459 + end 17.460 + 17.461 + tagged JAL .it : 17.462 + begin 17.463 + wbQ.enq(tagged WB_ALU {dest:31, data:pc_plus4 }); 17.464 + newPC = { pc_plus4[31:28], it.target, 2'b0 }; 17.465 + branchTaken = True; 17.466 + end 17.467 + 17.468 + tagged JALR .it : 17.469 + begin 17.470 + wbQ.enq(tagged WB_ALU {dest:it.rdst, data:pc_plus4 }); 17.471 + newPC = rf.rd1(it.rsrc); 17.472 + branchTaken = True; 17.473 + end 17.474 + 17.475 + // -- Cop0 ------------------------------------------------------ 17.476 + 17.477 + tagged MTC0 .it : 17.478 + begin 17.479 + case ( it.cop0dst ) 17.480 + 5'd10 : cp0_statsEn <= unpack(truncate(rf.rd1(it.rsrc))); 17.481 + 5'd21 : cp0_tohost <= truncate(rf.rd1(it.rsrc)); 17.482 + default : 17.483 + $display( " RTL-ERROR : %m : Illegal MTC0 cop0dst register!" ); 17.484 + endcase 17.485 + wbQ.enq(tagged WB_Host 0); //no idea wwhat this actually should be. 17.486 + end 17.487 + 17.488 +//this is host stuff? 17.489 + tagged MFC0 .it : 17.490 + begin 17.491 + case ( it.cop0src ) 17.492 + // not actually an ALU instruction but don't have the format otherwise 17.493 + 5'd10 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(cp0_statsEn)) }); 17.494 + 5'd20 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_fromhost }); 17.495 + 5'd21 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_tohost }); 17.496 + default : 17.497 + $display( " RTL-ERROR : %m : Illegal MFC0 cop0src register!" ); 17.498 + endcase 17.499 + end 17.500 + 17.501 + // -- Illegal --------------------------------------------------- 17.502 + 17.503 + default : 17.504 + $display( " RTL-ERROR : %m : Illegal instruction !" ); 17.505 + 17.506 + endcase 17.507 + 17.508 +//evaluate branch prediction 17.509 + Addr ppc = pcQ.first().qnxtpc; //predicted branch 17.510 + if (ppc != newPC) //prediction wrong 17.511 + begin 17.512 + epoch <= pcQ.first().qepoch + 1; 17.513 + bp.upd(instrpc, newPC); //update branch predictor 17.514 + pcQ.clear(); 17.515 + pc <= newPC; 17.516 + end 17.517 + else 17.518 + pcQ.deq(); 17.519 + 17.520 + if ( cp0_statsEn ) 17.521 + num_inst <= num_inst+1; 17.522 + 17.523 + endrule 17.524 + 17.525 + rule writeback; // ( stage == Writeback ); 17.526 + traceTiny("mkProc", "writeback","W"); 17.527 + 17.528 + 17.529 + // get what to do off the writeback queue 17.530 + wbQ.deq(); 17.531 + case (wbQ.first()) matches 17.532 + tagged WB_ALU {data:.res, dest:.rdst} : rf.wr(rdst, res); 17.533 + tagged WB_Load .regWr : 17.534 + begin 17.535 + dataRespQ.deq(); 17.536 + if (dataRespQ.first() matches tagged LoadResp .ld) 17.537 + rf.wr(truncate(ld.tag), ld.data); // no need to use Rindx from queue? Duplicate? 17.538 + end 17.539 + tagged WB_Store : dataRespQ.deq(); 17.540 + tagged WB_Host .dat : noAction; 17.541 + endcase 17.542 + 17.543 + endrule 17.544 + 17.545 + rule inc_num_cycles; 17.546 + if ( cp0_statsEn ) 17.547 + num_cycles <= num_cycles+1; 17.548 + endrule 17.549 + 17.550 +// THis rule breaks things 17.551 +// rule handleCPUToHost; 17.552 +// let req <- server_stub.acceptRequest_ReadCPUToHost(); 17.553 +// case (req) 17.554 +// 0: server_stub.sendResponse_ReadCPUToHost(cp0_tohost); 17.555 +// 1: server_stub.sendResponse_ReadCPUToHost(pc); 17.556 +// 2: server_stub.sendResponse_ReadCPUToHost(zeroExtend(pack(stage))); 17.557 +// endcase 17.558 +// endrule 17.559 +//----------------------------------------------------------- 17.560 +// My Adds 17.561 +//----------------------------------------------------------- 17.562 + 17.563 + //----------------------------------------------------------- 17.564 + // Methods 17.565 + 17.566 + interface Client imem_client; 17.567 + interface Get request = toGet(instReqQ); 17.568 + interface Put response = toPut(instRespQ); 17.569 + endinterface 17.570 + 17.571 + interface Client dmem_client; 17.572 + interface Get request = toGet(dataReqQ); 17.573 + interface Put response = toPut(dataRespQ); 17.574 + endinterface 17.575 + 17.576 + interface Get statsEn_get = toGet(asReg(cp0_statsEn)); 17.577 + 17.578 + interface ProcStats stats; 17.579 + interface Get num_cycles = toGet(asReg(num_cycles)); 17.580 + interface Get num_inst = toGet(asReg(num_inst)); 17.581 + endinterface 17.582 + 17.583 + interface CPUToHost tohost; 17.584 + method Bit#(32) cpuToHost(int req); 17.585 + return (case (req) 17.586 + 0: cp0_tohost; 17.587 + 1: pc; 17.588 + 2: zeroExtend(pack(stage)); 17.589 + endcase); 17.590 + endmethod 17.591 + endinterface 17.592 + 17.593 +endmodule 17.594 +