# HG changeset patch # User punk # Date 1272982433 14400 # Node ID 2c8166d205d5e2be6199d3e7dbe957ee1218fa28 # Parent 0c775e733b818b81b3b91ab5c6ead596ca5d9e48 [svn r34] uses scratchpad, set up for audio through c diff -r 0c775e733b81 -r 2c8166d205d5 config/pm/Pygar/audio_core/audio_core_exe.apm --- a/config/pm/Pygar/audio_core/audio_core_exe.apm Mon May 03 09:53:56 2010 -0400 +++ b/config/pm/Pygar/audio_core/audio_core_exe.apm Tue May 04 10:13:53 2010 -0400 @@ -87,6 +87,7 @@ core=Audio Processor Core funcp_base_types=Functional Partition Base Types audio_pipe_types=Simple Audio Processor Control Types +path_types=Audio Path Types [Audio Processor Core/Requires] processor_library=External Trace Processor Library @@ -95,12 +96,9 @@ instruction_cache=Blocking Instruction Cache mem_arb=Round-robin memory arbiter - - [Simple Audio Processor Control Types] File=modules/bluespec/Pygar/core/audio_pipe_types.awb - [Trace Functions] File=modules/bluespec/Pygar/core/trace.awb @@ -109,3 +107,6 @@ [External Trace Processor Library] File=modules/bluespec/Pygar/lab4/audio_processor_library.awb + +[Audio Path Types] +File=modules/bluespec/Pygar/core/path_types.awb diff -r 0c775e733b81 -r 2c8166d205d5 modules/bluespec/Pygar/core/AudioCore.dic --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/modules/bluespec/Pygar/core/AudioCore.dic Tue May 04 10:13:53 2010 -0400 @@ -0,0 +1,4 @@ +def VDEV.SCRATCH.MEMORY "program.0/program.vmh"; + + + diff -r 0c775e733b81 -r 2c8166d205d5 modules/bluespec/Pygar/core/AudioCoreRRR.cpp --- a/modules/bluespec/Pygar/core/AudioCoreRRR.cpp Mon May 03 09:53:56 2010 -0400 +++ b/modules/bluespec/Pygar/core/AudioCoreRRR.cpp Tue May 04 10:13:53 2010 -0400 @@ -62,6 +62,7 @@ // RRR service methods // +/* Not used by scratchpad UINT32 AUDIOCORERRR_SERVER_CLASS::MemoryRequestLoad (UINT32 address) { @@ -86,6 +87,7 @@ memory->Write(0,(UINT64) address, sizeof(UINT32), &data); } +*/ void diff -r 0c775e733b81 -r 2c8166d205d5 modules/bluespec/Pygar/core/AudioCoreRRR.h --- a/modules/bluespec/Pygar/core/AudioCoreRRR.h Mon May 03 09:53:56 2010 -0400 +++ b/modules/bluespec/Pygar/core/AudioCoreRRR.h Tue May 04 10:13:53 2010 -0400 @@ -41,8 +41,10 @@ // RRR service methods // + /* Not Used by ScratchPad UINT32 MemoryRequestLoad (UINT32 address); void MemoryRequestStore (UINT32 address, UINT32 data); + */ void SendProcessedStream(UINT16 control, UINT16 data0); }; diff -r 0c775e733b81 -r 2c8166d205d5 modules/bluespec/Pygar/core/AudioCoreRRR.rrr --- a/modules/bluespec/Pygar/core/AudioCoreRRR.rrr Mon May 03 09:53:56 2010 -0400 +++ b/modules/bluespec/Pygar/core/AudioCoreRRR.rrr Tue May 04 10:13:53 2010 -0400 @@ -9,8 +9,10 @@ server sw (cpp, method) <- hw (bsv, connection) { method SendProcessedStream (in UINT32[32] ctrl, in UINT32[32] sample); - method MemoryRequestLoad (in UINT32[32] address, out UINT32[32] value); - method MemoryRequestStore (in UINT32[32] address, in UINT32[32] value); + +// Not used by SCRATCHPAD +// method MemoryRequestLoad (in UINT32[32] address, out UINT32[32] value); +// method MemoryRequestStore (in UINT32[32] address, in UINT32[32] value); }; }; diff -r 0c775e733b81 -r 2c8166d205d5 modules/bluespec/Pygar/core/PathTypes.bsv --- a/modules/bluespec/Pygar/core/PathTypes.bsv Mon May 03 09:53:56 2010 -0400 +++ b/modules/bluespec/Pygar/core/PathTypes.bsv Tue May 04 10:13:53 2010 -0400 @@ -1,6 +1,8 @@ import Trace::*; import Vector::*; +`include "asim/provides/audio_pipe_types.bsh" + `define MAX_VOICES 4 `define MAX_CORES 16 `define MAX_PATH_IDS 18 @@ -10,9 +12,9 @@ typedef Bit#(32) MemAddr; typedef Int#(TLog#(`MAX_PATH_IDS)) PathId; -typedef Int#(24) Sample; +//typedef Int#(16) Sample; typedef Int#(TLog#(`MAX_VOICES)) VoiceId; - +typedef Bit#(8) Volume; // This is arbitrarily set to 8 bits or max val 256 //The mixer is identified as PathId 0, path end is max PathId mixerId = 0; @@ -27,5 +29,13 @@ VoiceId voice; MemAddr startAddr; CorePath route; + Volume outVol; } FullPath deriving (Bits, Eq); +typedef Maybe#(AudioProcessorUnit) AudioPipeUnit; // deriving (Bits, Eq); + +typedef struct +{ + VoiceId voice; + AudioPipeUnit data; +} AudioStream deriving (Bits, Eq); diff -r 0c775e733b81 -r 2c8166d205d5 modules/bluespec/Pygar/core/Processor.bsv --- a/modules/bluespec/Pygar/core/Processor.bsv Mon May 03 09:53:56 2010 -0400 +++ b/modules/bluespec/Pygar/core/Processor.bsv Tue May 04 10:13:53 2010 -0400 @@ -250,10 +250,13 @@ FIFO#(PCStat) pcQ <-mkSizedFIFO(3); SFIFO#(WBResult, Rindx) wbQ <-mkSFIFO(findwbf); + // NEED TO ADD CAPABILITY FOR RESET (should be able to just say if I get valid in and these are flagged, clear them. Reg#(Bit#(32)) cp0_tohost <- mkReg(0); Reg#(Bit#(32)) cp0_fromhost <- mkReg(0); Reg#(Bool) cp0_statsEn <- mkReg(False); - + Reg#(Bool) cp0_audioEOF <- mkReg(False); // Register to let code that EOF is reached + Reg#(Bool) cp0_progComp <- mkReg(False); // Register to let processor know that the program is complete (as this terminates) + // Memory request/response state FIFO#(InstReq) instReqQ <- mkBFIFO1(); @@ -488,11 +491,14 @@ // -- Cop0 ------------------------------------------------------ - tagged MTC0 .it : + tagged MTC0 .it : //Recieve things from host computer begin + $display( " PROCESSOR MTC0 call\n"); case ( it.cop0dst ) 5'd10 : cp0_statsEn <= unpack(truncate(rf.rd1(it.rsrc))); 5'd21 : cp0_tohost <= truncate(rf.rd1(it.rsrc)); + 5'd26 : cp0_progComp <= unpack(truncate(rf.rd1(it.rsrc))); //states audio program completed and termination okay + 5'd27 : outAudioFifo.enq(tagged Sample unpack(truncate(rf.rd1(it.rsrc)))); //Bit size is 16 not 32 default : $display( " RTL-ERROR : %m : Illegal MTC0 cop0dst register!" ); endcase @@ -500,13 +506,27 @@ end //this is host stuff? - tagged MFC0 .it : + tagged MFC0 .it : //Things out begin + $display( " PROCESSOR MFC0 call\n"); case ( it.cop0src ) // not actually an ALU instruction but don't have the format otherwise 5'd10 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(cp0_statsEn)) }); 5'd20 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_fromhost }); 5'd21 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_tohost }); + 5'd25 : begin + $display( "**** EOF Requested\n "); + wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(cp0_audioEOF)) }); // Reading clears bit + cp0_audioEOF <= False; + end + 5'd28 : begin + $display( "***** Reqesting Sample \n"); + let sample = inAudioFifo.first(); // is this going to cause perf. delay? + if (sample matches tagged Sample .audio) // if it is EOF another rule sets the cp0_audioEOF + wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(audio)) }); // do I need pack? + else $display ( "Audio File EOF Reached. Invalid sample request."); + inAudioFifo.deq(); + end default : $display( " RTL-ERROR : %m : Illegal MFC0 cop0src register!" ); endcase @@ -572,10 +592,22 @@ endrule // for now, we don't do anything. - rule connectAudioReqResp; +// rule connectAudioReqResp; // $display("rlm: PROCESSOR copies a datum\n"); - outAudioFifo.enq(inAudioFifo.first()); - inAudioFifo.deq; +// outAudioFifo.enq(inAudioFifo.first()); +// inAudioFifo.deq; +// endrule + + rule flagAudioEnd (inAudioFifo.first() matches tagged EndOfFile); + $display (" Proc Says End Audio Flag Set "); + cp0_audioEOF <= True; + inAudioFifo.deq; + endrule + + rule sendAudioEnd (cp0_progComp); + $display (" PROCESSOR Says Program Complete "); + outAudioFifo.enq(tagged EndOfFile); + cp0_progComp <= False; //only send one. And functions to reset endrule // Server items & rules: @@ -585,12 +617,12 @@ AudioProcessorControl ctrl = unpack(truncate(command.ctrl)); if(ctrl == EndOfFile) begin -// $display("lsp: PROCESSOR received EOF "); + $display("lsp: PROCESSOR received EOF "); inAudioFifo.enq(tagged EndOfFile); end else begin -// $display("lsp: PROCESSOR received Data "); + $display("lsp: PROCESSOR received Data "); inAudioFifo.enq(tagged Sample unpack(truncate(command.sample))); end endrule diff -r 0c775e733b81 -r 2c8166d205d5 modules/bluespec/Pygar/core/RoutingTable.bsv --- a/modules/bluespec/Pygar/core/RoutingTable.bsv Mon May 03 09:53:56 2010 -0400 +++ b/modules/bluespec/Pygar/core/RoutingTable.bsv Tue May 04 10:13:53 2010 -0400 @@ -3,12 +3,13 @@ import PathTypes::*; function FullPath genEmptyPaths (Integer a) ; - FullPath empt = FullPath {voice: fromInteger(a), startAddr: 0, route: emptyCore}; + FullPath empt = FullPath {voice: fromInteger(a), startAddr: 0, route: emptyCore, outVol: 0}; return (empt); endfunction interface RoutingTable; method FullPath getPath(Integer voiceNo); + method Vector#(`MAX_VOICES, Volume) getMixerScalars(); endinterface module mkRoutingTable(RoutingTable); @@ -25,9 +26,10 @@ routeTable[0].startAddr = 0; //where is this really going to come from? routeTable[0].route[0] = 3; routeTable[0].route[1] = mixerId; + routeTable[0].outVol = 200; //rest are already initialized toinvalid - // or if you just want to update a straight list, this longer emplate works. + // or if you just want to update a straight list, this longer template works. function CorePath createVoice1Route(); CorePath outPath = emptyCore; @@ -40,13 +42,21 @@ return outPath; endfunction routeTable[1].route = createVoice1Route; - routeTable[1].startAddr = 0; + routeTable[1].startAddr = 0; + routeTable[1].outVol = 200; //remaining voices are all initialized to empty. - method FullPath getPath(Integer a); + method FullPath getPath(Integer a); return routeTable[a]; endmethod + + method Vector#(`MAX_VOICES, Volume) getMixerScalars(); + Vector#(`MAX_VOICES, Volume) scalars = newVector(); + for(Integer i = 0; i < `MAX_VOICES; i = i+1) + scalars[i] = routeTable[i].outVol; + return scalars; + endmethod endmodule diff -r 0c775e733b81 -r 2c8166d205d5 modules/bluespec/Pygar/core/audioCorePipeline.bsv --- a/modules/bluespec/Pygar/core/audioCorePipeline.bsv Mon May 03 09:53:56 2010 -0400 +++ b/modules/bluespec/Pygar/core/audioCorePipeline.bsv Tue May 04 10:13:53 2010 -0400 @@ -35,9 +35,14 @@ //Local includes `include "asim/provides/audio_pipe_types.bsh" //provides Audio Pipeline interface +`include "asim/provides/path_types.bsh" `include "asim/provides/core.bsh" `include "asim/provides/processor_library.bsh" `include "asim/provides/fpga_components.bsh" +`include "asim/provides/scratchpad_memory.bsh" +`include "asim/provides/mem_services.bsh" +`include "asim/dict/VDEV_SCRATCH.bsh" + `include "asim/rrr/remote_client_stub_AUDIOCORERRR.bsh" //`include "asim/rrr/remote_server_stub_AUDIOCORERRR.bsh" @@ -47,7 +52,10 @@ //External memory // I'm not comfortable assuming that the memory subsystem is in order - // So I'll insert a completion buffer here. + // So I'll insert a completion buffer here. + MEMORY_IFC#(Bit#(18), Bit#(32)) memory <- mkScratchpad(`VDEV_SCRATCH_MEMORY, SCRATCHPAD_CACHED); //Services Memory items + + // Services Samples ClientStub_AUDIOCORERRR client_stub <- mkClientStub_AUDIOCORERRR(); // Make this big enough so that several outstanding requests may be supported FIFO#(Bit#(MainMemTagSz)) tags <- mkSizedFIFO(8); @@ -63,24 +71,22 @@ case (coreReq) matches tagged LoadReq .load: begin //Allocate ROB space - client_stub.makeRequest_MemoryRequestLoad(load.addr); + memory.readReq(truncate(load.addr>>2)); tags.enq(load.tag); end tagged StoreReq .store: begin - client_stub.makeRequest_MemoryRequestStore(store.addr,store.data); + memory.write(truncate(store.addr>>2),store.data); end endcase endrule rule receiveMemResp; - let memResp <- client_stub.getResponse_MemoryRequestLoad(); + let memResp <- memory.readRsp(); tags.deq; core.mmem_client.response.put(tagged LoadResp {data:memResp, tag: tags.first}); endrule - // this isn't particularly correct as it doesn't actually connect the processor interfaces, but this should allow me to verify the data path before fully blending the two items together. - rule feedOutput; let pipelineData <- core.sampleOutput.get(); AudioProcessorControl endOfFileTag = EndOfFile; diff -r 0c775e733b81 -r 2c8166d205d5 modules/bluespec/Pygar/core/audioPipe.bsv --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/modules/bluespec/Pygar/core/audioPipe.bsv Tue May 04 10:13:53 2010 -0400 @@ -0,0 +1,106 @@ +// The MIT License + +// Copyright (c) 2009 Massachusetts Institute of Technology + +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: + +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. + +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +// THE SOFTWARE. + +// Author: Kermin Fleming kfleming@mit.edu + +import Connectable::*; +import GetPut::*; +import ClientServer::*; +import FIFO::*; +import SpecialFIFOs::*; + +//AWB includes +`include "asim/provides/low_level_platform_interface.bsh" +`include "asim/provides/soft_connections.bsh" +`include "asim/provides/common_services.bsh" + +//Local includes +`include "asim/provides/audio_pipe_types.bsh" //provides Audio Pipeline interface +`include "asim/provides/core.bsh" +`include "asim/provides/processor_library.bsh" +`include "asim/provides/fpga_components.bsh" +`include "asim/provides/scratchpad_memory.bsh" +`include "asim/provides/mem_services.bsh" +`include "asim/dict/VDEV_SCRATCH.bsh" + +`include "asim/rrr/remote_client_stub_AUDIOCORERRR.bsh" +//`include "asim/rrr/remote_server_stub_AUDIOCORERRR.bsh" + +function +module [CONNECTED_MODULE] mkConnectedApplication (); + Core core <- mkCore; + Reg#(int) cycle <- mkReg(0); + + + //get volumes + //mkMixer(); + + //External memory + // I'm not comfortable assuming that the memory subsystem is in order + // So I'll insert a completion buffer here. + MEMORY_IFC#(Bit#(18), Bit#(32)) memory <- mkScratchpad(`VDEV_SCRATCH_MEMORY, SCRATCHPAD_CACHED); //Services Memory items + + // Services Samples + ClientStub_AUDIOCORERRR client_stub <- mkClientStub_AUDIOCORERRR(); + // Make this big enough so that several outstanding requests may be supported + FIFO#(Bit#(MainMemTagSz)) tags <- mkSizedFIFO(8); + + // this is for the tracing + rule printCycles; + cycle <= cycle+1; + $fdisplay(stderr, " => Cycle = %d", cycle); + endrule + + rule sendMemReq; + let coreReq <- core.mmem_client.request.get; + case (coreReq) matches + tagged LoadReq .load: begin + //Allocate ROB space + memory.readReq(truncate(load.addr>>2)); + tags.enq(load.tag); + end + tagged StoreReq .store: begin + memory.write(truncate(store.addr>>2),store.data); + end + endcase + endrule + + rule receiveMemResp; + let memResp <- memory.readRsp(); + tags.deq; + core.mmem_client.response.put(tagged LoadResp {data:memResp, + tag: tags.first}); + endrule + + rule feedOutput; + let pipelineData <- core.sampleOutput.get(); + AudioProcessorControl endOfFileTag = EndOfFile; + AudioProcessorControl sampleTag = Data; + + case (pipelineData) matches + tagged EndOfFile: + client_stub.makeRequest_SendProcessedStream(zeroExtend(pack(endOfFileTag)),?); + tagged Sample .sample:client_stub.makeRequest_SendProcessedStream(zeroExtend(pack(sampleTag)), zeroExtend(pack(sample))); + endcase + endrule + +endmodule diff -r 0c775e733b81 -r 2c8166d205d5 modules/bluespec/Pygar/core/audioPipe.bsv~ --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/modules/bluespec/Pygar/core/audioPipe.bsv~ Tue May 04 10:13:53 2010 -0400 @@ -0,0 +1,103 @@ +// The MIT License + +// Copyright (c) 2009 Massachusetts Institute of Technology + +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: + +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. + +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +// THE SOFTWARE. + +// Author: Kermin Fleming kfleming@mit.edu + +import Connectable::*; +import GetPut::*; +import ClientServer::*; +import FIFO::*; +import SpecialFIFOs::*; + +//AWB includes +`include "asim/provides/low_level_platform_interface.bsh" +`include "asim/provides/soft_connections.bsh" +`include "asim/provides/common_services.bsh" + +//Local includes +`include "asim/provides/audio_pipe_types.bsh" //provides Audio Pipeline interface +`include "asim/provides/core.bsh" +`include "asim/provides/processor_library.bsh" +`include "asim/provides/fpga_components.bsh" +`include "asim/provides/scratchpad_memory.bsh" +`include "asim/provides/mem_services.bsh" +`include "asim/dict/VDEV_SCRATCH.bsh" + +`include "asim/rrr/remote_client_stub_AUDIOCORERRR.bsh" +//`include "asim/rrr/remote_server_stub_AUDIOCORERRR.bsh" + +module [CONNECTED_MODULE] mkConnectedApplication (); + Core core <- mkCore; + Reg#(int) cycle <- mkReg(0); + + //mkMixer(); + + //External memory + // I'm not comfortable assuming that the memory subsystem is in order + // So I'll insert a completion buffer here. + MEMORY_IFC#(Bit#(18), Bit#(32)) memory <- mkScratchpad(`VDEV_SCRATCH_MEMORY, SCRATCHPAD_CACHED); //Services Memory items + + // Services Samples + ClientStub_AUDIOCORERRR client_stub <- mkClientStub_AUDIOCORERRR(); + // Make this big enough so that several outstanding requests may be supported + FIFO#(Bit#(MainMemTagSz)) tags <- mkSizedFIFO(8); + + // this is for the tracing + rule printCycles; + cycle <= cycle+1; + $fdisplay(stderr, " => Cycle = %d", cycle); + endrule + + rule sendMemReq; + let coreReq <- core.mmem_client.request.get; + case (coreReq) matches + tagged LoadReq .load: begin + //Allocate ROB space + memory.readReq(truncate(load.addr>>2)); + tags.enq(load.tag); + end + tagged StoreReq .store: begin + memory.write(truncate(store.addr>>2),store.data); + end + endcase + endrule + + rule receiveMemResp; + let memResp <- memory.readRsp(); + tags.deq; + core.mmem_client.response.put(tagged LoadResp {data:memResp, + tag: tags.first}); + endrule + + rule feedOutput; + let pipelineData <- core.sampleOutput.get(); + AudioProcessorControl endOfFileTag = EndOfFile; + AudioProcessorControl sampleTag = Data; + + case (pipelineData) matches + tagged EndOfFile: + client_stub.makeRequest_SendProcessedStream(zeroExtend(pack(endOfFileTag)),?); + tagged Sample .sample:client_stub.makeRequest_SendProcessedStream(zeroExtend(pack(sampleTag)), zeroExtend(pack(sample))); + endcase + endrule + +endmodule diff -r 0c775e733b81 -r 2c8166d205d5 modules/bluespec/Pygar/core/audio_core_pipe.awb --- a/modules/bluespec/Pygar/core/audio_core_pipe.awb Mon May 03 09:53:56 2010 -0400 +++ b/modules/bluespec/Pygar/core/audio_core_pipe.awb Tue May 04 10:13:53 2010 -0400 @@ -4,6 +4,7 @@ %provides connected_application %requires audio_pipe_types +%requires path_types %requires core %requires funcp_simulated_memory %requires funcp_base_types @@ -18,6 +19,8 @@ %sources -t CPP -v PRIVATE AudioCoreRRR.cpp %sources -t H -v PUBLIC AudioCoreRRR.h %sources -t RRR -v PUBLIC AudioCoreRRR.rrr +%sources -t DICT -v PUBLIC AudioCore.dic + %sources -t CPP -v PRIVATE SndfileWavUtil.cpp %sources -t H -v PUBLIC SndfileWavUtil.h %library /usr/lib/libsndfile.so diff -r 0c775e733b81 -r 2c8166d205d5 modules/bluespec/Pygar/core/mixer.bsv --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/modules/bluespec/Pygar/core/mixer.bsv Tue May 04 10:13:53 2010 -0400 @@ -0,0 +1,69 @@ +// The MIT License + +// Copyright (c) 2009 Massachusetts Institute of Technology + +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: + +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. + +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +// THE SOFTWARE. + +import Connectable::*; +import GetPut::*; +import ClientServer::*; +import Processor::*; +import MemArb::*; +import MemTypes::*; + +//AWB includes +`include "asim/provides/low_level_platform_interface.bsh" +`include "asim/provides/soft_connections.bsh" +`include "asim/provides/common_services.bsh" + +// Local includes +`include "asim/provides/processor_library.bsh" +`include "asim/provides/audio_pipe_types.bsh" +`include "asim/provides/path_types.bsh" + +interface PutMixerIn; + method Action sendVoiceIn(AudioStream voiceInput); +endinterface + +interface Mixer#(Vector#(`MAX_VOICES, Volume)); + interface PutMixerIn toMixer; + interface Get#(AudioProcessorUnit) mixerOut; +endinterface + + +module [CONNECTED_MODULE] mkMixer( Mixer#(Vector(`MAX_VOICES, Volume))); + // Instantiate the modules + Vector#(`MAX_VOICES, FIFO#(AudioPipeUnit)) voicesIn <- newVector(); + Vector#(`MAX_VOICES, Bool) voiceEnded <- replicate(False); + + FIFO#(AudioProcessorUnit) masterFifo <- mkFIFO(); + + rule processSample //implicit on all voiceFifos having data + endrule + + // Internal connections + + interface PutMixerIn toMixer; + method Action sendVoiceIn(AudioStream voiceInput); + voicesIn[voiceInput.voice].enq(voiceInput.data); + endmethod + + interface Get mixerOut = fifoToGet(masterFifo); + +endmodule diff -r 0c775e733b81 -r 2c8166d205d5 modules/bluespec/Pygar/core/mixer.bsv~ --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/modules/bluespec/Pygar/core/mixer.bsv~ Tue May 04 10:13:53 2010 -0400 @@ -0,0 +1,62 @@ +// The MIT License + +// Copyright (c) 2009 Massachusetts Institute of Technology + +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: + +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. + +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +// THE SOFTWARE. + +import Connectable::*; +import GetPut::*; +import ClientServer::*; +import Processor::*; +import MemArb::*; +import MemTypes::*; + +//AWB includes +`include "asim/provides/low_level_platform_interface.bsh" +`include "asim/provides/soft_connections.bsh" +`include "asim/provides/common_services.bsh" + +// Local includes +`include "asim/provides/processor_library.bsh" +`include "asim/provides/processor.bsh" +`include "asim/provides/audio_pipe_types.bsh" + +interface Core; + + // Interface from core to main memory + interface Client#(MainMemReq,MainMemResp) mmem_client; + + interface Get#(AudioProcessorUnit) sampleOutput; + +endinterface + +module [CONNECTED_MODULE] mkCore( Core ); + + // Instantiate the modules + + Proc proc <- mkProc(); + ICache#(InstReq,InstResp) icache <- mkInstCache(); + DCache#(DataReq,DataResp) dcache <- mkDataCache(); + MemArb marb <- mkMemArb(); + + // Internal connections + + interface sampleOutput = proc.sampleOutput; + +endmodule diff -r 0c775e733b81 -r 2c8166d205d5 modules/bluespec/Pygar/core/path_types.awb --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/modules/bluespec/Pygar/core/path_types.awb Tue May 04 10:13:53 2010 -0400 @@ -0,0 +1,10 @@ +%name Audio Path Types +%desc Provides definitions for audio portion of pipeline definitions + +%provides path_types + +%attributes PYGAR + +%public PathTypes.bsv + + diff -r 0c775e733b81 -r 2c8166d205d5 modules/bluespec/Pygar/core/route_table.awb --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/modules/bluespec/Pygar/core/route_table.awb Tue May 04 10:13:53 2010 -0400 @@ -0,0 +1,12 @@ +%name Routing Table +%desc Outlines a set up for routes and mixing scalars + +%provides route_table + +%requires path_types + +%attributes PYGAR + +%public RouteTable.bsv + + diff -r 0c775e733b81 -r 2c8166d205d5 modules/bluespec/Pygar/lab4/#Processor.bsv# --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/modules/bluespec/Pygar/lab4/#Processor.bsv# Tue May 04 10:13:53 2010 -0400 @@ -0,0 +1,591 @@ +/// The MIT License + +// Copyright (c) 2009 Massachusetts Institute of Technology + +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: + +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. + +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +// THE SOFTWARE. + +import Connectable::*; +import GetPut::*; +import ClientServer::*; +import RegFile::*; + +import FIFO::*; +import FIFOF::*; +import SFIFO::*; +import RWire::*; + +import BFIFO::*; +import MemTypes::*; +import ProcTypes::*; +import BRegFile::*; +import BranchPred::*; +//import PathTypes::*; This is only there to force the debugging + +import Trace::*; + +//AWB includes +`include "asim/provides/low_level_platform_interface.bsh" +`include "asim/provides/soft_connections.bsh" +`include "asim/provides/common_services.bsh" + +// Local includes +`include "asim/provides/processor_library.bsh" +`include "asim/rrr/remote_server_stub_PROCESSORSYSTEMRRR.bsh" +`include "asim/provides/common_services.bsh" +`include "asim/dict/STATS_PROCESSOR.bsh" + +interface ProcStats; + interface Get#(Stat) num_cycles; + interface Get#(Stat) num_inst; +endinterface + +interface CPUToHost; + method Bit#(32) cpuToHost(int req); +endinterface + +interface Proc; + + // Interface from processor to caches + interface Client#(DataReq,DataResp) dmem_client; + interface Client#(InstReq,InstResp) imem_client; + + // Interface for enabling/disabling statistics on the rest of the core + interface Get#(Bool) statsEn_get; + + // Interface for collecting statistics. + interface ProcStats stats; + + // Interface to host + interface CPUToHost tohost; + +endinterface + + +typedef enum { PCgen, Exec, Writeback } Stage deriving(Eq,Bits); + +//----------------------------------------------------------- +// Register file module +//----------------------------------------------------------- + +interface BRFile; + method Action wr( Rindx rindx, Bit#(32) data ); + method Bit#(32) rd1( Rindx rindx ); + method Bit#(32) rd2( Rindx rindx ); +endinterface + +module mkBRFile( BRFile ); + + RegFile#(Rindx,Bit#(32)) rfile <- mkBRegFile(); + + method Action wr( Rindx rindx, Bit#(32) data ); + rfile.upd( rindx, data ); + endmethod + + method Bit#(32) rd1( Rindx rindx ); + return ( rindx == 0 ) ? 0 : rfile.sub(rindx); + endmethod + + method Bit#(32) rd2( Rindx rindx ); + return ( rindx == 0 ) ? 0 : rfile.sub(rindx); + endmethod + +endmodule + +//----------------------------------------------------------- +// Helper functions +//----------------------------------------------------------- + +function Bit#(32) slt( Bit#(32) val1, Bit#(32) val2 ); + return zeroExtend( pack( signedLT(val1,val2) ) ); +endfunction + +function Bit#(32) sltu( Bit#(32) val1, Bit#(32) val2 ); + return zeroExtend( pack( val1 < val2 ) ); +endfunction + +function Bit#(32) rshft( Bit#(32) val ); + return zeroExtend(val[4:0]); +endfunction + + +//----------------------------------------------------------- +// Find funct for wbQ +//----------------------------------------------------------- +function Bool findwbf(Rindx fVal, WBResult cmpVal); + case (cmpVal) matches + tagged WB_ALU {data:.res, dest:.rd} : + return (fVal == rd); + tagged WB_Load .rd : + return (fVal == rd); + tagged WB_Store .st : + return False; + tagged WB_Host .x : + return False; + endcase +endfunction + + +//----------------------------------------------------------- +// Stall funct for wbQ +//----------------------------------------------------------- +function Bool stall(Instr inst, SFIFO#(WBResult, Rindx) f); + case (inst) matches + // -- Memory Ops ------------------------------------------------ + tagged LW .it : + return f.find(it.rbase); + tagged SW {rsrc:.dreg, rbase:.addr, offset:.o} : + return (f.find(addr) || f.find2(dreg)); + + // -- Simple Ops ------------------------------------------------ + tagged ADDIU .it : return f.find(it.rsrc); + tagged SLTI .it : return f.find(it.rsrc); + tagged SLTIU .it : return f.find(it.rsrc); + tagged ANDI .it : return f.find(it.rsrc); + tagged ORI .it : return f.find(it.rsrc); + tagged XORI .it : return f.find(it.rsrc); + + tagged LUI .it : return f.find(it.rdst); //this rds/wrs itself + tagged SLL .it : return f.find(it.rsrc); + tagged SRL .it : return f.find(it.rsrc); + tagged SRA .it : return f.find(it.rsrc); + tagged SLLV .it : return (f.find(it.rsrc) || f.find(it.rshamt)); + tagged SRLV .it : return (f.find(it.rsrc) || f.find(it.rshamt)); + tagged SRAV .it : return (f.find(it.rsrc) || f.find(it.rshamt)); + tagged ADDU .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); + tagged SUBU .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); + tagged AND .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); + tagged OR .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); + tagged XOR .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); + tagged NOR .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); + tagged SLT .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); + tagged SLTU .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); + + + // -- Branches -------------------------------------------------- + + tagged BLEZ .it : return (f.find(it.rsrc)); + tagged BGTZ .it : return (f.find(it.rsrc)); + tagged BLTZ .it : return (f.find(it.rsrc)); + tagged BGEZ .it : return (f.find(it.rsrc)); + tagged BEQ .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); + tagged BNE .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); + + // -- Jumps ----------------------------------------------------- + + tagged J .it : return False; + tagged JR .it : return f.find(it.rsrc); + tagged JALR .it : return f.find(it.rsrc); + tagged JAL .it : return False; + + // -- Cop0 ------------------------------------------------------ + + tagged MTC0 .it : return f.find(it.rsrc); + tagged MFC0 .it : return False; + + // -- Illegal --------------------------------------------------- + + default : return False; + + endcase +endfunction +//----------------------------------------------------------- +// Reference processor +//----------------------------------------------------------- + + +//(* doc = "synthesis attribute ram_style mkProc distributed;" *) +//(* synthesize *) + +module [CONNECTED_MODULE] mkProc( Proc ); + + //----------------------------------------------------------- + // Debug port + + ServerStub_PROCESSORSYSTEMRRR server_stub <- mkServerStub_PROCESSORSYSTEMRRR(); + + + //----------------------------------------------------------- + // State + + // Standard processor state + + Reg#(Addr) pc <- mkReg(32'h00001000); + Reg#(Epoch) epoch <- mkReg(0); + Reg#(Stage) stage <- mkReg(PCgen); + BRFile rf <- mkBRFile; + + // Branch Prediction + BranchPred bp <- mkBranchPred(); + FIFO#(PCStat) execpc <- mkLFIFO(); + + // Pipelines + FIFO#(PCStat) pcQ <-mkSizedFIFO(3); + SFIFO#(WBResult, Rindx) wbQ <-mkSFIFO(findwbf); + + Reg#(Bit#(32)) cp0_tohost <- mkReg(0); + Reg#(Bit#(32)) cp0_fromhost <- mkReg(0); + Reg#(Bool) cp0_statsEn <- mkReg(False); + + // Memory request/response state + + FIFO#(InstReq) instReqQ <- mkBFIFO1(); + FIFO#(InstResp) instRespQ <- mkFIFO(); + + FIFO#(DataReq) dataReqQ <- mkBFIFO1(); + FIFO#(DataResp) dataRespQ <- mkFIFO(); + + // Statistics state + Reg#(Stat) num_cycles <- mkReg(0); + Reg#(Stat) num_inst <- mkReg(0); + + //Or: + // Statistics state + //STAT num_cycles <- mkStatCounter(`STATS_PROCESSOR_CYCLE_COUNT); + //STAT num_inst <- mkStatCounter(`STATS_PROCESSOR_INST_COUNT); + + //----------------------------------------------------------- + // Rules + + (* descending_urgency = "exec, pcgen" *) + rule pcgen; //( stage == PCgen ); + let pc_plus4 = pc + 4; + + traceTiny("mkProc", "pc",pc); + traceTiny("mkProc", "pcgen","P"); + instReqQ.enq( LoadReq{ addr:pc, tag:epoch} ); + + let next_pc = bp.get(pc); + if (next_pc matches tagged Valid .npc) + begin + pcQ.enq(PCStat {qpc:pc, qnxtpc:npc, qepoch:epoch}); + pc <= npc; + end + else + begin + pcQ.enq(PCStat {qpc:pc, qnxtpc:pc_plus4, qepoch:epoch}); + pc <= pc_plus4; + end + + endrule + + rule discard (instRespQ.first() matches tagged LoadResp .ld + &&& ld.tag != epoch); + traceTiny("mkProc", "stage", "D"); + instRespQ.deq(); + endrule + + (* conflict_free = "exec, writeback" *) + rule exec (instRespQ.first() matches tagged LoadResp.ld + &&& (ld.tag == epoch) + &&& unpack(ld.data) matches .inst + &&& !stall(inst, wbQ)); + + // Some abbreviations + let sext = signExtend; + let zext = zeroExtend; + let sra = signedShiftRight; + + // Get the instruction + + instRespQ.deq(); + Instr inst + = case ( instRespQ.first() ) matches + tagged LoadResp .ld : return unpack(ld.data); + tagged StoreResp .st : return ?; + endcase; + + // Get the PC info + let instrpc = pcQ.first().qpc; + let pc_plus4 = instrpc + 4; + + Bool branchTaken = False; + Addr newPC = pc_plus4; + + // Tracing + traceTiny("mkProc", "exec","X"); + traceTiny("mkProc", "exInstTiny",inst); + traceFull("mkProc", "exInstFull",inst); + + case ( inst ) matches + + // -- Memory Ops ------------------------------------------------ + + tagged LW .it : + begin + Addr addr = rf.rd1(it.rbase) + sext(it.offset); + dataReqQ.enq( LoadReq{ addr:addr, tag:zeroExtend(it.rdst) } ); + wbQ.enq(tagged WB_Load it.rdst); + end + + tagged SW .it : + begin + Addr addr = rf.rd1(it.rbase) + sext(it.offset); + dataReqQ.enq( StoreReq{ tag:0, addr:addr, data:rf.rd2(it.rsrc) } ); + wbQ.enq(tagged WB_Store); + end + + // -- Simple Ops ------------------------------------------------ + + tagged ADDIU .it : + begin + Bit#(32) result = rf.rd1(it.rsrc) + sext(it.imm); + wbQ.enq(tagged WB_ALU {data:result, dest:it.rdst}); + end + tagged SLTI .it : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:slt( rf.rd1(it.rsrc), sext(it.imm) )}); + tagged SLTIU .it : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:sltu( rf.rd1(it.rsrc), sext(it.imm) ) }); + tagged ANDI .it : + begin + Bit#(32) zext_it_imm = zext(it.imm); + wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(rf.rd1(it.rsrc) & zext_it_imm)} ); + end + tagged ORI .it : + begin + Bit#(32) zext_it_imm = zext(it.imm); + wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(rf.rd1(it.rsrc) | zext_it_imm)} ); + end + tagged XORI .it : + begin + Bit#(32) zext_it_imm = zext(it.imm); + wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) ^ zext_it_imm )}); + end + tagged LUI .it : + begin + Bit#(32) zext_it_imm = zext(it.imm); + wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(zext_it_imm << 32'd16) }); + end + + tagged SLL .it : + begin + Bit#(32) zext_it_shamt = zext(it.shamt); + wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) << zext_it_shamt )} ); + end + tagged SRL .it : + begin + Bit#(32) zext_it_shamt = zext(it.shamt); + wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) >> zext_it_shamt )}); + end + tagged SRA .it : + begin + Bit#(32) zext_it_shamt = zext(it.shamt); + wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( rf.rd1(it.rsrc), zext_it_shamt )}); + end + tagged SLLV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) << rshft(rf.rd2(it.rshamt)) )}); + tagged SRLV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) >> rshft(rf.rd2(it.rshamt)) )} ); + tagged SRAV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( rf.rd1(it.rsrc), rshft(rf.rd2(it.rshamt)) ) }); + tagged ADDU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) + rf.rd2(it.rsrc2) )} ); + tagged SUBU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) - rf.rd2(it.rsrc2) )} ); + tagged AND .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) & rf.rd2(it.rsrc2) )} ); + tagged OR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) | rf.rd2(it.rsrc2) )} ); + tagged XOR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) ^ rf.rd2(it.rsrc2) )} ); + tagged NOR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(~(rf.rd1(it.rsrc1) | rf.rd2(it.rsrc2)) )} ); + tagged SLT .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:slt( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) }); + tagged SLTU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sltu( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) }); + + // -- Branches -------------------------------------------------- + + tagged BLEZ .it : + if ( signedLE( rf.rd1(it.rsrc), 0 ) ) + begin + newPC = pc_plus4 + (sext(it.offset) << 2); + branchTaken = True; + end + + tagged BGTZ .it : + if ( signedGT( rf.rd1(it.rsrc), 0 ) ) + begin + newPC = pc_plus4 + (sext(it.offset) << 2); + branchTaken = True; + end + + tagged BLTZ .it : + if ( signedLT( rf.rd1(it.rsrc), 0 ) ) + begin + newPC = pc_plus4 + (sext(it.offset) << 2); + branchTaken = True; + end + + tagged BGEZ .it : + if ( signedGE( rf.rd1(it.rsrc), 0 ) ) + begin + newPC = pc_plus4 + (sext(it.offset) << 2); + branchTaken = True; + end + + tagged BEQ .it : + if ( rf.rd1(it.rsrc1) == rf.rd2(it.rsrc2) ) + begin + newPC = pc_plus4 + (sext(it.offset) << 2); + branchTaken = True; + end + + tagged BNE .it : + if ( rf.rd1(it.rsrc1) != rf.rd2(it.rsrc2) ) + begin + newPC = pc_plus4 + (sext(it.offset) << 2); + branchTaken = True; + end + + // -- Jumps ----------------------------------------------------- + + tagged J .it : + begin + newPC = { pc_plus4[31:28], it.target, 2'b0 }; + branchTaken = True; + end + + tagged JR .it : + begin + newPC = rf.rd1(it.rsrc); + branchTaken = True; + end + + tagged JAL .it : + begin + wbQ.enq(tagged WB_ALU {dest:31, data:pc_plus4 }); + newPC = { pc_plus4[31:28], it.target, 2'b0 }; + branchTaken = True; + end + + tagged JALR .it : + begin + wbQ.enq(tagged WB_ALU {dest:it.rdst, data:pc_plus4 }); + newPC = rf.rd1(it.rsrc); + branchTaken = True; + end + + // -- Cop0 ------------------------------------------------------ + + tagged MTC0 .it : + begin + case ( it.cop0dst ) + 5'd10 : cp0_statsEn <= unpack(truncate(rf.rd1(it.rsrc))); + 5'd21 : cp0_tohost <= truncate(rf.rd1(it.rsrc)); + default : + $display( " RTL-ERROR : %m : Illegal MTC0 cop0dst register!" ); + endcase + wbQ.enq(tagged WB_Host 0); //no idea wwhat this actually should be. + end + +//this is host stuff? + tagged MFC0 .it : + begin + case ( it.cop0src ) + // not actually an ALU instruction but don't have the format otherwise + 5'd10 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(cp0_statsEn)) }); + 5'd20 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_fromhost }); + 5'd21 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_tohost }); + default : + $display( " RTL-ERROR : %m : Illegal MFC0 cop0src register!" ); + endcase + end + + // -- Illegal --------------------------------------------------- + + default : + $display( " RTL-ERROR : %m : Illegal instruction !" ); + + endcase + +//evaluate branch prediction + Addr ppc = pcQ.first().qnxtpc; //predicted branch + if (ppc != newPC) //prediction wrong + begin + epoch <= pcQ.first().qepoch + 1; + bp.upd(instrpc, newPC); //update branch predictor + pcQ.clear(); + pc <= newPC; + end + else + pcQ.deq(); + + if ( cp0_statsEn ) + num_inst <= num_inst+1; + + endrule + + rule writeback; // ( stage == Writeback ); + traceTiny("mkProc", "writeback","W"); + + + // get what to do off the writeback queue + wbQ.deq(); + case (wbQ.first()) matches + tagged WB_ALU {data:.res, dest:.rdst} : rf.wr(rdst, res); + tagged WB_Load .regWr : + begin + dataRespQ.deq(); + if (dataRespQ.first() matches tagged LoadResp .ld) + rf.wr(truncate(ld.tag), ld.data); // no need to use Rindx from queue? Duplicate? + end + tagged WB_Store : dataRespQ.deq(); + tagged WB_Host .dat : noAction; + endcase + + endrule + + rule inc_num_cycles; + if ( cp0_statsEn ) + num_cycles <= num_cycles+1; + endrule + +// THis rule breaks things +// rule handleCPUToHost; +// let req <- server_stub.acceptRequest_ReadCPUToHost(); +// case (req) +// 0: server_stub.sendResponse_ReadCPUToHost(cp0_tohost); +// 1: server_stub.sendResponse_ReadCPUToHost(pc); +// 2: server_stub.sendResponse_ReadCPUToHost(zeroExtend(pack(stage))); +// endcase +// endrule +//----------------------------------------------------------- +// My Adds +//----------------------------------------------------------- + + //----------------------------------------------------------- + // Methods + + interface Client imem_client; + interface Get request = toGet(instReqQ); + interface Put response = toPut(instRespQ); + endinterface + + interface Client dmem_client; + interface Get request = toGet(dataReqQ); + interface Put response = toPut(dataRespQ); + endinterface + + interface Get statsEn_get = toGet(asReg(cp0_statsEn)); + + interface ProcStats stats; + interface Get num_cycles = toGet(asReg(num_cycles)); + interface Get num_inst = toGet(asReg(num_inst)); + endinterface + + interface CPUToHost tohost; + method Bit#(32) cpuToHost(int req); + return (case (req) + 0: cp0_tohost; + 1: pc; + 2: zeroExtend(pack(stage)); + endcase); + endmethod + endinterface + +endmodule +