view modules/bluespec/Pygar/core/Processor.bsv @ 33:2c8166d205d5 pygar svn.34

[svn r34] uses scratchpad, set up for audio through c
author punk
date Tue, 04 May 2010 10:13:53 -0400
parents f5dfbe28fa59
children 14f7a7ace3f5
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1 /// The MIT License
3 // Copyright (c) 2009 Massachusetts Institute of Technology
5 // Permission is hereby granted, free of charge, to any person obtaining a copy
6 // of this software and associated documentation files (the "Software"), to deal
7 // in the Software without restriction, including without limitation the rights
8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 // copies of the Software, and to permit persons to whom the Software is
10 // furnished to do so, subject to the following conditions:
12 // The above copyright notice and this permission notice shall be included in
13 // all copies or substantial portions of the Software.
15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
21 // THE SOFTWARE.
24 import Connectable::*;
25 import GetPut::*;
26 import ClientServer::*;
27 import RegFile::*;
29 import FIFO::*;
30 import FIFOF::*;
31 import SFIFO::*;
32 import RWire::*;
34 import Trace::*;
35 import BFIFO::*;
36 import MemTypes::*;
37 import ProcTypes::*;
38 import BRegFile::*;
39 import BranchPred::*;
40 //import PathTypes::*; This is only there to force the debugging
42 //AWB includes
43 `include "asim/provides/low_level_platform_interface.bsh"
44 `include "asim/provides/soft_connections.bsh"
45 `include "asim/provides/common_services.bsh"
47 // Local includes
48 //`include "asim/provides/processor_library.bsh" (included above directly)
49 `include "asim/rrr/remote_server_stub_AUDIOCORERRR.bsh"
50 `include "asim/provides/common_services.bsh"
51 `include "asim/dict/STATS_PROCESSOR.bsh"
52 `include "asim/provides/processor_library.bsh"
54 // Local includes. Look for the correspondingly named .awb files
55 // workspace/labs/src/mit-6.375/modules/bluespec/mit-6.375/common/
56 // to find the actual Bluespec files which are used to generate
57 // these includes. These files are specific to this audio processing
58 // pipeline
60 `include "asim/provides/audio_pipe_types.bsh"
62 //interface CPUToHost;
63 // method Bit#(32) cpuToHost(int req);
64 //endinterface
66 interface Proc;
68 // Interface from processor to caches
69 interface Client#(DataReq,DataResp) dmem_client;
70 interface Client#(InstReq,InstResp) imem_client;
72 // Interface for enabling/disabling statistics on the rest of the core
73 interface Get#(Bool) statsEn_get;
75 // // Interface to host
76 // interface CPUToHost tohost;
78 // Interface to Audio Pipeline
79 interface Get#(AudioProcessorUnit) sampleOutput;
81 endinterface
83 //The full interface for this is as below in the common file for audioProcessorTypes.bsv
84 //interface AudioOut;
85 // interface Get#(AudioProcessorUnit) audioSampleOutput;
86 //endinterface
88 //interface AudioIn;
89 // interface Put#(AudioProcessorUnit) audioSampleInput;
90 //endinterface
92 typedef enum { PCgen, Exec, Writeback } Stage deriving(Eq,Bits);
94 //-----------------------------------------------------------
95 // Register file module
96 //-----------------------------------------------------------
98 interface BRFile;
99 method Action wr( Rindx rindx, Bit#(32) data );
100 method Bit#(32) rd1( Rindx rindx );
101 method Bit#(32) rd2( Rindx rindx );
102 endinterface
104 module mkBRFile( BRFile );
106 RegFile#(Rindx,Bit#(32)) rfile <- mkBRegFile();
108 method Action wr( Rindx rindx, Bit#(32) data );
109 rfile.upd( rindx, data );
110 endmethod
112 method Bit#(32) rd1( Rindx rindx );
113 return ( rindx == 0 ) ? 0 : rfile.sub(rindx);
114 endmethod
116 method Bit#(32) rd2( Rindx rindx );
117 return ( rindx == 0 ) ? 0 : rfile.sub(rindx);
118 endmethod
120 endmodule
122 //-----------------------------------------------------------
123 // Helper functions
124 //-----------------------------------------------------------
126 function Bit#(32) slt( Bit#(32) val1, Bit#(32) val2 );
127 return zeroExtend( pack( signedLT(val1,val2) ) );
128 endfunction
130 function Bit#(32) sltu( Bit#(32) val1, Bit#(32) val2 );
131 return zeroExtend( pack( val1 < val2 ) );
132 endfunction
134 function Bit#(32) rshft( Bit#(32) val );
135 return zeroExtend(val[4:0]);
136 endfunction
139 //-----------------------------------------------------------
140 // Find funct for wbQ
141 //-----------------------------------------------------------
142 function Bool findwbf(Rindx fVal, WBResult cmpVal);
143 case (cmpVal) matches
144 tagged WB_ALU {data:.res, dest:.rd} :
145 return (fVal == rd);
146 tagged WB_Load .rd :
147 return (fVal == rd);
148 tagged WB_Store .st :
149 return False;
150 tagged WB_Host .x :
151 return False;
152 endcase
153 endfunction
156 //-----------------------------------------------------------
157 // Stall funct for wbQ
158 //-----------------------------------------------------------
159 function Bool stall(Instr inst, SFIFO#(WBResult, Rindx) f);
160 case (inst) matches
161 // -- Memory Ops ------------------------------------------------
162 tagged LW .it :
163 return f.find(it.rbase);
164 tagged SW {rsrc:.dreg, rbase:.addr, offset:.o} :
165 return (f.find(addr) || f.find2(dreg));
167 // -- Simple Ops ------------------------------------------------
168 tagged ADDIU .it : return f.find(it.rsrc);
169 tagged SLTI .it : return f.find(it.rsrc);
170 tagged SLTIU .it : return f.find(it.rsrc);
171 tagged ANDI .it : return f.find(it.rsrc);
172 tagged ORI .it : return f.find(it.rsrc);
173 tagged XORI .it : return f.find(it.rsrc);
175 tagged LUI .it : return f.find(it.rdst); //this rds/wrs itself
176 tagged SLL .it : return f.find(it.rsrc);
177 tagged SRL .it : return f.find(it.rsrc);
178 tagged SRA .it : return f.find(it.rsrc);
179 tagged SLLV .it : return (f.find(it.rsrc) || f.find(it.rshamt));
180 tagged SRLV .it : return (f.find(it.rsrc) || f.find(it.rshamt));
181 tagged SRAV .it : return (f.find(it.rsrc) || f.find(it.rshamt));
182 tagged ADDU .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
183 tagged SUBU .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
184 tagged AND .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
185 tagged OR .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
186 tagged XOR .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
187 tagged NOR .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
188 tagged SLT .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
189 tagged SLTU .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
192 // -- Branches --------------------------------------------------
194 tagged BLEZ .it : return (f.find(it.rsrc));
195 tagged BGTZ .it : return (f.find(it.rsrc));
196 tagged BLTZ .it : return (f.find(it.rsrc));
197 tagged BGEZ .it : return (f.find(it.rsrc));
198 tagged BEQ .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
199 tagged BNE .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
201 // -- Jumps -----------------------------------------------------
203 tagged J .it : return False;
204 tagged JR .it : return f.find(it.rsrc);
205 tagged JALR .it : return f.find(it.rsrc);
206 tagged JAL .it : return False;
208 // -- Cop0 ------------------------------------------------------
210 tagged MTC0 .it : return f.find(it.rsrc);
211 tagged MFC0 .it : return False;
213 // -- Illegal ---------------------------------------------------
215 default : return False;
217 endcase
218 endfunction
219 //-----------------------------------------------------------
220 // Reference processor
221 //-----------------------------------------------------------
224 //(* doc = "synthesis attribute ram_style mkProc distributed;" *)
225 //(* synthesize *)
227 module [CONNECTED_MODULE] mkProc( Proc );
229 //-----------------------------------------------------------
230 // Debug port
232 ServerStub_AUDIOCORERRR server_stub <- mkServerStub_AUDIOCORERRR();
235 //-----------------------------------------------------------
236 // State
238 // Standard processor state
240 Reg#(Addr) pc <- mkReg(32'h00001000);
241 Reg#(Epoch) epoch <- mkReg(0);
242 Reg#(Stage) stage <- mkReg(PCgen);
243 BRFile rf <- mkBRFile;
245 // Branch Prediction
246 BranchPred bp <- mkBranchPred();
247 FIFO#(PCStat) execpc <- mkLFIFO();
249 // Pipelines
250 FIFO#(PCStat) pcQ <-mkSizedFIFO(3);
251 SFIFO#(WBResult, Rindx) wbQ <-mkSFIFO(findwbf);
253 // NEED TO ADD CAPABILITY FOR RESET (should be able to just say if I get valid in and these are flagged, clear them.
254 Reg#(Bit#(32)) cp0_tohost <- mkReg(0);
255 Reg#(Bit#(32)) cp0_fromhost <- mkReg(0);
256 Reg#(Bool) cp0_statsEn <- mkReg(False);
257 Reg#(Bool) cp0_audioEOF <- mkReg(False); // Register to let code that EOF is reached
258 Reg#(Bool) cp0_progComp <- mkReg(False); // Register to let processor know that the program is complete (as this terminates)
260 // Memory request/response state
262 FIFO#(InstReq) instReqQ <- mkBFIFO1();
263 FIFO#(InstResp) instRespQ <- mkFIFO();
265 FIFO#(DataReq) dataReqQ <- mkBFIFO1();
266 FIFO#(DataResp) dataRespQ <- mkFIFO();
268 // Audio I/O
269 FIFO#(AudioProcessorUnit) inAudioFifo <- mkFIFO;
270 FIFO#(AudioProcessorUnit) outAudioFifo <- mkFIFO;
273 // Statistics state (2010)
274 // Reg#(Stat) num_cycles <- mkReg(0);
275 // Reg#(Stat) num_inst <- mkReg(0);
277 //Or:
278 // Statistics state
279 STAT num_cycles <- mkStatCounter(`STATS_PROCESSOR_CYCLE_COUNT);
280 STAT num_inst <- mkStatCounter(`STATS_PROCESSOR_INST_COUNT);
282 //-----------------------------------------------------------
283 // Rules
285 (* descending_urgency = "exec, pcgen" *)
286 rule pcgen; //( stage == PCgen );
287 let pc_plus4 = pc + 4;
289 traceTiny("mkProc", "pc",pc);
290 traceTiny("mkProc", "pcgen","P");
291 instReqQ.enq( LoadReq{ addr:pc, tag:epoch} );
293 let next_pc = bp.get(pc);
294 if (next_pc matches tagged Valid .npc)
295 begin
296 pcQ.enq(PCStat {qpc:pc, qnxtpc:npc, qepoch:epoch});
297 pc <= npc;
298 end
299 else
300 begin
301 pcQ.enq(PCStat {qpc:pc, qnxtpc:pc_plus4, qepoch:epoch});
302 pc <= pc_plus4;
303 end
305 endrule
307 rule discard (instRespQ.first() matches tagged LoadResp .ld
308 &&& ld.tag != epoch);
309 traceTiny("mkProc", "stage", "D");
310 instRespQ.deq();
311 endrule
313 (* conflict_free = "exec, writeback" *)
314 rule exec (instRespQ.first() matches tagged LoadResp.ld
315 &&& (ld.tag == epoch)
316 &&& unpack(ld.data) matches .inst
317 &&& !stall(inst, wbQ));
319 // Some abbreviations
320 let sext = signExtend;
321 let zext = zeroExtend;
322 let sra = signedShiftRight;
324 // Get the instruction
326 instRespQ.deq();
327 Instr inst
328 = case ( instRespQ.first() ) matches
329 tagged LoadResp .ld : return unpack(ld.data);
330 tagged StoreResp .st : return ?;
331 endcase;
333 // Get the PC info
334 let instrpc = pcQ.first().qpc;
335 let pc_plus4 = instrpc + 4;
337 Bool branchTaken = False;
338 Addr newPC = pc_plus4;
340 // Tracing
341 traceTiny("mkProc", "exec","X");
342 traceTiny("mkProc", "exInstTiny",inst);
343 traceFull("mkProc", "exInstFull",inst);
345 case ( inst ) matches
347 // -- Memory Ops ------------------------------------------------
349 tagged LW .it :
350 begin
351 Addr addr = rf.rd1(it.rbase) + sext(it.offset);
352 dataReqQ.enq( LoadReq{ addr:addr, tag:zeroExtend(it.rdst) } );
353 wbQ.enq(tagged WB_Load it.rdst);
354 end
356 tagged SW .it :
357 begin
358 Addr addr = rf.rd1(it.rbase) + sext(it.offset);
359 dataReqQ.enq( StoreReq{ tag:0, addr:addr, data:rf.rd2(it.rsrc) } );
360 wbQ.enq(tagged WB_Store);
361 end
363 // -- Simple Ops ------------------------------------------------
365 tagged ADDIU .it :
366 begin
367 Bit#(32) result = rf.rd1(it.rsrc) + sext(it.imm);
368 wbQ.enq(tagged WB_ALU {data:result, dest:it.rdst});
369 end
370 tagged SLTI .it : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:slt( rf.rd1(it.rsrc), sext(it.imm) )});
371 tagged SLTIU .it : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:sltu( rf.rd1(it.rsrc), sext(it.imm) ) });
372 tagged ANDI .it :
373 begin
374 Bit#(32) zext_it_imm = zext(it.imm);
375 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(rf.rd1(it.rsrc) & zext_it_imm)} );
376 end
377 tagged ORI .it :
378 begin
379 Bit#(32) zext_it_imm = zext(it.imm);
380 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(rf.rd1(it.rsrc) | zext_it_imm)} );
381 end
382 tagged XORI .it :
383 begin
384 Bit#(32) zext_it_imm = zext(it.imm);
385 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) ^ zext_it_imm )});
386 end
387 tagged LUI .it :
388 begin
389 Bit#(32) zext_it_imm = zext(it.imm);
390 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(zext_it_imm << 32'd16) });
391 end
393 tagged SLL .it :
394 begin
395 Bit#(32) zext_it_shamt = zext(it.shamt);
396 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) << zext_it_shamt )} );
397 end
398 tagged SRL .it :
399 begin
400 Bit#(32) zext_it_shamt = zext(it.shamt);
401 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) >> zext_it_shamt )});
402 end
403 tagged SRA .it :
404 begin
405 Bit#(32) zext_it_shamt = zext(it.shamt);
406 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( rf.rd1(it.rsrc), zext_it_shamt )});
407 end
408 tagged SLLV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) << rshft(rf.rd2(it.rshamt)) )});
409 tagged SRLV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) >> rshft(rf.rd2(it.rshamt)) )} );
410 tagged SRAV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( rf.rd1(it.rsrc), rshft(rf.rd2(it.rshamt)) ) });
411 tagged ADDU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) + rf.rd2(it.rsrc2) )} );
412 tagged SUBU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) - rf.rd2(it.rsrc2) )} );
413 tagged AND .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) & rf.rd2(it.rsrc2) )} );
414 tagged OR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) | rf.rd2(it.rsrc2) )} );
415 tagged XOR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) ^ rf.rd2(it.rsrc2) )} );
416 tagged NOR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(~(rf.rd1(it.rsrc1) | rf.rd2(it.rsrc2)) )} );
417 tagged SLT .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:slt( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) });
418 tagged SLTU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sltu( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) });
420 // -- Branches --------------------------------------------------
422 tagged BLEZ .it :
423 if ( signedLE( rf.rd1(it.rsrc), 0 ) )
424 begin
425 newPC = pc_plus4 + (sext(it.offset) << 2);
426 branchTaken = True;
427 end
429 tagged BGTZ .it :
430 if ( signedGT( rf.rd1(it.rsrc), 0 ) )
431 begin
432 newPC = pc_plus4 + (sext(it.offset) << 2);
433 branchTaken = True;
434 end
436 tagged BLTZ .it :
437 if ( signedLT( rf.rd1(it.rsrc), 0 ) )
438 begin
439 newPC = pc_plus4 + (sext(it.offset) << 2);
440 branchTaken = True;
441 end
443 tagged BGEZ .it :
444 if ( signedGE( rf.rd1(it.rsrc), 0 ) )
445 begin
446 newPC = pc_plus4 + (sext(it.offset) << 2);
447 branchTaken = True;
448 end
450 tagged BEQ .it :
451 if ( rf.rd1(it.rsrc1) == rf.rd2(it.rsrc2) )
452 begin
453 newPC = pc_plus4 + (sext(it.offset) << 2);
454 branchTaken = True;
455 end
457 tagged BNE .it :
458 if ( rf.rd1(it.rsrc1) != rf.rd2(it.rsrc2) )
459 begin
460 newPC = pc_plus4 + (sext(it.offset) << 2);
461 branchTaken = True;
462 end
464 // -- Jumps -----------------------------------------------------
466 tagged J .it :
467 begin
468 newPC = { pc_plus4[31:28], it.target, 2'b0 };
469 branchTaken = True;
470 end
472 tagged JR .it :
473 begin
474 newPC = rf.rd1(it.rsrc);
475 branchTaken = True;
476 end
478 tagged JAL .it :
479 begin
480 wbQ.enq(tagged WB_ALU {dest:31, data:pc_plus4 });
481 newPC = { pc_plus4[31:28], it.target, 2'b0 };
482 branchTaken = True;
483 end
485 tagged JALR .it :
486 begin
487 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:pc_plus4 });
488 newPC = rf.rd1(it.rsrc);
489 branchTaken = True;
490 end
492 // -- Cop0 ------------------------------------------------------
494 tagged MTC0 .it : //Recieve things from host computer
495 begin
496 $display( " PROCESSOR MTC0 call\n");
497 case ( it.cop0dst )
498 5'd10 : cp0_statsEn <= unpack(truncate(rf.rd1(it.rsrc)));
499 5'd21 : cp0_tohost <= truncate(rf.rd1(it.rsrc));
500 5'd26 : cp0_progComp <= unpack(truncate(rf.rd1(it.rsrc))); //states audio program completed and termination okay
501 5'd27 : outAudioFifo.enq(tagged Sample unpack(truncate(rf.rd1(it.rsrc)))); //Bit size is 16 not 32
502 default :
503 $display( " RTL-ERROR : %m : Illegal MTC0 cop0dst register!" );
504 endcase
505 wbQ.enq(tagged WB_Host 0); //no idea wwhat this actually should be.
506 end
508 //this is host stuff?
509 tagged MFC0 .it : //Things out
510 begin
511 $display( " PROCESSOR MFC0 call\n");
512 case ( it.cop0src )
513 // not actually an ALU instruction but don't have the format otherwise
514 5'd10 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(cp0_statsEn)) });
515 5'd20 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_fromhost });
516 5'd21 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_tohost });
517 5'd25 : begin
518 $display( "**** EOF Requested\n ");
519 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(cp0_audioEOF)) }); // Reading clears bit
520 cp0_audioEOF <= False;
521 end
522 5'd28 : begin
523 $display( "***** Reqesting Sample \n");
524 let sample = inAudioFifo.first(); // is this going to cause perf. delay?
525 if (sample matches tagged Sample .audio) // if it is EOF another rule sets the cp0_audioEOF
526 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(audio)) }); // do I need pack?
527 else $display ( "Audio File EOF Reached. Invalid sample request.");
528 inAudioFifo.deq();
529 end
530 default :
531 $display( " RTL-ERROR : %m : Illegal MFC0 cop0src register!" );
532 endcase
533 end
535 // -- Illegal ---------------------------------------------------
537 default :
538 $display( " RTL-ERROR : %m : Illegal instruction !" );
540 endcase
542 //evaluate branch prediction
543 Addr ppc = pcQ.first().qnxtpc; //predicted branch
544 if (ppc != newPC) //prediction wrong
545 begin
546 epoch <= pcQ.first().qepoch + 1;
547 bp.upd(instrpc, newPC); //update branch predictor
548 pcQ.clear();
549 pc <= newPC;
550 end
551 else
552 pcQ.deq();
554 if ( cp0_statsEn )
555 num_inst.incr();
557 endrule
559 rule writeback; // ( stage == Writeback );
560 traceTiny("mkProc", "writeback","W");
563 // get what to do off the writeback queue
564 wbQ.deq();
565 case (wbQ.first()) matches
566 tagged WB_ALU {data:.res, dest:.rdst} : rf.wr(rdst, res);
567 tagged WB_Load .regWr :
568 begin
569 dataRespQ.deq();
570 if (dataRespQ.first() matches tagged LoadResp .ld)
571 rf.wr(truncate(ld.tag), ld.data); // no need to use Rindx from queue? Duplicate?
572 end
573 tagged WB_Store : dataRespQ.deq();
574 tagged WB_Host .dat : noAction;
575 endcase
577 endrule
579 rule inc_num_cycles;
580 if ( cp0_statsEn )
581 num_cycles.incr();
582 endrule
584 (* conservative_implicit_conditions *)
585 rule handleCPUToHost;
586 let req <- server_stub.acceptRequest_ReadCPUToHost();
587 case (req)
588 0: server_stub.sendResponse_ReadCPUToHost(cp0_tohost);
589 1: server_stub.sendResponse_ReadCPUToHost(pc);
590 2: server_stub.sendResponse_ReadCPUToHost(zeroExtend(pack(stage)));
591 endcase
592 endrule
594 // for now, we don't do anything.
595 // rule connectAudioReqResp;
596 // $display("rlm: PROCESSOR copies a datum\n");
597 // outAudioFifo.enq(inAudioFifo.first());
598 // inAudioFifo.deq;
599 // endrule
601 rule flagAudioEnd (inAudioFifo.first() matches tagged EndOfFile);
602 $display (" Proc Says End Audio Flag Set ");
603 cp0_audioEOF <= True;
604 inAudioFifo.deq;
605 endrule
607 rule sendAudioEnd (cp0_progComp);
608 $display (" PROCESSOR Says Program Complete ");
609 outAudioFifo.enq(tagged EndOfFile);
610 cp0_progComp <= False; //only send one. And functions to reset
611 endrule
613 // Server items & rules:
615 rule feedInput;
616 let command <- server_stub.acceptRequest_SendUnprocessedStream();
617 AudioProcessorControl ctrl = unpack(truncate(command.ctrl));
618 if(ctrl == EndOfFile)
619 begin
620 $display("lsp: PROCESSOR received EOF ");
621 inAudioFifo.enq(tagged EndOfFile);
622 end
623 else
624 begin
625 $display("lsp: PROCESSOR received Data ");
626 inAudioFifo.enq(tagged Sample unpack(truncate(command.sample)));
627 end
628 endrule
631 //-----------------------------------------------------------
632 // Methods
634 interface Client imem_client;
635 interface Get request = fifoToGet(instReqQ);
636 interface Put response = fifoToPut(instRespQ);
637 endinterface
639 interface Client dmem_client;
640 interface Get request = fifoToGet(dataReqQ);
641 interface Put response = fifoToPut(dataRespQ);
642 endinterface
644 interface Get statsEn_get = toGet(asReg(cp0_statsEn));
646 // interface CPUToHost tohost;
647 // method Bit#(32) cpuToHost(int req);
648 // return (case (req)
649 // 0: cp0_tohost;
650 // 1: pc;
651 // 2: zeroExtend(pack(stage));
652 // endcase);
653 // endmethod
654 // endinterface
656 interface Get sampleOutput = fifoToGet(outAudioFifo);
658 endmodule