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1 import RegFile::*;
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2 import RWire::*;
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3 import ProcTypes::*;
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4
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5 `include "asim/provides/low_level_platform_interface.bsh"
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6 `include "asim/provides/soft_connections.bsh"
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7 `include "asim/provides/fpga_components.bsh"
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8 `include "asim/provides/common_services.bsh"
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9
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10 //-----------------------------------------------------------
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11 // Register file module
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12 //-----------------------------------------------------------
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13
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14 interface BRegFile #(type index_t, type data_t);
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15 method Action upd(index_t addr, data_t data);
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16 method data_t sub(index_t addr);
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17 endinterface
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18
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19 module mkBRegFile(RegFile#(index_t, data_t))
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20 provisos (Bits#(index_t, size_index),
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21 Bits#(data_t, size_data),
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22 Eq#(index_t),
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23 Bounded#(index_t) );
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24
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25 LUTRAM#(index_t, data_t) rf <- mkLUTRAM_RegFile();
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26 RWire#(Tuple2#(index_t, data_t)) rw <-mkRWire();
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27
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28 method Action upd (index_t r, data_t d);
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29 rf.upd(r,d);
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30 rw.wset(tuple2(r,d));
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31 endmethod
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32
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33 method data_t sub (index_t r);
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34 case (rw.wget()) matches
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35 tagged Valid {.wr, .d} :
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36 return (wr == r) ? d : rf.sub(r);
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37 tagged Invalid : return rf.sub(r);
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38 endcase
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39 endmethod
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40
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41 endmodule
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