rlm@8: import RegFile::*;
rlm@8: import RWire::*;
rlm@8: import ProcTypes::*;
rlm@8: 
punk@58: `include "asim/provides/low_level_platform_interface.bsh"
punk@58: `include "asim/provides/soft_connections.bsh"
punk@58: `include "asim/provides/fpga_components.bsh"
punk@58: `include "asim/provides/common_services.bsh"
punk@58: 
rlm@8: //-----------------------------------------------------------
rlm@8: // Register file module
rlm@8: //-----------------------------------------------------------
rlm@8: 
rlm@8: interface BRegFile #(type index_t, type data_t);
rlm@8:    method Action upd(index_t addr, data_t data);
rlm@8:    method data_t sub(index_t addr);
rlm@8: endinterface
rlm@8: 
rlm@8: module mkBRegFile(RegFile#(index_t, data_t)) 
rlm@8:    provisos (Bits#(index_t, size_index),
rlm@8: 	     Bits#(data_t, size_data),
rlm@8: 	     Eq#(index_t),
rlm@8: 	     Bounded#(index_t) );
rlm@8: 
punk@58:    LUTRAM#(index_t, data_t) rf <- mkLUTRAM_RegFile();
rlm@8:    RWire#(Tuple2#(index_t, data_t)) rw <-mkRWire();
rlm@8: 
rlm@8:    method Action upd (index_t r, data_t d);
rlm@8:       rf.upd(r,d);
rlm@8:       rw.wset(tuple2(r,d));
rlm@8:    endmethod
rlm@8: 
rlm@8:    method data_t sub (index_t r);
rlm@8:       case (rw.wget()) matches
rlm@8: 	 tagged Valid {.wr, .d} :
rlm@8: 	    return (wr == r) ? d : rf.sub(r);
rlm@8: 	 tagged Invalid : return rf.sub(r);
rlm@8:       endcase
rlm@8:    endmethod
rlm@8:    
rlm@8: endmodule