diff modules/bluespec/Pygar/lab4/BRegFile.bsv @ 58:52f9a257c2ba pygar svn.59

[svn r59] LUTRAMing
author punk
date Mon, 10 May 2010 13:47:12 -0400
parents 74716e9a81cc
children 92041177735c
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     1.1 --- a/modules/bluespec/Pygar/lab4/BRegFile.bsv	Mon May 10 12:17:52 2010 -0400
     1.2 +++ b/modules/bluespec/Pygar/lab4/BRegFile.bsv	Mon May 10 13:47:12 2010 -0400
     1.3 @@ -2,6 +2,11 @@
     1.4  import RWire::*;
     1.5  import ProcTypes::*;
     1.6  
     1.7 +`include "asim/provides/low_level_platform_interface.bsh"
     1.8 +`include "asim/provides/soft_connections.bsh"
     1.9 +`include "asim/provides/fpga_components.bsh"
    1.10 +`include "asim/provides/common_services.bsh"
    1.11 +
    1.12  //-----------------------------------------------------------
    1.13  // Register file module
    1.14  //-----------------------------------------------------------
    1.15 @@ -17,7 +22,7 @@
    1.16  	     Eq#(index_t),
    1.17  	     Bounded#(index_t) );
    1.18  
    1.19 -   RegFile#(index_t, data_t) rf <- mkRegFileWCF(minBound, maxBound);
    1.20 +   LUTRAM#(index_t, data_t) rf <- mkLUTRAM_RegFile();
    1.21     RWire#(Tuple2#(index_t, data_t)) rw <-mkRWire();
    1.22  
    1.23     method Action upd (index_t r, data_t d);