// The MIT License

 

 // Copyright (c) 2009 Massachusetts Institute of Technology

 

 // Permission is hereby granted, free of charge, to any person obtaining a copy

 // of this software and associated documentation files (the "Software"), to deal

 // in the Software without restriction, including without limitation the rights

 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

 // copies of the Software, and to permit persons to whom the Software is

 // furnished to do so, subject to the following conditions:

 

 // The above copyright notice and this permission notice shall be included in

 // all copies or substantial portions of the Software.

 

 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE

 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

 // THE SOFTWARE.

 

 // Author: Kermin Fleming kfleming@mit.edu

 

 import Connectable::*;

 import GetPut::*;

 import ClientServer::*;

 import FIFO::*;

 import SpecialFIFOs::*;

 

 //AWB includes

 `include "asim/provides/low_level_platform_interface.bsh"

 `include "asim/provides/soft_connections.bsh"

 `include "asim/provides/common_services.bsh"

 

 //Local includes

 `include "asim/provides/audio_pipe_types.bsh"  //provides Audio Pipeline interface

 `include "asim/provides/path_types.bsh"

 `include "asim/provides/core.bsh"

 `include "asim/provides/mixer.bsh"

 `include "asim/provides/processor_library.bsh"

 `include "asim/provides/fpga_components.bsh"

 `include "asim/provides/scratchpad_memory.bsh"

 `include "asim/provides/mem_services.bsh"

 `include "asim/dict/VDEV_SCRATCH.bsh"

 

 `include "asim/rrr/remote_client_stub_AUDIOCORERRR.bsh"

 `include "asim/rrr/remote_server_stub_AUDIOCORERRR.bsh"

 

 module [CONNECTED_MODULE] mkConnectedApplication ();

    Core core <- mkCore;

    // RLM::

    // the simple existance of this additional core causes the dreaded

    // beast to emerge --- the ASSERTION FAILURE: sw/model/stats-device.cpp:317 Cycle:0

    //stats device: Duplicate entry DATA_CACHE_NUM_WRITEBACKS, postion 0

    //Core core1 <- mkCore;

    Reg#(int) cycle <- mkReg(0);

 

 //   Reg#(Bit#(32)) ac_fini <- mkReg(0);

 

   //External memory 

   // I'm not comfortable assuming that the memory subsystem is in order  

   // So I'll insert a completion buffer here.

   MEMORY_IFC#(Bit#(18), Bit#(32)) memory <- mkScratchpad(`VDEV_SCRATCH_MEMORY, SCRATCHPAD_CACHED);   //Services Memory items

 

   // Services Samples 

   ClientStub_AUDIOCORERRR client_stub <- mkClientStub_AUDIOCORERRR();   

   // Make this big enough so that several outstanding requests may be supported

   FIFO#(Bit#(MainMemTagSz)) tags <- mkSizedFIFO(8);

 

    //-----------------------------------------------------------

    // Debug port

    

    ServerStub_AUDIOCORERRR server_stub <- mkServerStub_AUDIOCORERRR();   

 

    

   // this is for the tracing

   rule printCycles;

     cycle <= cycle+1;

     $fdisplay(stderr, " => Cycle = %d", cycle);

   endrule

 

   rule sendMemReq;

     let coreReq <- core.mmem_client.request.get;

     case (coreReq) matches 

       tagged LoadReq .load: begin

 //	                      $display("PIPE Load Addr Req %h", load.addr); 

                               //Allocate ROB space

                               memory.readReq(truncate(load.addr>>2));

                               tags.enq(load.tag);

                             end

        tagged StoreReq .store: begin

 //	  	              $display("PIPE Write Addr Req %h", store.addr); 

 	                      memory.write(truncate(store.addr>>2),store.data);

                               end

     endcase

   endrule

   

   rule receiveMemResp;

     let memResp <- memory.readRsp();

     tags.deq;

     core.mmem_client.response.put(tagged LoadResp {data:memResp,

                                                    tag: tags.first});

 //   	                $display("PIPE Receive MemReq %x", memResp); 

   endrule

 

    rule feedOutput;

      let pipelineData <- core.sampleOutput.get();

      AudioProcessorControl endOfFileTag = EndOfFile;

      AudioProcessorControl sampleTag = Data;

 

      case (pipelineData) matches

        tagged EndOfFile: 

        client_stub.makeRequest_SendProcessedStream(zeroExtend(pack(endOfFileTag)),?);

        tagged Sample .sample:client_stub.makeRequest_SendProcessedStream(zeroExtend(pack(sampleTag)), zeroExtend(pack(sample)));

      endcase

    endrule

 

    //*****  SERVER Side  *****

 

 /*   (* conservative_implicit_conditions *)

   rule handleCPUToHost;

    let req <- server_stub.acceptRequest_ReadCPUToHost();

     case (req)

      0: server_stub.sendResponse_ReadCPUToHost(cp0_tohost);

     endcase

   endrule

 */   

    rule feedInput;

      let command <- server_stub.acceptRequest_SendUnprocessedStream();

      AudioProcessorControl ctrl = unpack(truncate(command.ctrl));

 

       Bit#(32) test = unpack(truncate(command.channel));

       $display("rlm: %x", test);

 	   

 

       if(ctrl == EndOfFile)

 	begin

 	   $display("lsp: PIPE received EOF   ");

            core.sampleInput.put(tagged EndOfFile);

        end

      else 

 	begin

 //	   $display("lsp: PIPE received Data   ");

            core.sampleInput.put(tagged Sample unpack(truncate(command.sample)));

        end

    endrule     

 endmodule