diff modules/bluespec/Pygar/core/audioCorePipeline.bsv @ 47:97d1959f7c5c pygar svn.48

[svn r48] changed sctipt to use our own programs, changed rlp.wav and rlp1.wav to be shorter
author rlm
date Wed, 05 May 2010 13:23:58 -0400
parents 4d87fa55a776
children a139cc07b773
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     1.1 --- a/modules/bluespec/Pygar/core/audioCorePipeline.bsv	Wed May 05 12:43:51 2010 -0400
     1.2 +++ b/modules/bluespec/Pygar/core/audioCorePipeline.bsv	Wed May 05 13:23:58 2010 -0400
     1.3 @@ -49,6 +49,11 @@
     1.4  
     1.5  module [CONNECTED_MODULE] mkConnectedApplication ();
     1.6     Core core <- mkCore;
     1.7 +   // RLM::
     1.8 +   // the simple existance of this additional core causes the dreaded
     1.9 +   // beast to emerge --- the ASSERTION FAILURE: sw/model/stats-device.cpp:317 Cycle:0
    1.10 +   //stats device: Duplicate entry DATA_CACHE_NUM_WRITEBACKS, postion 0
    1.11 +   //Core core1 <- mkCore;
    1.12     Reg#(int) cycle <- mkReg(0);
    1.13  
    1.14  //   Reg#(Bit#(32)) ac_fini <- mkReg(0);