|
rlm@8
|
1 import RegFile::*;
|
|
rlm@8
|
2 import RWire::*;
|
|
rlm@8
|
3 import ProcTypes::*;
|
|
rlm@8
|
4
|
|
punk@58
|
5 `include "asim/provides/low_level_platform_interface.bsh"
|
|
punk@58
|
6 `include "asim/provides/soft_connections.bsh"
|
|
punk@58
|
7 `include "asim/provides/fpga_components.bsh"
|
|
punk@58
|
8 `include "asim/provides/common_services.bsh"
|
|
punk@58
|
9
|
|
rlm@8
|
10 //-----------------------------------------------------------
|
|
rlm@8
|
11 // Register file module
|
|
rlm@8
|
12 //-----------------------------------------------------------
|
|
rlm@8
|
13
|
|
punk@62
|
14 interface BRFile;
|
|
punk@62
|
15 method Action wr( Rindx rindx, Bit#(32) data );
|
|
punk@62
|
16 method Action Value Bit#(32) rd1( Rindx rindx );
|
|
punk@62
|
17 method Action Value Bit#(32) rd2( Rindx rindx );
|
|
rlm@8
|
18 endinterface
|
|
rlm@8
|
19
|
|
punk@60
|
20 (* doc = "synthesis attribute ram_style mkBRegFile distributed;" *)
|
|
punk@60
|
21 (* synthesize *)
|
|
punk@62
|
22 module mkBRegFile(BRFile)
|
|
rlm@8
|
23 provisos (Bits#(index_t, size_index),
|
|
rlm@8
|
24 Bits#(data_t, size_data),
|
|
rlm@8
|
25 Eq#(index_t),
|
|
rlm@8
|
26 Bounded#(index_t) );
|
|
rlm@8
|
27
|
|
punk@59
|
28 LUTRAM#(index_t, data_t) rf <- mkLUTRAMU_RegFile();
|
|
rlm@8
|
29 RWire#(Tuple2#(index_t, data_t)) rw <-mkRWire();
|
|
rlm@8
|
30
|
|
punk@62
|
31 method Action wr( Rindx rindx, Bit#(32) data );
|
|
punk@62
|
32 rf.upd( rindx, data );
|
|
punk@62
|
33 rw.wset(tuple2(rindex,data));
|
|
rlm@8
|
34 endmethod
|
|
rlm@8
|
35
|
|
punk@62
|
36 method Bit#(32) rd1 (Rindx r);
|
|
punk@62
|
37 if (r == 0) return 0;
|
|
punk@62
|
38 else begin
|
|
punk@62
|
39 case (rw.wget()) matches
|
|
punk@62
|
40 tagged Valid {.wr, .d} :
|
|
punk@62
|
41 return (wr == r) ? d : rf.sub(r);
|
|
punk@62
|
42 tagged Invalid : return rf.sub(r);
|
|
punk@62
|
43 endcase
|
|
punk@62
|
44 end
|
|
punk@62
|
45 endmethod
|
|
punk@62
|
46
|
|
punk@62
|
47 method Bit#(32) rd2 (Rindx r);
|
|
punk@62
|
48 if (r == 0) return 0;
|
|
punk@62
|
49 else begin
|
|
punk@62
|
50 case (rw.wget()) matches
|
|
punk@62
|
51 tagged Valid {.wr, .d} :
|
|
punk@62
|
52 return (wr == r) ? d : rf.sub(r);
|
|
punk@62
|
53 tagged Invalid : return rf.sub(r);
|
|
punk@62
|
54 endcase
|
|
punk@62
|
55 end
|
|
rlm@8
|
56 endmethod
|
|
rlm@8
|
57
|
|
rlm@8
|
58 endmodule
|
