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comparison modules/bluespec/Pygar/lab4/BRegFile.bsv @ 62:90fa9b289aab pygar svn.63

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[svn r63] synthesis boundaries
author punk
date Mon, 10 May 2010 21:00:49 -0400
parents 6179c07c21d7
children 1d5cbb5343d2
comparison
equal deleted inserted replaced
61:74d2fe78f36a 62:90fa9b289aab
9 9
10 //----------------------------------------------------------- 10 //-----------------------------------------------------------
11 // Register file module 11 // Register file module
12 //----------------------------------------------------------- 12 //-----------------------------------------------------------
13 13
14 interface BRegFile #(type index_t, type data_t); 14 interface BRFile;
15 method Action upd(index_t addr, data_t data); 15 method Action wr( Rindx rindx, Bit#(32) data );
16 method data_t sub(index_t addr); 16 method Action Value Bit#(32) rd1( Rindx rindx );
17 method Action Value Bit#(32) rd2( Rindx rindx );
17 endinterface 18 endinterface
18
19 19
20 (* doc = "synthesis attribute ram_style mkBRegFile distributed;" *) 20 (* doc = "synthesis attribute ram_style mkBRegFile distributed;" *)
21 (* synthesize *) 21 (* synthesize *)
22 module mkBRegFile(RegFile#(index_t, data_t)) 22 module mkBRegFile(BRFile)
23 provisos (Bits#(index_t, size_index), 23 provisos (Bits#(index_t, size_index),
24 Bits#(data_t, size_data), 24 Bits#(data_t, size_data),
25 Eq#(index_t), 25 Eq#(index_t),
26 Bounded#(index_t) ); 26 Bounded#(index_t) );
27 27
28 LUTRAM#(index_t, data_t) rf <- mkLUTRAMU_RegFile(); 28 LUTRAM#(index_t, data_t) rf <- mkLUTRAMU_RegFile();
29 RWire#(Tuple2#(index_t, data_t)) rw <-mkRWire(); 29 RWire#(Tuple2#(index_t, data_t)) rw <-mkRWire();
30 30
31 method Action upd (index_t r, data_t d); 31 method Action wr( Rindx rindx, Bit#(32) data );
32 rf.upd(r,d); 32 rf.upd( rindx, data );
33 rw.wset(tuple2(r,d)); 33 rw.wset(tuple2(rindex,data));
34 endmethod 34 endmethod
35 35
36 method data_t sub (index_t r); 36 method Bit#(32) rd1 (Rindx r);
37 case (rw.wget()) matches 37 if (r == 0) return 0;
38 tagged Valid {.wr, .d} : 38 else begin
39 return (wr == r) ? d : rf.sub(r); 39 case (rw.wget()) matches
40 tagged Invalid : return rf.sub(r); 40 tagged Valid {.wr, .d} :
41 endcase 41 return (wr == r) ? d : rf.sub(r);
42 tagged Invalid : return rf.sub(r);
43 endcase
44 end
45 endmethod
46
47 method Bit#(32) rd2 (Rindx r);
48 if (r == 0) return 0;
49 else begin
50 case (rw.wget()) matches
51 tagged Valid {.wr, .d} :
52 return (wr == r) ? d : rf.sub(r);
53 tagged Invalid : return rf.sub(r);
54 endcase
55 end
42 endmethod 56 endmethod
43 57
44 endmodule 58 endmodule