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changeset 51:9fe5ed4af92d pygar svn.52

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[svn r52] tested having multiple cores
author punk
date Wed, 05 May 2010 17:01:04 -0400
parents 2b18894f75e2
children 49049f97312c
files benchProgs/thru.smips.vmh modules/bluespec/Pygar/core/Processor.bsv modules/bluespec/Pygar/core/Processor.dic modules/bluespec/Pygar/core/ProcessorSystem.dic modules/bluespec/Pygar/core/audioCore.bsv modules/bluespec/Pygar/core/audioCorePipeline.bsv modules/bluespec/Pygar/lab4/DataCache.dic modules/bluespec/Pygar/lab4/DataCacheBlocking.bsv modules/bluespec/Pygar/lab4/InstCache.dic modules/bluespec/Pygar/lab4/InstCacheBlocking.bsv
diffstat 10 files changed, 28 insertions(+), 36 deletions(-) [+]
line wrap: on
line diff
     1.1 --- a/benchProgs/thru.smips.vmh	Wed May 05 15:19:32 2010 -0400
     1.2 +++ b/benchProgs/thru.smips.vmh	Wed May 05 17:01:04 2010 -0400
     1.3 @@ -1,7 +1,7 @@
     1.4  
     1.5  @400      // <__start>
     1.6  3c1d0002  // 00001000 lui $sp,0x2
     1.7 -0c00042c  // 00001004 jal 10b0 <main>
     1.8 +0c00042d  // 00001004 jal 10b4 <main>
     1.9  00000000  // 00001008 nop
    1.10  00000000  // 0000100c nop
    1.11  
    1.12 @@ -53,24 +53,24 @@
    1.13  8fa40010  // 00001090 lw $a0,16($sp)
    1.14  0c00041a  // 00001094 jal 1068 <putSample>
    1.15  08000420  // 00001098 j 1080 <runWithStats+c>
    1.16 -00002021  // 0000109c move $a0,$zero
    1.17 -0c000409  // 000010a0 jal 1024 <setStats>
    1.18 -8fbf0050  // 000010a4 lw $ra,80($sp)
    1.19 -27bd0058  // 000010a8 addiu $sp,$sp,88
    1.20 -03e00008  // 000010ac jr $ra
    1.21 +0c00040c  // 0000109c jal 1030 <setComp>
    1.22 +00002021  // 000010a0 move $a0,$zero
    1.23 +0c000409  // 000010a4 jal 1024 <setStats>
    1.24 +8fbf0050  // 000010a8 lw $ra,80($sp)
    1.25 +27bd0058  // 000010ac addiu $sp,$sp,88
    1.26 +03e00008  // 000010b0 jr $ra
    1.27  
    1.28 -@42c      // <main>
    1.29 -27bdffe8  // 000010b0 addiu $sp,$sp,-24
    1.30 -24040001  // 000010b4 li $a0,1
    1.31 -afbf0010  // 000010b8 sw $ra,16($sp)
    1.32 -0c00041d  // 000010bc jal 1074 <runWithStats>
    1.33 -0c000404  // 000010c0 jal 1010 <verify>
    1.34 -00402021  // 000010c4 move $a0,$v0
    1.35 -0c000406  // 000010c8 jal 1018 <finishTest>
    1.36 -0c00040c  // 000010cc jal 1030 <setComp>
    1.37 -8fbf0010  // 000010d0 lw $ra,16($sp)
    1.38 -27bd0018  // 000010d4 addiu $sp,$sp,24
    1.39 -03e00008  // 000010d8 jr $ra
    1.40 +@42d      // <main>
    1.41 +27bdffe8  // 000010b4 addiu $sp,$sp,-24
    1.42 +24040001  // 000010b8 li $a0,1
    1.43 +afbf0010  // 000010bc sw $ra,16($sp)
    1.44 +0c00041d  // 000010c0 jal 1074 <runWithStats>
    1.45 +0c00040c  // 000010c4 jal 1030 <setComp>
    1.46 +8fbf0010  // 000010c8 lw $ra,16($sp)
    1.47 +27bd0018  // 000010cc addiu $sp,$sp,24
    1.48 +03e00008  // 000010d0 jr $ra
    1.49 +00000000  // 000010d4 nop
    1.50 +00000000  // 000010d8 nop
    1.51  00000000  // 000010dc nop
    1.52  
    1.53  @438      // <_heapend>

     2.1 --- a/modules/bluespec/Pygar/core/Processor.bsv	Wed May 05 15:19:32 2010 -0400
     2.2 +++ b/modules/bluespec/Pygar/core/Processor.bsv	Wed May 05 17:01:04 2010 -0400
     2.3 @@ -1,4 +1,4 @@
     2.4 -/// The MIT License
     2.5 +// The MIT License
     2.6  
     2.7  // Copyright (c) 2009 Massachusetts Institute of Technology
     2.8  
     2.9 @@ -48,7 +48,6 @@
    2.10  //`include "asim/provides/processor_library.bsh" (included above directly)
    2.11  
    2.12  `include "asim/provides/common_services.bsh"
    2.13 -`include "asim/dict/STATS_PROCESSOR.bsh"
    2.14  `include "asim/provides/processor_library.bsh"
    2.15  
    2.16  // Local includes. Look for the correspondingly named .awb files
    2.17 @@ -216,7 +215,7 @@
    2.18  //(* doc = "synthesis attribute ram_style mkProc distributed;" *)
    2.19  //(* synthesize *)
    2.20  
    2.21 -module  [CONNECTED_MODULE] mkProc( Proc );
    2.22 +module mkProc( Proc );
    2.23  
    2.24     //-----------------------------------------------------------
    2.25     // State

     3.1 --- a/modules/bluespec/Pygar/core/Processor.dic	Wed May 05 15:19:32 2010 -0400
     3.2 +++ b/modules/bluespec/Pygar/core/Processor.dic	Wed May 05 17:01:04 2010 -0400
     3.3 @@ -1,2 +0,0 @@
     3.4 -def STATS.PROCESSOR.CYCLE_COUNT  "PROCESSOR: Cycle count: ";
     3.5 -def STATS.PROCESSOR.INST_COUNT  "PROCESSOR: Instruction count: ";

     4.1 --- a/modules/bluespec/Pygar/core/ProcessorSystem.dic	Wed May 05 15:19:32 2010 -0400
     4.2 +++ b/modules/bluespec/Pygar/core/ProcessorSystem.dic	Wed May 05 17:01:04 2010 -0400
     4.3 @@ -1,4 +1,4 @@
     4.4 -def VDEV.SCRATCH.MEMORY     "program.0/program.vmh";
     4.5 +def VDEV.SCRATCH.MEMORYA     "program.0/program.vmh";
     4.6 +def VDEV.SCRATCH.MEMORYB     "program.0/program.vmh";
     4.7  
     4.8  
     4.9 -

     5.1 --- a/modules/bluespec/Pygar/core/audioCore.bsv	Wed May 05 15:19:32 2010 -0400
     5.2 +++ b/modules/bluespec/Pygar/core/audioCore.bsv	Wed May 05 17:01:04 2010 -0400
     5.3 @@ -55,7 +55,7 @@
     5.4     
     5.5  endinterface
     5.6  
     5.7 -module   [CONNECTED_MODULE]  mkCore( Core );
     5.8 +module   [CONNECTED_MODULE]  mkCore#(Integer prog) ( Core );
     5.9     
    5.10  
    5.11    // Instantiate the modules
    5.12 @@ -64,7 +64,7 @@
    5.13    ICache#(InstReq,InstResp) icache <- mkInstCache();
    5.14    DCache#(DataReq,DataResp) dcache <- mkDataCache();
    5.15    MemArb marb <- mkMemArb();
    5.16 -  MEMORY_IFC#(Bit#(18), Bit#(32)) memory <- mkScratchpad(`VDEV_SCRATCH_MEMORY, SCRATCHPAD_CACHED);   //Services Memory items
    5.17 +  MEMORY_IFC#(Bit#(18), Bit#(32)) memory <- mkScratchpad(prog, SCRATCHPAD_CACHED);   //Services Memory items
    5.18  
    5.19    // Make this big enough so that several outstanding requests may be supported
    5.20    FIFO#(Bit#(MainMemTagSz)) tags <- mkSizedFIFO(8);

     6.1 --- a/modules/bluespec/Pygar/core/audioCorePipeline.bsv	Wed May 05 15:19:32 2010 -0400
     6.2 +++ b/modules/bluespec/Pygar/core/audioCorePipeline.bsv	Wed May 05 17:01:04 2010 -0400
     6.3 @@ -40,12 +40,14 @@
     6.4  `include "asim/provides/mixer.bsh"
     6.5  `include "asim/provides/processor_library.bsh"
     6.6  `include "asim/provides/fpga_components.bsh"
     6.7 +`include "asim/dict/VDEV_SCRATCH.bsh"
     6.8  
     6.9  `include "asim/rrr/remote_client_stub_AUDIOCORERRR.bsh"
    6.10  `include "asim/rrr/remote_server_stub_AUDIOCORERRR.bsh"
    6.11  
    6.12  module [CONNECTED_MODULE] mkConnectedApplication ();
    6.13 -   Core core <- mkCore;
    6.14 +   Core core <- mkCore(`VDEV_SCRATCH_MEMORYA);
    6.15 +   Core anotherCore <- mkCore(`VDEV_SCRATCH_MEMORYB);
    6.16     // RLM::
    6.17     // the simple existance of this additional core causes the dreaded
    6.18     // beast to emerge --- the ASSERTION FAILURE: sw/model/stats-device.cpp:317 Cycle:0

     7.1 --- a/modules/bluespec/Pygar/lab4/DataCache.dic	Wed May 05 15:19:32 2010 -0400
     7.2 +++ b/modules/bluespec/Pygar/lab4/DataCache.dic	Wed May 05 17:01:04 2010 -0400
     7.3 @@ -1,3 +0,0 @@
     7.4 -def STATS.DATA_CACHE.NUM_ACCESSES  "DATA_CACHE: Number Of Accesses: ";
     7.5 -def STATS.DATA_CACHE.NUM_MISSES  "DATA_CACHE: Number Of Misses: ";
     7.6 -def STATS.DATA_CACHE.NUM_WRITEBACKS  "DATA_CACHE: Number Of Writebacks: ";
     7.7 \ No newline at end of file

     8.1 --- a/modules/bluespec/Pygar/lab4/DataCacheBlocking.bsv	Wed May 05 15:19:32 2010 -0400
     8.2 +++ b/modules/bluespec/Pygar/lab4/DataCacheBlocking.bsv	Wed May 05 17:01:04 2010 -0400
     8.3 @@ -26,7 +26,6 @@
     8.4  `include "asim/provides/processor_library.bsh"
     8.5  `include "asim/provides/fpga_components.bsh"
     8.6  `include "asim/provides/common_services.bsh"
     8.7 -`include "asim/dict/STATS_DATA_CACHE.bsh"
     8.8  
     8.9  import Connectable::*;
    8.10  import GetPut::*;

     9.1 --- a/modules/bluespec/Pygar/lab4/InstCache.dic	Wed May 05 15:19:32 2010 -0400
     9.2 +++ b/modules/bluespec/Pygar/lab4/InstCache.dic	Wed May 05 17:01:04 2010 -0400
     9.3 @@ -1,3 +1,1 @@
     9.4 -def STATS.INST_CACHE.NUM_ACCESSES  "INST_CACHE: Number Of Accesses: ";
     9.5 -def STATS.INST_CACHE.NUM_MISSES  "INST_CACHE: Number Of Misses: ";
     9.6 -def STATS.INST_CACHE.NUM_EVICTIONS  "INST_CACHE: Number Of Evictions: ";
     9.7 +

    10.1 --- a/modules/bluespec/Pygar/lab4/InstCacheBlocking.bsv	Wed May 05 15:19:32 2010 -0400
    10.2 +++ b/modules/bluespec/Pygar/lab4/InstCacheBlocking.bsv	Wed May 05 17:01:04 2010 -0400
    10.3 @@ -35,7 +35,6 @@
    10.4  `include "asim/provides/processor_library.bsh"
    10.5  `include "asim/provides/fpga_components.bsh"
    10.6  `include "asim/provides/common_services.bsh"
    10.7 -`include "asim/dict/STATS_INST_CACHE.bsh"
    10.8  
    10.9  interface ICache#( type req_t, type resp_t );
   10.10