# HG changeset patch
# User punk
# Date 1273093264 14400
# Node ID 9fe5ed4af92d55f0719a5a1d213aa1cc8d3a0139
# Parent  2b18894f75e22c4a2a97c6051aa485b81fc8cb0b
[svn r52] tested having multiple cores

diff -r 2b18894f75e2 -r 9fe5ed4af92d benchProgs/thru.smips.vmh
--- a/benchProgs/thru.smips.vmh	Wed May 05 15:19:32 2010 -0400
+++ b/benchProgs/thru.smips.vmh	Wed May 05 17:01:04 2010 -0400
@@ -1,7 +1,7 @@
 
 @400      // <__start>
 3c1d0002  // 00001000 lui $sp,0x2
-0c00042c  // 00001004 jal 10b0 <main>
+0c00042d  // 00001004 jal 10b4 <main>
 00000000  // 00001008 nop
 00000000  // 0000100c nop
 
@@ -53,24 +53,24 @@
 8fa40010  // 00001090 lw $a0,16($sp)
 0c00041a  // 00001094 jal 1068 <putSample>
 08000420  // 00001098 j 1080 <runWithStats+c>
-00002021  // 0000109c move $a0,$zero
-0c000409  // 000010a0 jal 1024 <setStats>
-8fbf0050  // 000010a4 lw $ra,80($sp)
-27bd0058  // 000010a8 addiu $sp,$sp,88
-03e00008  // 000010ac jr $ra
+0c00040c  // 0000109c jal 1030 <setComp>
+00002021  // 000010a0 move $a0,$zero
+0c000409  // 000010a4 jal 1024 <setStats>
+8fbf0050  // 000010a8 lw $ra,80($sp)
+27bd0058  // 000010ac addiu $sp,$sp,88
+03e00008  // 000010b0 jr $ra
 
-@42c      // <main>
-27bdffe8  // 000010b0 addiu $sp,$sp,-24
-24040001  // 000010b4 li $a0,1
-afbf0010  // 000010b8 sw $ra,16($sp)
-0c00041d  // 000010bc jal 1074 <runWithStats>
-0c000404  // 000010c0 jal 1010 <verify>
-00402021  // 000010c4 move $a0,$v0
-0c000406  // 000010c8 jal 1018 <finishTest>
-0c00040c  // 000010cc jal 1030 <setComp>
-8fbf0010  // 000010d0 lw $ra,16($sp)
-27bd0018  // 000010d4 addiu $sp,$sp,24
-03e00008  // 000010d8 jr $ra
+@42d      // <main>
+27bdffe8  // 000010b4 addiu $sp,$sp,-24
+24040001  // 000010b8 li $a0,1
+afbf0010  // 000010bc sw $ra,16($sp)
+0c00041d  // 000010c0 jal 1074 <runWithStats>
+0c00040c  // 000010c4 jal 1030 <setComp>
+8fbf0010  // 000010c8 lw $ra,16($sp)
+27bd0018  // 000010cc addiu $sp,$sp,24
+03e00008  // 000010d0 jr $ra
+00000000  // 000010d4 nop
+00000000  // 000010d8 nop
 00000000  // 000010dc nop
 
 @438      // <_heapend>
diff -r 2b18894f75e2 -r 9fe5ed4af92d modules/bluespec/Pygar/core/Processor.bsv
--- a/modules/bluespec/Pygar/core/Processor.bsv	Wed May 05 15:19:32 2010 -0400
+++ b/modules/bluespec/Pygar/core/Processor.bsv	Wed May 05 17:01:04 2010 -0400
@@ -1,4 +1,4 @@
-/// The MIT License
+// The MIT License
 
 // Copyright (c) 2009 Massachusetts Institute of Technology
 
@@ -48,7 +48,6 @@
 //`include "asim/provides/processor_library.bsh" (included above directly)
 
 `include "asim/provides/common_services.bsh"
-`include "asim/dict/STATS_PROCESSOR.bsh"
 `include "asim/provides/processor_library.bsh"
 
 // Local includes. Look for the correspondingly named .awb files
@@ -216,7 +215,7 @@
 //(* doc = "synthesis attribute ram_style mkProc distributed;" *)
 //(* synthesize *)
 
-module  [CONNECTED_MODULE] mkProc( Proc );
+module mkProc( Proc );
 
    //-----------------------------------------------------------
    // State
diff -r 2b18894f75e2 -r 9fe5ed4af92d modules/bluespec/Pygar/core/Processor.dic
--- a/modules/bluespec/Pygar/core/Processor.dic	Wed May 05 15:19:32 2010 -0400
+++ b/modules/bluespec/Pygar/core/Processor.dic	Wed May 05 17:01:04 2010 -0400
@@ -1,2 +0,0 @@
-def STATS.PROCESSOR.CYCLE_COUNT  "PROCESSOR: Cycle count: ";
-def STATS.PROCESSOR.INST_COUNT  "PROCESSOR: Instruction count: ";
diff -r 2b18894f75e2 -r 9fe5ed4af92d modules/bluespec/Pygar/core/ProcessorSystem.dic
--- a/modules/bluespec/Pygar/core/ProcessorSystem.dic	Wed May 05 15:19:32 2010 -0400
+++ b/modules/bluespec/Pygar/core/ProcessorSystem.dic	Wed May 05 17:01:04 2010 -0400
@@ -1,4 +1,4 @@
-def VDEV.SCRATCH.MEMORY     "program.0/program.vmh";
+def VDEV.SCRATCH.MEMORYA     "program.0/program.vmh";
+def VDEV.SCRATCH.MEMORYB     "program.0/program.vmh";
 
 
-
diff -r 2b18894f75e2 -r 9fe5ed4af92d modules/bluespec/Pygar/core/audioCore.bsv
--- a/modules/bluespec/Pygar/core/audioCore.bsv	Wed May 05 15:19:32 2010 -0400
+++ b/modules/bluespec/Pygar/core/audioCore.bsv	Wed May 05 17:01:04 2010 -0400
@@ -55,7 +55,7 @@
    
 endinterface
 
-module   [CONNECTED_MODULE]  mkCore( Core );
+module   [CONNECTED_MODULE]  mkCore#(Integer prog) ( Core );
    
 
   // Instantiate the modules
@@ -64,7 +64,7 @@
   ICache#(InstReq,InstResp) icache <- mkInstCache();
   DCache#(DataReq,DataResp) dcache <- mkDataCache();
   MemArb marb <- mkMemArb();
-  MEMORY_IFC#(Bit#(18), Bit#(32)) memory <- mkScratchpad(`VDEV_SCRATCH_MEMORY, SCRATCHPAD_CACHED);   //Services Memory items
+  MEMORY_IFC#(Bit#(18), Bit#(32)) memory <- mkScratchpad(prog, SCRATCHPAD_CACHED);   //Services Memory items
 
   // Make this big enough so that several outstanding requests may be supported
   FIFO#(Bit#(MainMemTagSz)) tags <- mkSizedFIFO(8);
diff -r 2b18894f75e2 -r 9fe5ed4af92d modules/bluespec/Pygar/core/audioCorePipeline.bsv
--- a/modules/bluespec/Pygar/core/audioCorePipeline.bsv	Wed May 05 15:19:32 2010 -0400
+++ b/modules/bluespec/Pygar/core/audioCorePipeline.bsv	Wed May 05 17:01:04 2010 -0400
@@ -40,12 +40,14 @@
 `include "asim/provides/mixer.bsh"
 `include "asim/provides/processor_library.bsh"
 `include "asim/provides/fpga_components.bsh"
+`include "asim/dict/VDEV_SCRATCH.bsh"
 
 `include "asim/rrr/remote_client_stub_AUDIOCORERRR.bsh"
 `include "asim/rrr/remote_server_stub_AUDIOCORERRR.bsh"
 
 module [CONNECTED_MODULE] mkConnectedApplication ();
-   Core core <- mkCore;
+   Core core <- mkCore(`VDEV_SCRATCH_MEMORYA);
+   Core anotherCore <- mkCore(`VDEV_SCRATCH_MEMORYB);
    // RLM::
    // the simple existance of this additional core causes the dreaded
    // beast to emerge --- the ASSERTION FAILURE: sw/model/stats-device.cpp:317 Cycle:0
diff -r 2b18894f75e2 -r 9fe5ed4af92d modules/bluespec/Pygar/lab4/DataCache.dic
--- a/modules/bluespec/Pygar/lab4/DataCache.dic	Wed May 05 15:19:32 2010 -0400
+++ b/modules/bluespec/Pygar/lab4/DataCache.dic	Wed May 05 17:01:04 2010 -0400
@@ -1,3 +0,0 @@
-def STATS.DATA_CACHE.NUM_ACCESSES  "DATA_CACHE: Number Of Accesses: ";
-def STATS.DATA_CACHE.NUM_MISSES  "DATA_CACHE: Number Of Misses: ";
-def STATS.DATA_CACHE.NUM_WRITEBACKS  "DATA_CACHE: Number Of Writebacks: ";
\ No newline at end of file
diff -r 2b18894f75e2 -r 9fe5ed4af92d modules/bluespec/Pygar/lab4/DataCacheBlocking.bsv
--- a/modules/bluespec/Pygar/lab4/DataCacheBlocking.bsv	Wed May 05 15:19:32 2010 -0400
+++ b/modules/bluespec/Pygar/lab4/DataCacheBlocking.bsv	Wed May 05 17:01:04 2010 -0400
@@ -26,7 +26,6 @@
 `include "asim/provides/processor_library.bsh"
 `include "asim/provides/fpga_components.bsh"
 `include "asim/provides/common_services.bsh"
-`include "asim/dict/STATS_DATA_CACHE.bsh"
 
 import Connectable::*;
 import GetPut::*;
diff -r 2b18894f75e2 -r 9fe5ed4af92d modules/bluespec/Pygar/lab4/InstCache.dic
--- a/modules/bluespec/Pygar/lab4/InstCache.dic	Wed May 05 15:19:32 2010 -0400
+++ b/modules/bluespec/Pygar/lab4/InstCache.dic	Wed May 05 17:01:04 2010 -0400
@@ -1,3 +1,1 @@
-def STATS.INST_CACHE.NUM_ACCESSES  "INST_CACHE: Number Of Accesses: ";
-def STATS.INST_CACHE.NUM_MISSES  "INST_CACHE: Number Of Misses: ";
-def STATS.INST_CACHE.NUM_EVICTIONS  "INST_CACHE: Number Of Evictions: ";
+
diff -r 2b18894f75e2 -r 9fe5ed4af92d modules/bluespec/Pygar/lab4/InstCacheBlocking.bsv
--- a/modules/bluespec/Pygar/lab4/InstCacheBlocking.bsv	Wed May 05 15:19:32 2010 -0400
+++ b/modules/bluespec/Pygar/lab4/InstCacheBlocking.bsv	Wed May 05 17:01:04 2010 -0400
@@ -35,7 +35,6 @@
 `include "asim/provides/processor_library.bsh"
 `include "asim/provides/fpga_components.bsh"
 `include "asim/provides/common_services.bsh"
-`include "asim/dict/STATS_INST_CACHE.bsh"
 
 interface ICache#( type req_t, type resp_t );