Mercurial > pygar
changeset 1:91a1f76ddd62 pygar svn.2
[svn r2] Adding initial lab 5 source
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1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 1.2 +++ b/common/BranchPred.bsv Tue Apr 13 17:34:33 2010 -0400 1.3 @@ -0,0 +1,41 @@ 1.4 +import RegFile::*; 1.5 +import ProcTypes::*; 1.6 +import FIFO::*; 1.7 + 1.8 +typedef Maybe#(Addr) BrPred; 1.9 +typedef Bit#(4) BPindx; 1.10 + 1.11 +typedef struct {Addr brpc; Addr nextpc;} BrPair deriving (Bits,Eq); 1.12 + 1.13 +typedef union tagged 1.14 +{ 1.15 + BrPair Valid; 1.16 + void Invalid; 1.17 +} CBranchPath deriving(Bits, Eq); // have the cache start out invalid and add valid values. 1.18 + 1.19 +interface BranchPred; 1.20 + method BrPred get(Addr pres); //returns a maybe type that is invalid if no predition 1.21 + method Action upd(Addr pres, Addr next); 1.22 +endinterface 1.23 + 1.24 +module mkBranchPred(BranchPred); 1.25 + 1.26 + //state variables 1.27 + RegFile#(BPindx, CBranchPath) bcache <- mkRegFileFull(); // cache to hold 16 (based on BPindx) 1.28 + 1.29 + method Action upd(Addr pres, Addr next); 1.30 + BrPair brp; 1.31 + brp = BrPair {brpc:pres, nextpc:next}; 1.32 + bcache.upd(pres[5:2], tagged Valid brp); 1.33 + endmethod 1.34 + 1.35 + method BrPred get(Addr prespc); 1.36 + BPindx rd = prespc[5:2]; 1.37 + let cbp = bcache.sub(rd); 1.38 + if (cbp matches tagged Valid .bp &&& bp.brpc == prespc) //make sure that the read value was actually put there and the full address matches 1.39 + return tagged Valid bp.nextpc; 1.40 + else return Invalid; 1.41 + endmethod 1.42 + 1.43 +endmodule 1.44 +
2.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 2.2 +++ b/common/InterfaceTypes.bsv Tue Apr 13 17:34:33 2010 -0400 2.3 @@ -0,0 +1,28 @@ 2.4 +import Trace::*; 2.5 + 2.6 +`define MAX_VOICES 4 2.7 +`define MAX_CORES 16 2.8 +`define MAX_PATH_LENGTH 8 2.9 + 2.10 +// The path is hardwired and so should never be stored in a register. Therefore int type rather than Bit type 2.11 + 2.12 +typedef Bit#(32) MemAddr; 2.13 +typedef Int#(TLog#(MAX_CORES+2)) PathId; 2.14 + 2.15 +//The mixer is identified as PathId 0, path end is max 2.16 +PathId mixerId = 0; 2.17 +PathId endId = MAX_CORES+1; 2.18 + 2.19 +// Path is array of path ids 2.20 +typedef Vector#(MAX_PATH_LENGTH, PathId) CorePath; 2.21 +typedef struct 2.22 +{ 2.23 + MemAddr startAddr; 2.24 + CorePath route; 2.25 + } FullPath deriving(Eq, Bits); 2.26 + 2.27 +Vector#(MAX_VOICES, FullPath) routeTable; 2.28 +routeTable[0] = {startAddr: 12, route: {1, 2, 3, 0, endId, endId, endId, endId}} 2.29 + 2.30 + 2.31 +
3.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 3.2 +++ b/common/ProcTypes.bsv Tue Apr 13 17:34:33 2010 -0400 3.3 @@ -0,0 +1,375 @@ 3.4 + 3.5 +import Trace::*; 3.6 + 3.7 +//---------------------------------------------------------------------- 3.8 +// Other typedefs 3.9 +//---------------------------------------------------------------------- 3.10 + 3.11 +typedef Bit#(32) Addr; 3.12 +typedef Int#(18) Stat; 3.13 + 3.14 +//---------------------------------------------------------------------- 3.15 +// Basic instruction type 3.16 +//---------------------------------------------------------------------- 3.17 + 3.18 +typedef Bit#(5) Rindx; 3.19 +typedef Bit#(16) Simm; 3.20 +typedef Bit#(16) Zimm; 3.21 +typedef Bit#(8) Epoch; 3.22 +typedef Bit#(5) Shamt; 3.23 +typedef Bit#(26) Target; 3.24 +typedef Bit#(5) CP0indx; 3.25 +typedef Bit#(32) Data; 3.26 + 3.27 +typedef enum 3.28 +{ 3.29 + Taken, 3.30 + NotTaken 3.31 +} 3.32 + Direction 3.33 + deriving(Bits,Eq); 3.34 + 3.35 + 3.36 +//---------------------------------------------------------------------- 3.37 +// Pipeline typedefs 3.38 +//---------------------------------------------------------------------- 3.39 + 3.40 +typedef union tagged 3.41 +{ 3.42 + Tuple2#(Rindx,Data) ALUWB; 3.43 + Rindx MemWB; 3.44 + Tuple2#(Rindx,Data) CoWB; 3.45 +} 3.46 + WritebackType 3.47 + deriving(Bits,Eq); 3.48 + 3.49 +//////////////////////// 3.50 +// I Add Writeback queue type 3.51 +//////////// 3.52 +typedef union tagged 3.53 +{ 3.54 + struct {Bit#(32) data; Rindx dest; } WB_ALU; 3.55 + Bit#(32) WB_Host; 3.56 + Rindx WB_Load; 3.57 + void WB_Store; 3.58 +} 3.59 +WBResult deriving(Eq, Bits); 3.60 + 3.61 +//typedef struct{Addr qpc; Addr qnxtpc; Epoch qepoch;} PCStat deriving(Eq, Bits); 3.62 +typedef struct{Addr qpc; Epoch qepoch;} PCStat deriving(Eq, Bits); 3.63 + 3.64 +typedef union tagged 3.65 +{ 3.66 + 3.67 + struct { Rindx rbase; Rindx rdst; Simm offset; } LW; 3.68 + struct { Rindx rbase; Rindx rsrc; Simm offset; } SW; 3.69 + 3.70 + struct { Rindx rsrc; Rindx rdst; Simm imm; } ADDIU; 3.71 + struct { Rindx rsrc; Rindx rdst; Simm imm; } SLTI; 3.72 + struct { Rindx rsrc; Rindx rdst; Simm imm; } SLTIU; 3.73 + struct { Rindx rsrc; Rindx rdst; Zimm imm; } ANDI; 3.74 + struct { Rindx rsrc; Rindx rdst; Zimm imm; } ORI; 3.75 + struct { Rindx rsrc; Rindx rdst; Zimm imm; } XORI; 3.76 + struct { Rindx rdst; Zimm imm; } LUI; 3.77 + 3.78 + struct { Rindx rsrc; Rindx rdst; Shamt shamt; } SLL; 3.79 + struct { Rindx rsrc; Rindx rdst; Shamt shamt; } SRL; 3.80 + struct { Rindx rsrc; Rindx rdst; Shamt shamt; } SRA; 3.81 + struct { Rindx rsrc; Rindx rdst; Rindx rshamt; } SLLV; 3.82 + struct { Rindx rsrc; Rindx rdst; Rindx rshamt; } SRLV; 3.83 + struct { Rindx rsrc; Rindx rdst; Rindx rshamt; } SRAV; 3.84 + struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } ADDU; 3.85 + struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } SUBU; 3.86 + struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } AND; 3.87 + struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } OR; 3.88 + struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } XOR; 3.89 + struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } NOR; 3.90 + struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } SLT; 3.91 + struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } SLTU; 3.92 + 3.93 + struct { Target target; } J; 3.94 + struct { Target target; } JAL; 3.95 + struct { Rindx rsrc; } JR; 3.96 + struct { Rindx rsrc; Rindx rdst; } JALR; 3.97 + struct { Rindx rsrc1; Rindx rsrc2; Simm offset; } BEQ; 3.98 + struct { Rindx rsrc1; Rindx rsrc2; Simm offset; } BNE; 3.99 + struct { Rindx rsrc; Simm offset; } BLEZ; 3.100 + struct { Rindx rsrc; Simm offset; } BGTZ; 3.101 + struct { Rindx rsrc; Simm offset; } BLTZ; 3.102 + struct { Rindx rsrc; Simm offset; } BGEZ; 3.103 + 3.104 + struct { Rindx rdst; CP0indx cop0src; } MFC0; 3.105 + struct { Rindx rsrc; CP0indx cop0dst; } MTC0; 3.106 + 3.107 + void ILLEGAL; 3.108 + 3.109 +} 3.110 +Instr deriving(Eq); 3.111 + 3.112 +//---------------------------------------------------------------------- 3.113 +// Pack and Unpack 3.114 +//---------------------------------------------------------------------- 3.115 + 3.116 +Bit#(6) opFUNC = 6'b000000; Bit#(6) fcSLL = 6'b000000; 3.117 +Bit#(6) opRT = 6'b000001; Bit#(6) fcSRL = 6'b000010; 3.118 +Bit#(6) opRS = 6'b010000; Bit#(6) fcSRA = 6'b000011; 3.119 + Bit#(6) fcSLLV = 6'b000100; 3.120 +Bit#(6) opLW = 6'b100011; Bit#(6) fcSRLV = 6'b000110; 3.121 +Bit#(6) opSW = 6'b101011; Bit#(6) fcSRAV = 6'b000111; 3.122 + Bit#(6) fcADDU = 6'b100001; 3.123 +Bit#(6) opADDIU = 6'b001001; Bit#(6) fcSUBU = 6'b100011; 3.124 +Bit#(6) opSLTI = 6'b001010; Bit#(6) fcAND = 6'b100100; 3.125 +Bit#(6) opSLTIU = 6'b001011; Bit#(6) fcOR = 6'b100101; 3.126 +Bit#(6) opANDI = 6'b001100; Bit#(6) fcXOR = 6'b100110; 3.127 +Bit#(6) opORI = 6'b001101; Bit#(6) fcNOR = 6'b100111; 3.128 +Bit#(6) opXORI = 6'b001110; Bit#(6) fcSLT = 6'b101010; 3.129 +Bit#(6) opLUI = 6'b001111; Bit#(6) fcSLTU = 6'b101011; 3.130 + 3.131 +Bit#(6) opJ = 6'b000010; 3.132 +Bit#(6) opJAL = 6'b000011; 3.133 +Bit#(6) fcJR = 6'b001000; 3.134 +Bit#(6) fcJALR = 6'b001001; 3.135 +Bit#(6) opBEQ = 6'b000100; 3.136 +Bit#(6) opBNE = 6'b000101; 3.137 +Bit#(6) opBLEZ = 6'b000110; 3.138 +Bit#(6) opBGTZ = 6'b000111; 3.139 +Bit#(5) rtBLTZ = 5'b00000; 3.140 +Bit#(5) rtBGEZ = 5'b00001; 3.141 + 3.142 +Bit#(5) rsMFC0 = 5'b00000; 3.143 +Bit#(5) rsMTC0 = 5'b00100; 3.144 + 3.145 +instance Bits#(Instr,32); 3.146 + 3.147 + // Pack Function 3.148 + 3.149 + function Bit#(32) pack( Instr instr ); 3.150 + 3.151 + case ( instr ) matches 3.152 + 3.153 + tagged LW .it : return { opLW, it.rbase, it.rdst, it.offset }; 3.154 + tagged SW .it : return { opSW, it.rbase, it.rsrc, it.offset }; 3.155 + 3.156 + tagged ADDIU .it : return { opADDIU, it.rsrc, it.rdst, it.imm }; 3.157 + tagged SLTI .it : return { opSLTI, it.rsrc, it.rdst, it.imm }; 3.158 + tagged SLTIU .it : return { opSLTIU, it.rsrc, it.rdst, it.imm }; 3.159 + tagged ANDI .it : return { opANDI, it.rsrc, it.rdst, it.imm }; 3.160 + tagged ORI .it : return { opORI, it.rsrc, it.rdst, it.imm }; 3.161 + tagged XORI .it : return { opXORI, it.rsrc, it.rdst, it.imm }; 3.162 + tagged LUI .it : return { opLUI, 5'b0, it.rdst, it.imm }; 3.163 + 3.164 + tagged SLL .it : return { opFUNC, 5'b0, it.rsrc, it.rdst, it.shamt, fcSLL }; 3.165 + tagged SRL .it : return { opFUNC, 5'b0, it.rsrc, it.rdst, it.shamt, fcSRL }; 3.166 + tagged SRA .it : return { opFUNC, 5'b0, it.rsrc, it.rdst, it.shamt, fcSRA }; 3.167 + 3.168 + tagged SLLV .it : return { opFUNC, it.rshamt, it.rsrc, it.rdst, 5'b0, fcSLLV }; 3.169 + tagged SRLV .it : return { opFUNC, it.rshamt, it.rsrc, it.rdst, 5'b0, fcSRLV }; 3.170 + tagged SRAV .it : return { opFUNC, it.rshamt, it.rsrc, it.rdst, 5'b0, fcSRAV }; 3.171 + 3.172 + tagged ADDU .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcADDU }; 3.173 + tagged SUBU .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcSUBU }; 3.174 + tagged AND .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcAND }; 3.175 + tagged OR .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcOR }; 3.176 + tagged XOR .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcXOR }; 3.177 + tagged NOR .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcNOR }; 3.178 + tagged SLT .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcSLT }; 3.179 + tagged SLTU .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcSLTU }; 3.180 + 3.181 + tagged J .it : return { opJ, it.target }; 3.182 + tagged JAL .it : return { opJAL, it.target }; 3.183 + tagged JR .it : return { opFUNC, it.rsrc, 5'b0, 5'b0, 5'b0, fcJR }; 3.184 + tagged JALR .it : return { opFUNC, it.rsrc, 5'b0, it.rdst, 5'b0, fcJALR }; 3.185 + tagged BEQ .it : return { opBEQ, it.rsrc1, it.rsrc2, it.offset }; 3.186 + tagged BNE .it : return { opBNE, it.rsrc1, it.rsrc2, it.offset }; 3.187 + tagged BLEZ .it : return { opBLEZ, it.rsrc, 5'b0, it.offset }; 3.188 + tagged BGTZ .it : return { opBGTZ, it.rsrc, 5'b0, it.offset }; 3.189 + tagged BLTZ .it : return { opRT, it.rsrc, rtBLTZ, it.offset }; 3.190 + tagged BGEZ .it : return { opRT, it.rsrc, rtBGEZ, it.offset }; 3.191 + 3.192 + tagged MFC0 .it : return { opRS, rsMFC0, it.rdst, it.cop0src, 11'b0 }; 3.193 + tagged MTC0 .it : return { opRS, rsMTC0, it.rsrc, it.cop0dst, 11'b0 }; 3.194 + 3.195 + endcase 3.196 + 3.197 + endfunction 3.198 + 3.199 + // Unpack Function 3.200 + 3.201 + function Instr unpack( Bit#(32) instrBits ); 3.202 + 3.203 + let opcode = instrBits[ 31 : 26 ]; 3.204 + let rs = instrBits[ 25 : 21 ]; 3.205 + let rt = instrBits[ 20 : 16 ]; 3.206 + let rd = instrBits[ 15 : 11 ]; 3.207 + let shamt = instrBits[ 10 : 6 ]; 3.208 + let funct = instrBits[ 5 : 0 ]; 3.209 + let imm = instrBits[ 15 : 0 ]; 3.210 + let target = instrBits[ 25 : 0 ]; 3.211 + 3.212 + case ( opcode ) 3.213 + 3.214 + opLW : return LW { rbase:rs, rdst:rt, offset:imm }; 3.215 + opSW : return SW { rbase:rs, rsrc:rt, offset:imm }; 3.216 + opADDIU : return ADDIU { rsrc:rs, rdst:rt, imm:imm }; 3.217 + opSLTI : return SLTI { rsrc:rs, rdst:rt, imm:imm }; 3.218 + opSLTIU : return SLTIU { rsrc:rs, rdst:rt, imm:imm }; 3.219 + opANDI : return ANDI { rsrc:rs, rdst:rt, imm:imm }; 3.220 + opORI : return ORI { rsrc:rs, rdst:rt, imm:imm }; 3.221 + opXORI : return XORI { rsrc:rs, rdst:rt, imm:imm }; 3.222 + opLUI : return LUI { rdst:rt, imm:imm }; 3.223 + opJ : return J { target:target }; 3.224 + opJAL : return JAL { target:target }; 3.225 + opBEQ : return BEQ { rsrc1:rs, rsrc2:rt, offset:imm }; 3.226 + opBNE : return BNE { rsrc1:rs, rsrc2:rt, offset:imm }; 3.227 + opBLEZ : return BLEZ { rsrc:rs, offset:imm }; 3.228 + opBGTZ : return BGTZ { rsrc:rs, offset:imm }; 3.229 + 3.230 + opFUNC : 3.231 + case ( funct ) 3.232 + fcSLL : return SLL { rsrc:rt, rdst:rd, shamt:shamt }; 3.233 + fcSRL : return SRL { rsrc:rt, rdst:rd, shamt:shamt }; 3.234 + fcSRA : return SRA { rsrc:rt, rdst:rd, shamt:shamt }; 3.235 + fcSLLV : return SLLV { rsrc:rt, rdst:rd, rshamt:rs }; 3.236 + fcSRLV : return SRLV { rsrc:rt, rdst:rd, rshamt:rs }; 3.237 + fcSRAV : return SRAV { rsrc:rt, rdst:rd, rshamt:rs }; 3.238 + fcADDU : return ADDU { rsrc1:rs, rsrc2:rt, rdst:rd }; 3.239 + fcSUBU : return SUBU { rsrc1:rs, rsrc2:rt, rdst:rd }; 3.240 + fcAND : return AND { rsrc1:rs, rsrc2:rt, rdst:rd }; 3.241 + fcOR : return OR { rsrc1:rs, rsrc2:rt, rdst:rd }; 3.242 + fcXOR : return XOR { rsrc1:rs, rsrc2:rt, rdst:rd }; 3.243 + fcNOR : return NOR { rsrc1:rs, rsrc2:rt, rdst:rd }; 3.244 + fcSLT : return SLT { rsrc1:rs, rsrc2:rt, rdst:rd }; 3.245 + fcSLTU : return SLTU { rsrc1:rs, rsrc2:rt, rdst:rd }; 3.246 + fcJR : return JR { rsrc:rs }; 3.247 + fcJALR : return JALR { rsrc:rs, rdst:rd }; 3.248 + default : return ILLEGAL; 3.249 + endcase 3.250 + 3.251 + opRT : 3.252 + case ( rt ) 3.253 + rtBLTZ : return BLTZ { rsrc:rs, offset:imm }; 3.254 + rtBGEZ : return BGEZ { rsrc:rs, offset:imm }; 3.255 + default : return ILLEGAL; 3.256 + endcase 3.257 + 3.258 + opRS : 3.259 + case ( rs ) 3.260 + rsMFC0 : return MFC0 { rdst:rt, cop0src:rd }; 3.261 + rsMTC0 : return MTC0 { rsrc:rt, cop0dst:rd }; 3.262 + default : return ILLEGAL; 3.263 + endcase 3.264 + 3.265 + default : return ILLEGAL; 3.266 + 3.267 + endcase 3.268 + 3.269 + endfunction 3.270 + 3.271 +endinstance 3.272 + 3.273 +//---------------------------------------------------------------------- 3.274 +// Trace 3.275 +//---------------------------------------------------------------------- 3.276 + 3.277 +instance Traceable#(Instr); 3.278 + 3.279 + function Action traceTiny( String loc, String ttag, Instr inst ); 3.280 + case ( inst ) matches 3.281 + 3.282 + tagged LW .it : $fdisplay(stderr, " => %s:%s lw", loc, ttag ); 3.283 + tagged SW .it : $fdisplay(stderr, " => %s:%s sw", loc, ttag ); 3.284 + 3.285 + tagged ADDIU .it : $fdisplay(stderr, " => %s:%s addi", loc, ttag ); 3.286 + tagged SLTI .it : $fdisplay(stderr, " => %s:%s sli", loc, ttag ); 3.287 + tagged SLTIU .it : $fdisplay(stderr, " => %s:%s sliu", loc, ttag ); 3.288 + tagged ANDI .it : $fdisplay(stderr, " => %s:%s andi", loc, ttag ); 3.289 + tagged ORI .it : $fdisplay(stderr, " => %s:%s ori", loc, ttag ); 3.290 + tagged XORI .it : $fdisplay(stderr, " => %s:%s xori", loc, ttag ); 3.291 + tagged LUI .it : $fdisplay(stderr, " => %s:%s lui", loc, ttag ); 3.292 + 3.293 + tagged SLL .it : $fdisplay(stderr, " => %s:%s sll", loc, ttag ); 3.294 + tagged SRL .it : $fdisplay(stderr, " => %s:%s srl", loc, ttag ); 3.295 + tagged SRA .it : $fdisplay(stderr, " => %s:%s sra", loc, ttag ); 3.296 + tagged SLLV .it : $fdisplay(stderr, " => %s:%s sllv", loc, ttag ); 3.297 + tagged SRLV .it : $fdisplay(stderr, " => %s:%s srlv", loc, ttag ); 3.298 + tagged SRAV .it : $fdisplay(stderr, " => %s:%s srav", loc, ttag ); 3.299 + 3.300 + tagged ADDU .it : $fdisplay(stderr, " => %s:%s addu", loc, ttag ); 3.301 + tagged SUBU .it : $fdisplay(stderr, " => %s:%s subu", loc, ttag ); 3.302 + tagged AND .it : $fdisplay(stderr, " => %s:%s and", loc, ttag ); 3.303 + tagged OR .it : $fdisplay(stderr, " => %s:%s or", loc, ttag ); 3.304 + tagged XOR .it : $fdisplay(stderr, " => %s:%s xor", loc, ttag ); 3.305 + tagged NOR .it : $fdisplay(stderr, " => %s:%s nor", loc, ttag ); 3.306 + tagged SLT .it : $fdisplay(stderr, " => %s:%s slt", loc, ttag ); 3.307 + tagged SLTU .it : $fdisplay(stderr, " => %s:%s sltu", loc, ttag ); 3.308 + 3.309 + tagged J .it : $fdisplay(stderr, " => %s:%s j", loc, ttag ); 3.310 + tagged JAL .it : $fdisplay(stderr, " => %s:%s jal", loc, ttag ); 3.311 + tagged JR .it : $fdisplay(stderr, " => %s:%s jr", loc, ttag ); 3.312 + tagged JALR .it : $fdisplay(stderr, " => %s:%s jalr", loc, ttag ); 3.313 + tagged BEQ .it : $fdisplay(stderr, " => %s:%s beq", loc, ttag ); 3.314 + tagged BNE .it : $fdisplay(stderr, " => %s:%s bne", loc, ttag ); 3.315 + tagged BLEZ .it : $fdisplay(stderr, " => %s:%s blez", loc, ttag ); 3.316 + tagged BGTZ .it : $fdisplay(stderr, " => %s:%s bgtz", loc, ttag ); 3.317 + tagged BLTZ .it : $fdisplay(stderr, " => %s:%s bltz", loc, ttag ); 3.318 + tagged BGEZ .it : $fdisplay(stderr, " => %s:%s bgez", loc, ttag ); 3.319 + 3.320 + tagged MFC0 .it : $fdisplay(stderr, " => %s:%s mfc0", loc, ttag ); 3.321 + tagged MTC0 .it : $fdisplay(stderr, " => %s:%s mtc0", loc, ttag ); 3.322 + 3.323 + tagged ILLEGAL : $fdisplay(stderr, " => %s:%s ill", loc, ttag ); 3.324 + 3.325 + endcase 3.326 + endfunction 3.327 + 3.328 + function Action traceFull( String loc, String ttag, Instr inst ); 3.329 + case ( inst ) matches 3.330 + 3.331 + tagged LW .it : $fdisplay(stderr, " => %s:%s lw r%0d, 0x%x(r%0d)", loc, ttag, it.rdst, it.offset, it.rbase ); 3.332 + tagged SW .it : $fdisplay(stderr, " => %s:%s sw r%0d, 0x%x(r%0d)", loc, ttag, it.rsrc, it.offset, it.rbase ); 3.333 + 3.334 + tagged ADDIU .it : $fdisplay(stderr, " => %s:%s addiu r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); 3.335 + tagged SLTI .it : $fdisplay(stderr, " => %s:%s slti r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); 3.336 + tagged SLTIU .it : $fdisplay(stderr, " => %s:%s sltiu r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); 3.337 + tagged ANDI .it : $fdisplay(stderr, " => %s:%s andi r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); 3.338 + tagged ORI .it : $fdisplay(stderr, " => %s:%s ori r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); 3.339 + tagged XORI .it : $fdisplay(stderr, " => %s:%s xori r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); 3.340 + tagged LUI .it : $fdisplay(stderr, " => %s:%s lui r%0d, 0x%x", loc, ttag, it.rdst, it.imm ); 3.341 + 3.342 + tagged SLL .it : $fdisplay(stderr, " => %s:%s sll r%0d, r%0d, %0d", loc, ttag, it.rdst, it.rsrc, it.shamt ); 3.343 + tagged SRL .it : $fdisplay(stderr, " => %s:%s srl r%0d, r%0d, %0d", loc, ttag, it.rdst, it.rsrc, it.shamt ); 3.344 + tagged SRA .it : $fdisplay(stderr, " => %s:%s sra r%0d, r%0d, %0d", loc, ttag, it.rdst, it.rsrc, it.shamt ); 3.345 + tagged SLLV .it : $fdisplay(stderr, " => %s:%s sllv r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc, it.rshamt ); 3.346 + tagged SRLV .it : $fdisplay(stderr, " => %s:%s srlv r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc, it.rshamt ); 3.347 + tagged SRAV .it : $fdisplay(stderr, " => %s:%s srav r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc, it.rshamt ); 3.348 + 3.349 + tagged ADDU .it : $fdisplay(stderr, " => %s:%s addu r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); 3.350 + tagged SUBU .it : $fdisplay(stderr, " => %s:%s subu r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); 3.351 + tagged AND .it : $fdisplay(stderr, " => %s:%s and r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); 3.352 + tagged OR .it : $fdisplay(stderr, " => %s:%s or r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); 3.353 + tagged XOR .it : $fdisplay(stderr, " => %s:%s xor r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); 3.354 + tagged NOR .it : $fdisplay(stderr, " => %s:%s nor r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); 3.355 + tagged SLT .it : $fdisplay(stderr, " => %s:%s slt r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); 3.356 + tagged SLTU .it : $fdisplay(stderr, " => %s:%s sltu r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); 3.357 + 3.358 + tagged J .it : $fdisplay(stderr, " => %s:%s j 0x%x", loc, ttag, it.target ); 3.359 + tagged JAL .it : $fdisplay(stderr, " => %s:%s jal 0x%x", loc, ttag, it.target ); 3.360 + tagged JR .it : $fdisplay(stderr, " => %s:%s jr r%0d", loc, ttag, it.rsrc ); 3.361 + tagged JALR .it : $fdisplay(stderr, " => %s:%s jalr r%0d", loc, ttag, it.rsrc ); 3.362 + tagged BEQ .it : $fdisplay(stderr, " => %s:%s beq r%0d, r%0d, 0x%x", loc, ttag, it.rsrc1, it.rsrc2, it.offset ); 3.363 + tagged BNE .it : $fdisplay(stderr, " => %s:%s bne r%0d, r%0d, 0x%x", loc, ttag, it.rsrc1, it.rsrc2, it.offset ); 3.364 + tagged BLEZ .it : $fdisplay(stderr, " => %s:%s blez r%0d, 0x%x", loc, ttag, it.rsrc, it.offset ); 3.365 + tagged BGTZ .it : $fdisplay(stderr, " => %s:%s bgtz r%0d, 0x%x", loc, ttag, it.rsrc, it.offset ); 3.366 + tagged BLTZ .it : $fdisplay(stderr, " => %s:%s bltz r%0d, 0x%x", loc, ttag, it.rsrc, it.offset ); 3.367 + tagged BGEZ .it : $fdisplay(stderr, " => %s:%s bgez r%0d, 0x%x", loc, ttag, it.rsrc, it.offset ); 3.368 + 3.369 + tagged MFC0 .it : $fdisplay(stderr, " => %s:%s mfc0 r%0d, cpr%0d", loc, ttag, it.rdst, it.cop0src ); 3.370 + tagged MTC0 .it : $fdisplay(stderr, " => %s:%s mtc0 r%0d, cpr%0d", loc, ttag, it.rsrc, it.cop0dst ); 3.371 + 3.372 + tagged ILLEGAL : $fdisplay(stderr, " => %s:%s illegal instruction", loc, ttag ); 3.373 + 3.374 + endcase 3.375 + endfunction 3.376 + 3.377 +endinstance 3.378 +
4.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 4.2 +++ b/core/scemi/Bridge.bsv Tue Apr 13 17:34:33 2010 -0400 4.3 @@ -0,0 +1,21 @@ 4.4 +`ifdef SCEMI_PCIE_VIRTEX5 4.5 +`ifdef BOARD_ML507 4.6 +`include "Bridge_VIRTEX5_ML50X.bsv" 4.7 +`endif 4.8 +`ifdef BOARD_XUPV5 4.9 +`include "Bridge_VIRTEX5_ML50X.bsv" 4.10 +`endif 4.11 +`endif 4.12 + 4.13 +`ifdef SCEMI_PCIE_DINI 4.14 +`ifdef BOARD_7002 4.15 +`include "Bridge_DINI_7002.bsv" 4.16 +`endif 4.17 +`ifdef BOARD_7006 4.18 +`include "Bridge_DINI_7006.bsv" 4.19 +`endif 4.20 +`endif 4.21 + 4.22 +`ifdef SCEMI_TCP 4.23 +`include "Bridge_TCP.bsv" 4.24 +`endif
5.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 5.2 +++ b/core/scemi/SceMiLayer.bsv Tue Apr 13 17:34:33 2010 -0400 5.3 @@ -0,0 +1,150 @@ 5.4 + 5.5 +import ClientServer::*; 5.6 +import FIFO::*; 5.7 +import GetPut::*; 5.8 +import DefaultValue::*; 5.9 +import SceMi::*; 5.10 +import Clocks::*; 5.11 + 5.12 +import Core::*; 5.13 +import ProcTypes::*; 5.14 +import Processor::*; 5.15 +import DataCacheBlocking::*; 5.16 +import InstCacheBlocking::*; 5.17 + 5.18 +interface DutWrapper; 5.19 + interface Core core; 5.20 + 5.21 + // We use a Bit#(1) instead of void because Bluespec Sce-Mi doesn't appear 5.22 + // to support sending void over the PCIe link yet. 5.23 + interface Put#(Bit#(1)) doreset; 5.24 +endinterface 5.25 + 5.26 +(* synthesize *) 5.27 +module [Module] mkDutWrapper (DutWrapper); 5.28 + 5.29 + Clock clk <- exposeCurrentClock; 5.30 + MakeResetIfc myrst <- mkReset(2000, True, clk); 5.31 + 5.32 + Core coreifc <- mkCore(reset_by myrst.new_rst); 5.33 + 5.34 + // For tracing 5.35 + Reg#(int) cycle <- mkReg(0); 5.36 + rule printCycles; 5.37 + cycle <= cycle + 1; 5.38 + $fdisplay(stderr, " => Cycle = %d", cycle); 5.39 + endrule 5.40 + 5.41 + interface Core core = coreifc; 5.42 + 5.43 + interface Put doreset; 5.44 + method Action put(Bit#(1) x); 5.45 + cycle <= 0; 5.46 + myrst.assertReset(); 5.47 + endmethod 5.48 + endinterface 5.49 + 5.50 +endmodule 5.51 + 5.52 +module [SceMiModule] mkSceMiLayer(); 5.53 + 5.54 + SceMiClockConfiguration conf = defaultValue; 5.55 + 5.56 + SceMiClockPortIfc clk_port <- mkSceMiClockPort(conf); 5.57 + DutWrapper dut <- buildDut(mkDutWrapper, clk_port); 5.58 + 5.59 + Empty mmem <- mkClientXactor(dut.core.mmem_client, clk_port); 5.60 + Empty tohost <- mkCPUToHostXactor(dut.core.tohost, clk_port); 5.61 + Empty stats <- mkCoreStatsXactor(dut.core.stats, clk_port); 5.62 + Empty doreset <- mkPutXactor(dut.doreset, clk_port); 5.63 + 5.64 + Empty shutdown <- mkShutdownXactor(); 5.65 + 5.66 +endmodule 5.67 + 5.68 +module [SceMiModule] mkCPUToHostXactor#(CPUToHost tohost, SceMiClockPortIfc clk_port ) (Empty); 5.69 + 5.70 + // Access the controlled clock and reset 5.71 + Clock cclock = clk_port.cclock; 5.72 + Reset creset = clk_port.creset; 5.73 + 5.74 + // req belongs entirely to the controlled clock domain. We'll use the 5.75 + // clock domain crossings already implemented by the Bluespec people (in 5.76 + // the Put and Get transactors), because they know about such things 5.77 + // better than I do. 5.78 + FIFO#(int) req <- mkFIFO(clocked_by cclock, reset_by creset); 5.79 + 5.80 + Get#(Bit#(32)) resp = interface Get; 5.81 + method ActionValue#(Bit#(32)) get(); 5.82 + req.deq(); 5.83 + return tohost.cpuToHost(req.first()); 5.84 + endmethod 5.85 + endinterface; 5.86 + 5.87 + Empty request <- mkPutXactor(toPut(req), clk_port); 5.88 + Empty response <- mkGetXactor(resp, clk_port); 5.89 + 5.90 +endmodule 5.91 + 5.92 +typedef enum { 5.93 + DCACHE_ACCESSES, DCACHE_MISSES, DCACHE_WRITEBACKS, 5.94 + ICACHE_ACCESSES, ICACHE_MISSES, ICACHE_EVICTIONS, 5.95 + PROC_INST, PROC_CYCLES 5.96 +} StatID deriving(Bits, Eq); 5.97 + 5.98 +module [SceMiModule] mkCoreStatsXactor#(CoreStats stats, SceMiClockPortIfc clk_port) (Empty); 5.99 + 5.100 + // Access the controlled clock and reset 5.101 + Clock cclock = clk_port.cclock; 5.102 + Reset creset = clk_port.creset; 5.103 + 5.104 + // Again, req and resp belong to the controlled clock domain. 5.105 + FIFO#(StatID) req <- mkFIFO(clocked_by cclock, reset_by creset); 5.106 + FIFO#(Stat) resp <- mkFIFO(clocked_by cclock, reset_by creset); 5.107 + 5.108 + rule handleRequest (True); 5.109 + case (req.first()) 5.110 + DCACHE_ACCESSES: begin 5.111 + let x <- stats.dcache.num_accesses.get(); 5.112 + resp.enq(x); 5.113 + end 5.114 + DCACHE_MISSES: begin 5.115 + let x <- stats.dcache.num_misses.get(); 5.116 + resp.enq(x); 5.117 + end 5.118 + DCACHE_WRITEBACKS: begin 5.119 + let x <- stats.dcache.num_writebacks.get(); 5.120 + resp.enq(x); 5.121 + end 5.122 + ICACHE_ACCESSES: begin 5.123 + let x <- stats.icache.num_accesses.get(); 5.124 + resp.enq(x); 5.125 + end 5.126 + ICACHE_MISSES: begin 5.127 + let x <- stats.icache.num_misses.get(); 5.128 + resp.enq(x); 5.129 + end 5.130 + ICACHE_EVICTIONS: begin 5.131 + let x <- stats.icache.num_evictions.get(); 5.132 + resp.enq(x); 5.133 + end 5.134 + PROC_INST: begin 5.135 + let x <- stats.proc.num_inst.get(); 5.136 + resp.enq(x); 5.137 + end 5.138 + PROC_CYCLES: begin 5.139 + let x <- stats.proc.num_cycles.get(); 5.140 + resp.enq(x); 5.141 + end 5.142 + endcase 5.143 + req.deq(); 5.144 + endrule 5.145 + 5.146 + Server#(StatID, Stat) server = interface Server; 5.147 + interface Get response = toGet(resp); 5.148 + interface Put request = toPut(req); 5.149 + endinterface; 5.150 + 5.151 + Empty xx <- mkServerXactor(server, clk_port); 5.152 +endmodule 5.153 +
6.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 6.2 +++ b/core/sim/bdir_dut/BFIFO.bi Tue Apr 13 17:34:33 2010 -0400 6.3 @@ -0,0 +1,23 @@ 6.4 +signature BFIFO where { 6.5 +import ¶Assert®¶; 6.6 + 6.7 +import ¶FIFOF_®¶; 6.8 + 6.9 +import ¶FIFOF®¶; 6.10 + 6.11 +import ¶FIFO®¶; 6.12 + 6.13 +import ¶List®¶; 6.14 + 6.15 +BFIFO.mkBFIFO1 :: (¶Prelude®¶.¶Bits®¶ item_t item_sz, ¶Prelude®¶.¶IsModule®¶ _m__ _c__) => 6.16 + _m__ (¶FIFO®¶.¶FIFO®¶ item_t); 6.17 + 6.18 +BFIFO.mkSizedBFIFO :: (¶Prelude®¶.¶Bits®¶ item_t item_sz, ¶Prelude®¶.¶IsModule®¶ _m__ _c__) => 6.19 + ¶Prelude®¶.¶Integer®¶ -> _m__ (¶FIFO®¶.¶FIFO®¶ item_t); 6.20 + 6.21 +BFIFO.mkBFIFOF1 :: (¶Prelude®¶.¶Bits®¶ item_t item_sz, ¶Prelude®¶.¶IsModule®¶ _m__ _c__) => 6.22 + _m__ (¶FIFOF®¶.¶FIFOF®¶ item_t); 6.23 + 6.24 +BFIFO.mkBFIFO_16 :: (¶Prelude®¶.¶IsModule®¶ _m__ _c__) => 6.25 + _m__ (¶FIFO®¶.¶FIFO®¶ (¶Prelude®¶.¶Bit®¶ 16)) 6.26 +}
7.1 Binary file core/sim/bdir_dut/BFIFO.bo has changed
8.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 8.2 +++ b/core/sim/bdir_dut/BRegFile.bi Tue Apr 13 17:34:33 2010 -0400 8.3 @@ -0,0 +1,54 @@ 8.4 +signature BRegFile where { 8.5 +import ¶Counter®¶; 8.6 + 8.7 +import ¶FIFOF_®¶; 8.8 + 8.9 +import ¶FIFOF®¶; 8.10 + 8.11 +import ¶FIFO®¶; 8.12 + 8.13 +import ¶Inout®¶; 8.14 + 8.15 +import ¶List®¶; 8.16 + 8.17 +import ¶Clocks®¶; 8.18 + 8.19 +import ¶ListN®¶; 8.20 + 8.21 +import ¶PrimArray®¶; 8.22 + 8.23 +import ¶RWire®¶; 8.24 + 8.25 +import ¶RegFile®¶; 8.26 + 8.27 +import ¶Vector®¶; 8.28 + 8.29 +import ¶Connectable®¶; 8.30 + 8.31 +import ¶GetPut®¶; 8.32 + 8.33 +import ¶ClientServer®¶; 8.34 + 8.35 +import Trace; 8.36 + 8.37 +import ProcTypes; 8.38 + 8.39 +interface (BRegFile.BRegFile :: * -> * -> *) index_t data_t = { 8.40 + BRegFile.upd :: index_t -> data_t -> ¶Prelude®¶.¶Action®¶ {-# arg_names = [addr, ¡data¡] #-}; 8.41 + BRegFile.sub :: index_t -> data_t {-# arg_names = [addr] #-} 8.42 +}; 8.43 + 8.44 +instance BRegFile (¶Prelude®¶.¶PrimMakeUndefined®¶ data_t) => 8.45 + ¶Prelude®¶.¶PrimMakeUndefined®¶ (BRegFile.BRegFile index_t data_t); 8.46 + 8.47 +instance BRegFile ¶Prelude®¶.¶PrimDeepSeqCond®¶ (BRegFile.BRegFile index_t data_t); 8.48 + 8.49 +instance BRegFile ¶Prelude®¶.¶PrimMakeUninitialized®¶ (BRegFile.BRegFile index_t data_t); 8.50 + 8.51 +BRegFile.mkBRegFile :: (¶Prelude®¶.¶Bounded®¶ index_t, 8.52 + ¶Prelude®¶.¶Eq®¶ index_t, 8.53 + ¶Prelude®¶.¶Bits®¶ data_t size_data, 8.54 + ¶Prelude®¶.¶Bits®¶ index_t size_index, 8.55 + ¶Prelude®¶.¶IsModule®¶ _m__ _c__) => 8.56 + _m__ (¶RegFile®¶.¶RegFile®¶ index_t data_t) 8.57 +}
9.1 Binary file core/sim/bdir_dut/BRegFile.bo has changed
10.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 10.2 +++ b/core/sim/bdir_dut/BranchPred.bi Tue Apr 13 17:34:33 2010 -0400 10.3 @@ -0,0 +1,78 @@ 10.4 +signature BranchPred where { 10.5 +import ¶Counter®¶; 10.6 + 10.7 +import ¶FIFOF_®¶; 10.8 + 10.9 +import ¶FIFOF®¶; 10.10 + 10.11 +import ¶FIFO®¶; 10.12 + 10.13 +import ¶Inout®¶; 10.14 + 10.15 +import ¶List®¶; 10.16 + 10.17 +import ¶Clocks®¶; 10.18 + 10.19 +import ¶ListN®¶; 10.20 + 10.21 +import ¶PrimArray®¶; 10.22 + 10.23 +import ¶RegFile®¶; 10.24 + 10.25 +import ¶Vector®¶; 10.26 + 10.27 +import ¶Connectable®¶; 10.28 + 10.29 +import ¶GetPut®¶; 10.30 + 10.31 +import ¶ClientServer®¶; 10.32 + 10.33 +import Trace; 10.34 + 10.35 +import ProcTypes; 10.36 + 10.37 +type (BranchPred.BrPred :: *) = ¶Prelude®¶.¶Maybe®¶ ProcTypes.Addr; 10.38 + 10.39 +type (BranchPred.BPindx :: *) = ¶Prelude®¶.¶Bit®¶ 4; 10.40 + 10.41 +struct (BranchPred.BrPair :: *) = { 10.42 + BranchPred.brpc :: ProcTypes.Addr; 10.43 + BranchPred.nextpc :: ProcTypes.Addr 10.44 +}; 10.45 + 10.46 +instance BranchPred ¶Prelude®¶.¶PrimMakeUndefined®¶ BranchPred.BrPair; 10.47 + 10.48 +instance BranchPred ¶Prelude®¶.¶PrimDeepSeqCond®¶ BranchPred.BrPair; 10.49 + 10.50 +instance BranchPred ¶Prelude®¶.¶PrimMakeUninitialized®¶ BranchPred.BrPair; 10.51 + 10.52 +instance BranchPred ¶Prelude®¶.¶Bits®¶ BranchPred.BrPair 64; 10.53 + 10.54 +instance BranchPred ¶Prelude®¶.¶Eq®¶ BranchPred.BrPair; 10.55 + 10.56 +data (BranchPred.CBranchPath :: *) = BranchPred.Valid BranchPred.BrPair | BranchPred.Invalid (); 10.57 + 10.58 +instance BranchPred ¶Prelude®¶.¶PrimMakeUndefined®¶ BranchPred.CBranchPath; 10.59 + 10.60 +instance BranchPred ¶Prelude®¶.¶PrimDeepSeqCond®¶ BranchPred.CBranchPath; 10.61 + 10.62 +instance BranchPred ¶Prelude®¶.¶PrimMakeUninitialized®¶ BranchPred.CBranchPath; 10.63 + 10.64 +instance BranchPred ¶Prelude®¶.¶Bits®¶ BranchPred.CBranchPath 65; 10.65 + 10.66 +instance BranchPred ¶Prelude®¶.¶Eq®¶ BranchPred.CBranchPath; 10.67 + 10.68 +interface (BranchPred.BranchPred :: *) = { 10.69 + BranchPred.get :: ProcTypes.Addr -> BranchPred.BrPred {-# arg_names = [pres] #-}; 10.70 + BranchPred.upd :: ProcTypes.Addr -> ProcTypes.Addr -> ¶Prelude®¶.¶Action®¶ {-# arg_names = [pres, 10.71 + next] #-} 10.72 +}; 10.73 + 10.74 +instance BranchPred ¶Prelude®¶.¶PrimMakeUndefined®¶ BranchPred.BranchPred; 10.75 + 10.76 +instance BranchPred ¶Prelude®¶.¶PrimDeepSeqCond®¶ BranchPred.BranchPred; 10.77 + 10.78 +instance BranchPred ¶Prelude®¶.¶PrimMakeUninitialized®¶ BranchPred.BranchPred; 10.79 + 10.80 +BranchPred.mkBranchPred :: (¶Prelude®¶.¶IsModule®¶ _m__ _c__) => _m__ BranchPred.BranchPred 10.81 +}
11.1 Binary file core/sim/bdir_dut/BranchPred.bo has changed
12.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 12.2 +++ b/core/sim/bdir_dut/Bridge.bi Tue Apr 13 17:34:33 2010 -0400 12.3 @@ -0,0 +1,137 @@ 12.4 +signature Bridge where { 12.5 +import ¶Assert®¶; 12.6 + 12.7 +import ¶ConfigReg®¶; 12.8 + 12.9 +import ¶Counter®¶; 12.10 + 12.11 +import ¶DReg®¶; 12.12 + 12.13 +import ¶EdgeDetect®¶; 12.14 + 12.15 +import ¶FIFOF_®¶; 12.16 + 12.17 +import ¶FIFOF®¶; 12.18 + 12.19 +import ¶FIFO®¶; 12.20 + 12.21 +import ¶HList®¶; 12.22 + 12.23 +import ¶Inout®¶; 12.24 + 12.25 +import ¶List®¶; 12.26 + 12.27 +import BFIFO; 12.28 + 12.29 +import ¶Clocks®¶; 12.30 + 12.31 +import ¶DiniPCIE®¶; 12.32 + 12.33 +import ¶ListN®¶; 12.34 + 12.35 +import ¶ModuleContextCore®¶; 12.36 + 12.37 +import ¶ModuleContext®¶; 12.38 + 12.39 +import ¶Monad®¶; 12.40 + 12.41 +import ¶PrimArray®¶; 12.42 + 12.43 +import ¶RWire®¶; 12.44 + 12.45 +import ¶RegFile®¶; 12.46 + 12.47 +import ¶Real®¶; 12.48 + 12.49 +import ¶RevertingVirtualReg®¶; 12.50 + 12.51 +import ¶Reserved®¶; 12.52 + 12.53 +import SFIFO; 12.54 + 12.55 +import ¶Vector®¶; 12.56 + 12.57 +import ¶BRAMCore®¶; 12.58 + 12.59 +import ¶BUtils®¶; 12.60 + 12.61 +import ¶Connectable®¶; 12.62 + 12.63 +import ¶DefaultValue®¶; 12.64 + 12.65 +import ¶Gearbox®¶; 12.66 + 12.67 +import ¶GetPut®¶; 12.68 + 12.69 +import ¶AlignedFIFOs®¶; 12.70 + 12.71 +import ¶ClientServer®¶; 12.72 + 12.73 +import ¶FIFOLevel®¶; 12.74 + 12.75 +import ¶SceMiDefines®¶; 12.76 + 12.77 +import ¶SceMiProxies®¶; 12.78 + 12.79 +import ¶SpecialFIFOs®¶; 12.80 + 12.81 +import ¶SceMiInternals®¶; 12.82 + 12.83 +import ¶SceMiAldecMacros®¶; 12.84 + 12.85 +import ¶SceMiEveMacros®¶; 12.86 + 12.87 +import ¶SceMiMacros®¶; 12.88 + 12.89 +import ¶TieOff®¶; 12.90 + 12.91 +import Trace; 12.92 + 12.93 +import MemTypes; 12.94 + 12.95 +import MemArb; 12.96 + 12.97 +import ProcTypes; 12.98 + 12.99 +import BRegFile; 12.100 + 12.101 +import BranchPred; 12.102 + 12.103 +import DataCacheBlocking; 12.104 + 12.105 +import InstCacheBlocking; 12.106 + 12.107 +import Processor; 12.108 + 12.109 +import Core; 12.110 + 12.111 +import ¶UnitAppendList®¶; 12.112 + 12.113 +import ¶XilinxCells®¶; 12.114 + 12.115 +import ¶SceMiClocks®¶; 12.116 + 12.117 +import ¶SceMiDiniPCIE®¶; 12.118 + 12.119 +import ¶SceMiTCP®¶; 12.120 + 12.121 +import ¶XilinxPCIE®¶; 12.122 + 12.123 +import ¶SceMiVirtex5PCIE®¶; 12.124 + 12.125 +import ¶SceMiPCIE®¶; 12.126 + 12.127 +import ¶SceMiCore®¶; 12.128 + 12.129 +import ¶SceMiXactors®¶; 12.130 + 12.131 +import ¶SceMiSerialProbe®¶; 12.132 + 12.133 +import ¶SceMi®¶; 12.134 + 12.135 +import SceMiLayer; 12.136 + 12.137 +Bridge.lt :: ¶SceMiDefines®¶.¶SceMiLinkType®¶; 12.138 + 12.139 +Bridge.mkBridge :: (¶Prelude®¶.¶IsModule®¶ _m__ _c__) => _m__ ¶Prelude®¶.¶Empty®¶ 12.140 +}
13.1 Binary file core/sim/bdir_dut/Bridge.bo has changed
14.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 14.2 +++ b/core/sim/bdir_dut/Core.bi Tue Apr 13 17:34:33 2010 -0400 14.3 @@ -0,0 +1,85 @@ 14.4 +signature Core where { 14.5 +import ¶Assert®¶; 14.6 + 14.7 +import ¶ConfigReg®¶; 14.8 + 14.9 +import ¶Counter®¶; 14.10 + 14.11 +import ¶FIFOF_®¶; 14.12 + 14.13 +import ¶FIFOF®¶; 14.14 + 14.15 +import ¶FIFO®¶; 14.16 + 14.17 +import ¶Inout®¶; 14.18 + 14.19 +import ¶List®¶; 14.20 + 14.21 +import BFIFO; 14.22 + 14.23 +import ¶Clocks®¶; 14.24 + 14.25 +import ¶ListN®¶; 14.26 + 14.27 +import ¶Monad®¶; 14.28 + 14.29 +import ¶PrimArray®¶; 14.30 + 14.31 +import ¶RWire®¶; 14.32 + 14.33 +import ¶RegFile®¶; 14.34 + 14.35 +import SFIFO; 14.36 + 14.37 +import ¶Vector®¶; 14.38 + 14.39 +import ¶Connectable®¶; 14.40 + 14.41 +import ¶GetPut®¶; 14.42 + 14.43 +import ¶ClientServer®¶; 14.44 + 14.45 +import Trace; 14.46 + 14.47 +import MemTypes; 14.48 + 14.49 +import MemArb; 14.50 + 14.51 +import ProcTypes; 14.52 + 14.53 +import BRegFile; 14.54 + 14.55 +import BranchPred; 14.56 + 14.57 +import DataCacheBlocking; 14.58 + 14.59 +import InstCacheBlocking; 14.60 + 14.61 +import Processor; 14.62 + 14.63 +interface (Core.CoreStats :: *) = { 14.64 + Core.dcache :: DataCacheBlocking.DCacheStats; 14.65 + Core.icache :: InstCacheBlocking.ICacheStats; 14.66 + Core.proc :: Processor.ProcStats 14.67 +}; 14.68 + 14.69 +instance Core ¶Prelude®¶.¶PrimMakeUndefined®¶ Core.CoreStats; 14.70 + 14.71 +instance Core ¶Prelude®¶.¶PrimDeepSeqCond®¶ Core.CoreStats; 14.72 + 14.73 +instance Core ¶Prelude®¶.¶PrimMakeUninitialized®¶ Core.CoreStats; 14.74 + 14.75 +interface (Core.Core :: *) = { 14.76 + Core.mmem_client :: ¶ClientServer®¶.¶Client®¶ MemTypes.MainMemReq MemTypes.MainMemResp; 14.77 + Core.stats :: Core.CoreStats; 14.78 + Core.tohost :: Processor.CPUToHost 14.79 +}; 14.80 + 14.81 +instance Core ¶Prelude®¶.¶PrimMakeUndefined®¶ Core.Core; 14.82 + 14.83 +instance Core ¶Prelude®¶.¶PrimDeepSeqCond®¶ Core.Core; 14.84 + 14.85 +instance Core ¶Prelude®¶.¶PrimMakeUninitialized®¶ Core.Core; 14.86 + 14.87 +Core.mkCore :: (¶Prelude®¶.¶IsModule®¶ _m__ _c__) => _m__ Core.Core 14.88 +}
15.1 Binary file core/sim/bdir_dut/Core.bo has changed
16.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 16.2 +++ b/core/sim/bdir_dut/DataCacheBlocking.bi Tue Apr 13 17:34:33 2010 -0400 16.3 @@ -0,0 +1,106 @@ 16.4 +signature DataCacheBlocking where { 16.5 +import ¶Assert®¶; 16.6 + 16.7 +import ¶Counter®¶; 16.8 + 16.9 +import ¶FIFOF_®¶; 16.10 + 16.11 +import ¶FIFOF®¶; 16.12 + 16.13 +import ¶FIFO®¶; 16.14 + 16.15 +import ¶Inout®¶; 16.16 + 16.17 +import ¶List®¶; 16.18 + 16.19 +import BFIFO; 16.20 + 16.21 +import ¶Clocks®¶; 16.22 + 16.23 +import ¶ListN®¶; 16.24 + 16.25 +import ¶PrimArray®¶; 16.26 + 16.27 +import ¶RegFile®¶; 16.28 + 16.29 +import ¶Vector®¶; 16.30 + 16.31 +import ¶Connectable®¶; 16.32 + 16.33 +import ¶GetPut®¶; 16.34 + 16.35 +import ¶ClientServer®¶; 16.36 + 16.37 +import Trace; 16.38 + 16.39 +import MemTypes; 16.40 + 16.41 +import ProcTypes; 16.42 + 16.43 +interface (DataCacheBlocking.DCacheStats :: *) = { 16.44 + DataCacheBlocking.num_accesses :: ¶GetPut®¶.¶Get®¶ ProcTypes.Stat; 16.45 + DataCacheBlocking.num_misses :: ¶GetPut®¶.¶Get®¶ ProcTypes.Stat; 16.46 + DataCacheBlocking.num_writebacks :: ¶GetPut®¶.¶Get®¶ ProcTypes.Stat 16.47 +}; 16.48 + 16.49 +instance DataCacheBlocking ¶Prelude®¶.¶PrimMakeUndefined®¶ DataCacheBlocking.DCacheStats; 16.50 + 16.51 +instance DataCacheBlocking ¶Prelude®¶.¶PrimDeepSeqCond®¶ DataCacheBlocking.DCacheStats; 16.52 + 16.53 +instance DataCacheBlocking ¶Prelude®¶.¶PrimMakeUninitialized®¶ DataCacheBlocking.DCacheStats; 16.54 + 16.55 +interface (DataCacheBlocking.DCache :: * -> * -> *) req_t resp_t = { 16.56 + DataCacheBlocking.proc_server :: ¶ClientServer®¶.¶Server®¶ req_t resp_t; 16.57 + DataCacheBlocking.mmem_client :: ¶ClientServer®¶.¶Client®¶ MemTypes.MainMemReq MemTypes.MainMemResp; 16.58 + DataCacheBlocking.statsEn_put :: ¶GetPut®¶.¶Put®¶ ¶Prelude®¶.¶Bool®¶; 16.59 + DataCacheBlocking.stats :: DataCacheBlocking.DCacheStats 16.60 +}; 16.61 + 16.62 +instance DataCacheBlocking (¶Prelude®¶.¶PrimMakeUndefined®¶ resp_t) => 16.63 + ¶Prelude®¶.¶PrimMakeUndefined®¶ (DataCacheBlocking.DCache req_t resp_t); 16.64 + 16.65 +instance DataCacheBlocking (¶Prelude®¶.¶PrimDeepSeqCond®¶ resp_t) => 16.66 + ¶Prelude®¶.¶PrimDeepSeqCond®¶ (DataCacheBlocking.DCache req_t resp_t); 16.67 + 16.68 +instance DataCacheBlocking ¶Prelude®¶.¶PrimMakeUninitialized®¶ 16.69 + (DataCacheBlocking.DCache req_t resp_t); 16.70 + 16.71 +type (DataCacheBlocking.CacheLineIndexSz :: #) = 10; 16.72 + 16.73 +type (DataCacheBlocking.CacheLineTagSz :: #) = 20; 16.74 + 16.75 +type (DataCacheBlocking.CacheLineSz :: #) = 32; 16.76 + 16.77 +type (DataCacheBlocking.CacheLineIndex :: *) = ¶Prelude®¶.¶Bit®¶ DataCacheBlocking.CacheLineIndexSz; 16.78 + 16.79 +type (DataCacheBlocking.CacheLineTag :: *) = ¶Prelude®¶.¶Bit®¶ DataCacheBlocking.CacheLineTagSz; 16.80 + 16.81 +type (DataCacheBlocking.CacheLine :: *) = ¶Prelude®¶.¶Bit®¶ DataCacheBlocking.CacheLineSz; 16.82 + 16.83 +data (DataCacheBlocking.CacheStage :: *) = 16.84 + DataCacheBlocking.Init () | 16.85 + DataCacheBlocking.Access () | 16.86 + DataCacheBlocking.RefillReq () | 16.87 + DataCacheBlocking.RefillResp (); 16.88 + 16.89 +instance DataCacheBlocking ¶Prelude®¶.¶PrimMakeUndefined®¶ DataCacheBlocking.CacheStage; 16.90 + 16.91 +instance DataCacheBlocking ¶Prelude®¶.¶PrimDeepSeqCond®¶ DataCacheBlocking.CacheStage; 16.92 + 16.93 +instance DataCacheBlocking ¶Prelude®¶.¶PrimMakeUninitialized®¶ DataCacheBlocking.CacheStage; 16.94 + 16.95 +instance DataCacheBlocking ¶Prelude®¶.¶Eq®¶ DataCacheBlocking.CacheStage; 16.96 + 16.97 +instance DataCacheBlocking ¶Prelude®¶.¶Bits®¶ DataCacheBlocking.CacheStage 2; 16.98 + 16.99 +DataCacheBlocking.getAddr :: MemTypes.DataReq -> ¶Prelude®¶.¶Bit®¶ MemTypes.AddrSz; 16.100 + 16.101 +DataCacheBlocking.getCacheLineIndex :: MemTypes.DataReq -> DataCacheBlocking.CacheLineIndex; 16.102 + 16.103 +DataCacheBlocking.getCacheLineTag :: MemTypes.DataReq -> DataCacheBlocking.CacheLineTag; 16.104 + 16.105 +DataCacheBlocking.getCacheLineAddr :: MemTypes.DataReq -> ¶Prelude®¶.¶Bit®¶ MemTypes.AddrSz; 16.106 + 16.107 +DataCacheBlocking.mkDataCache :: (¶Prelude®¶.¶IsModule®¶ _m__ _c__) => 16.108 + _m__ (DataCacheBlocking.DCache MemTypes.DataReq MemTypes.DataResp) 16.109 +}
17.1 Binary file core/sim/bdir_dut/DataCacheBlocking.bo has changed
18.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 18.2 +++ b/core/sim/bdir_dut/InstCacheBlocking.bi Tue Apr 13 17:34:33 2010 -0400 18.3 @@ -0,0 +1,109 @@ 18.4 +signature InstCacheBlocking where { 18.5 +import ¶Assert®¶; 18.6 + 18.7 +import ¶Counter®¶; 18.8 + 18.9 +import ¶FIFOF_®¶; 18.10 + 18.11 +import ¶FIFOF®¶; 18.12 + 18.13 +import ¶FIFO®¶; 18.14 + 18.15 +import ¶Inout®¶; 18.16 + 18.17 +import ¶List®¶; 18.18 + 18.19 +import BFIFO; 18.20 + 18.21 +import ¶Clocks®¶; 18.22 + 18.23 +import ¶ListN®¶; 18.24 + 18.25 +import ¶PrimArray®¶; 18.26 + 18.27 +import ¶RWire®¶; 18.28 + 18.29 +import ¶RegFile®¶; 18.30 + 18.31 +import ¶Vector®¶; 18.32 + 18.33 +import ¶Connectable®¶; 18.34 + 18.35 +import ¶GetPut®¶; 18.36 + 18.37 +import ¶ClientServer®¶; 18.38 + 18.39 +import Trace; 18.40 + 18.41 +import MemTypes; 18.42 + 18.43 +import ProcTypes; 18.44 + 18.45 +interface (InstCacheBlocking.ICacheStats :: *) = { 18.46 + InstCacheBlocking.num_accesses :: ¶GetPut®¶.¶Get®¶ ProcTypes.Stat; 18.47 + InstCacheBlocking.num_misses :: ¶GetPut®¶.¶Get®¶ ProcTypes.Stat; 18.48 + InstCacheBlocking.num_evictions :: ¶GetPut®¶.¶Get®¶ ProcTypes.Stat 18.49 +}; 18.50 + 18.51 +instance InstCacheBlocking ¶Prelude®¶.¶PrimMakeUndefined®¶ InstCacheBlocking.ICacheStats; 18.52 + 18.53 +instance InstCacheBlocking ¶Prelude®¶.¶PrimDeepSeqCond®¶ InstCacheBlocking.ICacheStats; 18.54 + 18.55 +instance InstCacheBlocking ¶Prelude®¶.¶PrimMakeUninitialized®¶ InstCacheBlocking.ICacheStats; 18.56 + 18.57 +interface (InstCacheBlocking.ICache :: * -> * -> *) req_t resp_t = { 18.58 + InstCacheBlocking.proc_server :: ¶ClientServer®¶.¶Server®¶ req_t resp_t; 18.59 + InstCacheBlocking.mmem_client :: ¶ClientServer®¶.¶Client®¶ MemTypes.MainMemReq MemTypes.MainMemResp; 18.60 + InstCacheBlocking.statsEn_put :: ¶GetPut®¶.¶Put®¶ ¶Prelude®¶.¶Bool®¶; 18.61 + InstCacheBlocking.stats :: InstCacheBlocking.ICacheStats 18.62 +}; 18.63 + 18.64 +instance InstCacheBlocking (¶Prelude®¶.¶PrimMakeUndefined®¶ resp_t) => 18.65 + ¶Prelude®¶.¶PrimMakeUndefined®¶ (InstCacheBlocking.ICache req_t resp_t); 18.66 + 18.67 +instance InstCacheBlocking (¶Prelude®¶.¶PrimDeepSeqCond®¶ resp_t) => 18.68 + ¶Prelude®¶.¶PrimDeepSeqCond®¶ (InstCacheBlocking.ICache req_t resp_t); 18.69 + 18.70 +instance InstCacheBlocking ¶Prelude®¶.¶PrimMakeUninitialized®¶ 18.71 + (InstCacheBlocking.ICache req_t resp_t); 18.72 + 18.73 +type (InstCacheBlocking.CacheLineIndexSz :: #) = 10; 18.74 + 18.75 +type (InstCacheBlocking.CacheLineTagSz :: #) = 20; 18.76 + 18.77 +type (InstCacheBlocking.CacheLineSz :: #) = 32; 18.78 + 18.79 +type (InstCacheBlocking.CacheLineIndex :: *) = ¶Prelude®¶.¶Bit®¶ InstCacheBlocking.CacheLineIndexSz; 18.80 + 18.81 +type (InstCacheBlocking.CacheLineTag :: *) = ¶Prelude®¶.¶Bit®¶ InstCacheBlocking.CacheLineTagSz; 18.82 + 18.83 +type (InstCacheBlocking.CacheLine :: *) = ¶Prelude®¶.¶Bit®¶ InstCacheBlocking.CacheLineSz; 18.84 + 18.85 +data (InstCacheBlocking.CacheStage :: *) = 18.86 + InstCacheBlocking.Init () | 18.87 + InstCacheBlocking.Access () | 18.88 + InstCacheBlocking.Evict () | 18.89 + InstCacheBlocking.RefillReq () | 18.90 + InstCacheBlocking.RefillResp (); 18.91 + 18.92 +instance InstCacheBlocking ¶Prelude®¶.¶PrimMakeUndefined®¶ InstCacheBlocking.CacheStage; 18.93 + 18.94 +instance InstCacheBlocking ¶Prelude®¶.¶PrimDeepSeqCond®¶ InstCacheBlocking.CacheStage; 18.95 + 18.96 +instance InstCacheBlocking ¶Prelude®¶.¶PrimMakeUninitialized®¶ InstCacheBlocking.CacheStage; 18.97 + 18.98 +instance InstCacheBlocking ¶Prelude®¶.¶Eq®¶ InstCacheBlocking.CacheStage; 18.99 + 18.100 +instance InstCacheBlocking ¶Prelude®¶.¶Bits®¶ InstCacheBlocking.CacheStage 3; 18.101 + 18.102 +InstCacheBlocking.getAddr :: MemTypes.InstReq -> ¶Prelude®¶.¶Bit®¶ MemTypes.AddrSz; 18.103 + 18.104 +InstCacheBlocking.getCacheLineIndex :: MemTypes.InstReq -> InstCacheBlocking.CacheLineIndex; 18.105 + 18.106 +InstCacheBlocking.getCacheLineTag :: MemTypes.InstReq -> InstCacheBlocking.CacheLineTag; 18.107 + 18.108 +InstCacheBlocking.getCacheLineAddr :: MemTypes.InstReq -> ¶Prelude®¶.¶Bit®¶ MemTypes.AddrSz; 18.109 + 18.110 +InstCacheBlocking.mkInstCache :: (¶Prelude®¶.¶IsModule®¶ _m__ _c__) => 18.111 + _m__ (InstCacheBlocking.ICache MemTypes.InstReq MemTypes.InstResp) 18.112 +}
19.1 Binary file core/sim/bdir_dut/InstCacheBlocking.bo has changed
20.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 20.2 +++ b/core/sim/bdir_dut/MemArb.bi Tue Apr 13 17:34:33 2010 -0400 20.3 @@ -0,0 +1,61 @@ 20.4 +signature MemArb where { 20.5 +import ¶Assert®¶; 20.6 + 20.7 +import ¶Counter®¶; 20.8 + 20.9 +import ¶FIFOF_®¶; 20.10 + 20.11 +import ¶FIFOF®¶; 20.12 + 20.13 +import ¶FIFO®¶; 20.14 + 20.15 +import ¶Inout®¶; 20.16 + 20.17 +import ¶List®¶; 20.18 + 20.19 +import BFIFO; 20.20 + 20.21 +import ¶Clocks®¶; 20.22 + 20.23 +import ¶ListN®¶; 20.24 + 20.25 +import ¶PrimArray®¶; 20.26 + 20.27 +import ¶Vector®¶; 20.28 + 20.29 +import ¶Connectable®¶; 20.30 + 20.31 +import ¶GetPut®¶; 20.32 + 20.33 +import ¶ClientServer®¶; 20.34 + 20.35 +import Trace; 20.36 + 20.37 +import MemTypes; 20.38 + 20.39 +interface (MemArb.MemArb :: *) = { 20.40 + MemArb.cache0_server :: ¶ClientServer®¶.¶Server®¶ MemTypes.MainMemReq MemTypes.MainMemResp; 20.41 + MemArb.cache1_server :: ¶ClientServer®¶.¶Server®¶ MemTypes.MainMemReq MemTypes.MainMemResp; 20.42 + MemArb.mmem_client :: ¶ClientServer®¶.¶Client®¶ MemTypes.MainMemReq MemTypes.MainMemResp 20.43 +}; 20.44 + 20.45 +instance MemArb ¶Prelude®¶.¶PrimMakeUndefined®¶ MemArb.MemArb; 20.46 + 20.47 +instance MemArb ¶Prelude®¶.¶PrimDeepSeqCond®¶ MemArb.MemArb; 20.48 + 20.49 +instance MemArb ¶Prelude®¶.¶PrimMakeUninitialized®¶ MemArb.MemArb; 20.50 + 20.51 +data (MemArb.ReqPtr :: *) = MemArb.REQ0 () | MemArb.REQ1 (); 20.52 + 20.53 +instance MemArb ¶Prelude®¶.¶PrimMakeUndefined®¶ MemArb.ReqPtr; 20.54 + 20.55 +instance MemArb ¶Prelude®¶.¶PrimDeepSeqCond®¶ MemArb.ReqPtr; 20.56 + 20.57 +instance MemArb ¶Prelude®¶.¶PrimMakeUninitialized®¶ MemArb.ReqPtr; 20.58 + 20.59 +instance MemArb ¶Prelude®¶.¶Eq®¶ MemArb.ReqPtr; 20.60 + 20.61 +instance MemArb ¶Prelude®¶.¶Bits®¶ MemArb.ReqPtr 1; 20.62 + 20.63 +MemArb.mkMemArb :: (¶Prelude®¶.¶IsModule®¶ _m__ _c__) => _m__ MemArb.MemArb 20.64 +}
21.1 Binary file core/sim/bdir_dut/MemArb.bo has changed
22.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 22.2 +++ b/core/sim/bdir_dut/MemTypes.bi Tue Apr 13 17:34:33 2010 -0400 22.3 @@ -0,0 +1,171 @@ 22.4 +signature MemTypes where { 22.5 +import ¶Counter®¶; 22.6 + 22.7 +import ¶FIFOF_®¶; 22.8 + 22.9 +import ¶FIFOF®¶; 22.10 + 22.11 +import ¶FIFO®¶; 22.12 + 22.13 +import ¶Inout®¶; 22.14 + 22.15 +import ¶List®¶; 22.16 + 22.17 +import ¶Clocks®¶; 22.18 + 22.19 +import ¶ListN®¶; 22.20 + 22.21 +import ¶PrimArray®¶; 22.22 + 22.23 +import ¶Vector®¶; 22.24 + 22.25 +import ¶Connectable®¶; 22.26 + 22.27 +import ¶GetPut®¶; 22.28 + 22.29 +import ¶ClientServer®¶; 22.30 + 22.31 +import Trace; 22.32 + 22.33 +data (MemTypes.MemReq :: # -> # -> # -> *) addrSz tagSz dataSz = 22.34 + MemTypes.LoadReq (MemTypes.¶MemReq_$LoadReq¶ addrSz tagSz dataSz) | 22.35 + MemTypes.StoreReq (MemTypes.¶MemReq_$StoreReq¶ addrSz tagSz dataSz); 22.36 + 22.37 +instance MemTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ (MemTypes.MemReq addrSz tagSz dataSz); 22.38 + 22.39 +instance MemTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ (MemTypes.MemReq addrSz tagSz dataSz); 22.40 + 22.41 +instance MemTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ (MemTypes.MemReq addrSz tagSz dataSz); 22.42 + 22.43 +instance MemTypes ¶Prelude®¶.¶Eq®¶ (MemTypes.MemReq addrSz tagSz dataSz); 22.44 + 22.45 +instance MemTypes (¶Prelude®¶.¶Add®¶ 1 _v103 _v100, 22.46 + ¶Prelude®¶.¶Max®¶ _v101 _v104 _v103, 22.47 + ¶Prelude®¶.¶Add®¶ _v105 _v104 _v103, 22.48 + ¶Prelude®¶.¶Add®¶ _v102 _v101 _v103, 22.49 + ¶Prelude®¶.¶Add®¶ addrSz _v106 _v104, 22.50 + ¶Prelude®¶.¶Add®¶ tagSz dataSz _v106, 22.51 + ¶Prelude®¶.¶Add®¶ addrSz tagSz _v101) => 22.52 + ¶Prelude®¶.¶Bits®¶ (MemTypes.MemReq addrSz tagSz dataSz) _v100; 22.53 + 22.54 +struct (MemTypes.¶MemReq_$LoadReq¶ :: # -> # -> # -> *) addrSz tagSz dataSz = { 22.55 + MemTypes.addr :: ¶Prelude®¶.¶Bit®¶ addrSz; 22.56 + MemTypes.tag :: ¶Prelude®¶.¶Bit®¶ tagSz 22.57 +}; 22.58 + 22.59 +instance MemTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ (MemTypes.¶MemReq_$LoadReq¶ addrSz tagSz dataSz); 22.60 + 22.61 +instance MemTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ (MemTypes.¶MemReq_$LoadReq¶ addrSz tagSz dataSz); 22.62 + 22.63 +instance MemTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ 22.64 + (MemTypes.¶MemReq_$LoadReq¶ addrSz tagSz dataSz); 22.65 + 22.66 +instance MemTypes ¶Prelude®¶.¶Eq®¶ (MemTypes.¶MemReq_$LoadReq¶ addrSz tagSz dataSz); 22.67 + 22.68 +instance MemTypes (¶Prelude®¶.¶Add®¶ _v101 _v104 _v100) => 22.69 + ¶Prelude®¶.¶Bits®¶ (MemTypes.¶MemReq_$LoadReq¶ _v101 _v104 dataSz) _v100; 22.70 + 22.71 +struct (MemTypes.¶MemReq_$StoreReq¶ :: # -> # -> # -> *) addrSz tagSz dataSz = { 22.72 + MemTypes.addr :: ¶Prelude®¶.¶Bit®¶ addrSz; 22.73 + MemTypes.tag :: ¶Prelude®¶.¶Bit®¶ tagSz; 22.74 + MemTypes.¡data¡ :: ¶Prelude®¶.¶Bit®¶ dataSz 22.75 +}; 22.76 + 22.77 +instance MemTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ (MemTypes.¶MemReq_$StoreReq¶ addrSz tagSz dataSz); 22.78 + 22.79 +instance MemTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ (MemTypes.¶MemReq_$StoreReq¶ addrSz tagSz dataSz); 22.80 + 22.81 +instance MemTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ 22.82 + (MemTypes.¶MemReq_$StoreReq¶ addrSz tagSz dataSz); 22.83 + 22.84 +instance MemTypes ¶Prelude®¶.¶Eq®¶ (MemTypes.¶MemReq_$StoreReq¶ addrSz tagSz dataSz); 22.85 + 22.86 +instance MemTypes (¶Prelude®¶.¶Add®¶ _v101 _v100 _v103, ¶Prelude®¶.¶Add®¶ _v104 _v107 _v100) => 22.87 + ¶Prelude®¶.¶Bits®¶ (MemTypes.¶MemReq_$StoreReq¶ _v101 _v104 _v107) _v103; 22.88 + 22.89 +data (MemTypes.MemResp :: # -> # -> *) tagSz dataSz = 22.90 + MemTypes.LoadResp (MemTypes.¶MemResp_$LoadResp¶ tagSz dataSz) | 22.91 + MemTypes.StoreResp (MemTypes.¶MemResp_$StoreResp¶ tagSz dataSz); 22.92 + 22.93 +instance MemTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ (MemTypes.MemResp tagSz dataSz); 22.94 + 22.95 +instance MemTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ (MemTypes.MemResp tagSz dataSz); 22.96 + 22.97 +instance MemTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ (MemTypes.MemResp tagSz dataSz); 22.98 + 22.99 +instance MemTypes ¶Prelude®¶.¶Eq®¶ (MemTypes.MemResp tagSz dataSz); 22.100 + 22.101 +instance MemTypes (¶Prelude®¶.¶Add®¶ 1 _v103 _v100, 22.102 + ¶Prelude®¶.¶Max®¶ _v101 _v104 _v103, 22.103 + ¶Prelude®¶.¶Add®¶ _v105 _v104 _v103, 22.104 + ¶Prelude®¶.¶Add®¶ _v102 _v101 _v103, 22.105 + ¶Prelude®¶.¶Add®¶ _v104 dataSz _v101) => 22.106 + ¶Prelude®¶.¶Bits®¶ (MemTypes.MemResp _v104 dataSz) _v100; 22.107 + 22.108 +struct (MemTypes.¶MemResp_$LoadResp¶ :: # -> # -> *) tagSz dataSz = { 22.109 + MemTypes.tag :: ¶Prelude®¶.¶Bit®¶ tagSz; 22.110 + MemTypes.¡data¡ :: ¶Prelude®¶.¶Bit®¶ dataSz 22.111 +}; 22.112 + 22.113 +instance MemTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ (MemTypes.¶MemResp_$LoadResp¶ tagSz dataSz); 22.114 + 22.115 +instance MemTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ (MemTypes.¶MemResp_$LoadResp¶ tagSz dataSz); 22.116 + 22.117 +instance MemTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ (MemTypes.¶MemResp_$LoadResp¶ tagSz dataSz); 22.118 + 22.119 +instance MemTypes ¶Prelude®¶.¶Eq®¶ (MemTypes.¶MemResp_$LoadResp¶ tagSz dataSz); 22.120 + 22.121 +instance MemTypes (¶Prelude®¶.¶Add®¶ _v101 _v104 _v100) => 22.122 + ¶Prelude®¶.¶Bits®¶ (MemTypes.¶MemResp_$LoadResp¶ _v101 _v104) _v100; 22.123 + 22.124 +struct (MemTypes.¶MemResp_$StoreResp¶ :: # -> # -> *) tagSz dataSz = { 22.125 + MemTypes.tag :: ¶Prelude®¶.¶Bit®¶ tagSz 22.126 +}; 22.127 + 22.128 +instance MemTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ (MemTypes.¶MemResp_$StoreResp¶ tagSz dataSz); 22.129 + 22.130 +instance MemTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ (MemTypes.¶MemResp_$StoreResp¶ tagSz dataSz); 22.131 + 22.132 +instance MemTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ (MemTypes.¶MemResp_$StoreResp¶ tagSz dataSz); 22.133 + 22.134 +instance MemTypes ¶Prelude®¶.¶Eq®¶ (MemTypes.¶MemResp_$StoreResp¶ tagSz dataSz); 22.135 + 22.136 +instance MemTypes ¶Prelude®¶.¶Bits®¶ (MemTypes.¶MemResp_$StoreResp¶ _v101 dataSz) _v101; 22.137 + 22.138 +type (MemTypes.AddrSz :: #) = 32; 22.139 + 22.140 +type (MemTypes.TagSz :: #) = 8; 22.141 + 22.142 +type (MemTypes.DataSz :: #) = 32; 22.143 + 22.144 +type (MemTypes.InstSz :: #) = 32; 22.145 + 22.146 +type (MemTypes.HostDataSz :: #) = 32; 22.147 + 22.148 +type (MemTypes.InstReq :: *) = MemTypes.MemReq MemTypes.AddrSz MemTypes.TagSz 0; 22.149 + 22.150 +type (MemTypes.InstResp :: *) = MemTypes.MemResp MemTypes.TagSz MemTypes.InstSz; 22.151 + 22.152 +type (MemTypes.DataReq :: *) = MemTypes.MemReq MemTypes.AddrSz MemTypes.TagSz MemTypes.DataSz; 22.153 + 22.154 +type (MemTypes.DataResp :: *) = MemTypes.MemResp MemTypes.TagSz MemTypes.DataSz; 22.155 + 22.156 +type (MemTypes.HostReq :: *) = MemTypes.MemReq MemTypes.AddrSz MemTypes.TagSz MemTypes.HostDataSz; 22.157 + 22.158 +type (MemTypes.HostResp :: *) = MemTypes.MemResp MemTypes.TagSz MemTypes.HostDataSz; 22.159 + 22.160 +type (MemTypes.MainMemAddrSz :: #) = 32; 22.161 + 22.162 +type (MemTypes.MainMemTagSz :: #) = 8; 22.163 + 22.164 +type (MemTypes.MainMemDataSz :: #) = 32; 22.165 + 22.166 +type (MemTypes.MainMemReq :: *) = 22.167 + MemTypes.MemReq MemTypes.MainMemAddrSz MemTypes.MainMemTagSz MemTypes.MainMemDataSz; 22.168 + 22.169 +type (MemTypes.MainMemResp :: *) = MemTypes.MemResp MemTypes.MainMemTagSz MemTypes.MainMemDataSz; 22.170 + 22.171 +instance MemTypes Trace.Traceable (MemTypes.MemReq a b c); 22.172 + 22.173 +instance MemTypes Trace.Traceable (MemTypes.MemResp a b) 22.174 +}
23.1 Binary file core/sim/bdir_dut/MemTypes.bo has changed
24.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 24.2 +++ b/core/sim/bdir_dut/ProcTypes.bi Tue Apr 13 17:34:33 2010 -0400 24.3 @@ -0,0 +1,725 @@ 24.4 +signature ProcTypes where { 24.5 +import ¶Counter®¶; 24.6 + 24.7 +import ¶FIFOF_®¶; 24.8 + 24.9 +import ¶FIFOF®¶; 24.10 + 24.11 +import ¶FIFO®¶; 24.12 + 24.13 +import ¶Inout®¶; 24.14 + 24.15 +import ¶List®¶; 24.16 + 24.17 +import ¶Clocks®¶; 24.18 + 24.19 +import ¶ListN®¶; 24.20 + 24.21 +import ¶PrimArray®¶; 24.22 + 24.23 +import ¶Vector®¶; 24.24 + 24.25 +import ¶Connectable®¶; 24.26 + 24.27 +import ¶GetPut®¶; 24.28 + 24.29 +import ¶ClientServer®¶; 24.30 + 24.31 +import Trace; 24.32 + 24.33 +type (ProcTypes.Addr :: *) = ¶Prelude®¶.¶Bit®¶ 32; 24.34 + 24.35 +type (ProcTypes.Stat :: *) = ¶Prelude®¶.¶Int®¶ 18; 24.36 + 24.37 +type (ProcTypes.Rindx :: *) = ¶Prelude®¶.¶Bit®¶ 5; 24.38 + 24.39 +type (ProcTypes.Simm :: *) = ¶Prelude®¶.¶Bit®¶ 16; 24.40 + 24.41 +type (ProcTypes.Zimm :: *) = ¶Prelude®¶.¶Bit®¶ 16; 24.42 + 24.43 +type (ProcTypes.Epoch :: *) = ¶Prelude®¶.¶Bit®¶ 8; 24.44 + 24.45 +type (ProcTypes.Shamt :: *) = ¶Prelude®¶.¶Bit®¶ 5; 24.46 + 24.47 +type (ProcTypes.Target :: *) = ¶Prelude®¶.¶Bit®¶ 26; 24.48 + 24.49 +type (ProcTypes.CP0indx :: *) = ¶Prelude®¶.¶Bit®¶ 5; 24.50 + 24.51 +type (ProcTypes.Data :: *) = ¶Prelude®¶.¶Bit®¶ 32; 24.52 + 24.53 +data (ProcTypes.Direction :: *) = ProcTypes.Taken () | ProcTypes.NotTaken (); 24.54 + 24.55 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.Direction; 24.56 + 24.57 +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.Direction; 24.58 + 24.59 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.Direction; 24.60 + 24.61 +instance ProcTypes ¶Prelude®¶.¶Bits®¶ ProcTypes.Direction 1; 24.62 + 24.63 +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.Direction; 24.64 + 24.65 +data (ProcTypes.WritebackType :: *) = 24.66 + ProcTypes.ALUWB (¶Prelude®¶.¶Tuple2®¶ ProcTypes.Rindx ProcTypes.Data) | 24.67 + ProcTypes.MemWB ProcTypes.Rindx | 24.68 + ProcTypes.CoWB (¶Prelude®¶.¶Tuple2®¶ ProcTypes.Rindx ProcTypes.Data); 24.69 + 24.70 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.WritebackType; 24.71 + 24.72 +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.WritebackType; 24.73 + 24.74 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.WritebackType; 24.75 + 24.76 +instance ProcTypes ¶Prelude®¶.¶Bits®¶ ProcTypes.WritebackType 39; 24.77 + 24.78 +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.WritebackType; 24.79 + 24.80 +data (ProcTypes.WBResult :: *) = 24.81 + ProcTypes.WB_ALU ProcTypes.¶WBResult_$WB_ALU¶ | 24.82 + ProcTypes.WB_Host (¶Prelude®¶.¶Bit®¶ 32) | 24.83 + ProcTypes.WB_Load ProcTypes.Rindx | 24.84 + ProcTypes.WB_Store (); 24.85 + 24.86 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.WBResult; 24.87 + 24.88 +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.WBResult; 24.89 + 24.90 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.WBResult; 24.91 + 24.92 +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.WBResult; 24.93 + 24.94 +instance ProcTypes ¶Prelude®¶.¶Bits®¶ ProcTypes.WBResult 39; 24.95 + 24.96 +struct (ProcTypes.¶WBResult_$WB_ALU¶ :: *) = { 24.97 + ProcTypes.¡data¡ :: ¶Prelude®¶.¶Bit®¶ 32; 24.98 + ProcTypes.dest :: ProcTypes.Rindx 24.99 +}; 24.100 + 24.101 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶WBResult_$WB_ALU¶; 24.102 + 24.103 +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶WBResult_$WB_ALU¶; 24.104 + 24.105 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶WBResult_$WB_ALU¶; 24.106 + 24.107 +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶WBResult_$WB_ALU¶; 24.108 + 24.109 +instance ProcTypes ¶Prelude®¶.¶Bits®¶ ProcTypes.¶WBResult_$WB_ALU¶ 37; 24.110 + 24.111 +struct (ProcTypes.PCStat :: *) = { 24.112 + ProcTypes.qpc :: ProcTypes.Addr; 24.113 + ProcTypes.qnxtpc :: ProcTypes.Addr; 24.114 + ProcTypes.qepoch :: ProcTypes.Epoch 24.115 +}; 24.116 + 24.117 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.PCStat; 24.118 + 24.119 +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.PCStat; 24.120 + 24.121 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.PCStat; 24.122 + 24.123 +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.PCStat; 24.124 + 24.125 +instance ProcTypes ¶Prelude®¶.¶Bits®¶ ProcTypes.PCStat 72; 24.126 + 24.127 +data (ProcTypes.Instr :: *) = 24.128 + ProcTypes.LW ProcTypes.¶Instr_$LW¶ | 24.129 + ProcTypes.SW ProcTypes.¶Instr_$SW¶ | 24.130 + ProcTypes.ADDIU ProcTypes.¶Instr_$ADDIU¶ | 24.131 + ProcTypes.SLTI ProcTypes.¶Instr_$SLTI¶ | 24.132 + ProcTypes.SLTIU ProcTypes.¶Instr_$SLTIU¶ | 24.133 + ProcTypes.ANDI ProcTypes.¶Instr_$ANDI¶ | 24.134 + ProcTypes.ORI ProcTypes.¶Instr_$ORI¶ | 24.135 + ProcTypes.XORI ProcTypes.¶Instr_$XORI¶ | 24.136 + ProcTypes.LUI ProcTypes.¶Instr_$LUI¶ | 24.137 + ProcTypes.SLL ProcTypes.¶Instr_$SLL¶ | 24.138 + ProcTypes.SRL ProcTypes.¶Instr_$SRL¶ | 24.139 + ProcTypes.SRA ProcTypes.¶Instr_$SRA¶ | 24.140 + ProcTypes.SLLV ProcTypes.¶Instr_$SLLV¶ | 24.141 + ProcTypes.SRLV ProcTypes.¶Instr_$SRLV¶ | 24.142 + ProcTypes.SRAV ProcTypes.¶Instr_$SRAV¶ | 24.143 + ProcTypes.ADDU ProcTypes.¶Instr_$ADDU¶ | 24.144 + ProcTypes.SUBU ProcTypes.¶Instr_$SUBU¶ | 24.145 + ProcTypes.AND ProcTypes.¶Instr_$AND¶ | 24.146 + ProcTypes.OR ProcTypes.¶Instr_$OR¶ | 24.147 + ProcTypes.XOR ProcTypes.¶Instr_$XOR¶ | 24.148 + ProcTypes.NOR ProcTypes.¶Instr_$NOR¶ | 24.149 + ProcTypes.SLT ProcTypes.¶Instr_$SLT¶ | 24.150 + ProcTypes.SLTU ProcTypes.¶Instr_$SLTU¶ | 24.151 + ProcTypes.J ProcTypes.¶Instr_$J¶ | 24.152 + ProcTypes.JAL ProcTypes.¶Instr_$JAL¶ | 24.153 + ProcTypes.JR ProcTypes.¶Instr_$JR¶ | 24.154 + ProcTypes.JALR ProcTypes.¶Instr_$JALR¶ | 24.155 + ProcTypes.BEQ ProcTypes.¶Instr_$BEQ¶ | 24.156 + ProcTypes.BNE ProcTypes.¶Instr_$BNE¶ | 24.157 + ProcTypes.BLEZ ProcTypes.¶Instr_$BLEZ¶ | 24.158 + ProcTypes.BGTZ ProcTypes.¶Instr_$BGTZ¶ | 24.159 + ProcTypes.BLTZ ProcTypes.¶Instr_$BLTZ¶ | 24.160 + ProcTypes.BGEZ ProcTypes.¶Instr_$BGEZ¶ | 24.161 + ProcTypes.MFC0 ProcTypes.¶Instr_$MFC0¶ | 24.162 + ProcTypes.MTC0 ProcTypes.¶Instr_$MTC0¶ | 24.163 + ProcTypes.ILLEGAL (); 24.164 + 24.165 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.Instr; 24.166 + 24.167 +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.Instr; 24.168 + 24.169 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.Instr; 24.170 + 24.171 +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.Instr; 24.172 + 24.173 +struct (ProcTypes.¶Instr_$LW¶ :: *) = { 24.174 + ProcTypes.rbase :: ProcTypes.Rindx; 24.175 + ProcTypes.rdst :: ProcTypes.Rindx; 24.176 + ProcTypes.offset :: ProcTypes.Simm 24.177 +}; 24.178 + 24.179 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$LW¶; 24.180 + 24.181 +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$LW¶; 24.182 + 24.183 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$LW¶; 24.184 + 24.185 +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$LW¶; 24.186 + 24.187 +struct (ProcTypes.¶Instr_$SW¶ :: *) = { 24.188 + ProcTypes.rbase :: ProcTypes.Rindx; 24.189 + ProcTypes.rsrc :: ProcTypes.Rindx; 24.190 + ProcTypes.offset :: ProcTypes.Simm 24.191 +}; 24.192 + 24.193 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$SW¶; 24.194 + 24.195 +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$SW¶; 24.196 + 24.197 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$SW¶; 24.198 + 24.199 +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$SW¶; 24.200 + 24.201 +struct (ProcTypes.¶Instr_$ADDIU¶ :: *) = { 24.202 + ProcTypes.rsrc :: ProcTypes.Rindx; 24.203 + ProcTypes.rdst :: ProcTypes.Rindx; 24.204 + ProcTypes.imm :: ProcTypes.Simm 24.205 +}; 24.206 + 24.207 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$ADDIU¶; 24.208 + 24.209 +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$ADDIU¶; 24.210 + 24.211 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$ADDIU¶; 24.212 + 24.213 +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$ADDIU¶; 24.214 + 24.215 +struct (ProcTypes.¶Instr_$SLTI¶ :: *) = { 24.216 + ProcTypes.rsrc :: ProcTypes.Rindx; 24.217 + ProcTypes.rdst :: ProcTypes.Rindx; 24.218 + ProcTypes.imm :: ProcTypes.Simm 24.219 +}; 24.220 + 24.221 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$SLTI¶; 24.222 + 24.223 +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$SLTI¶; 24.224 + 24.225 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$SLTI¶; 24.226 + 24.227 +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$SLTI¶; 24.228 + 24.229 +struct (ProcTypes.¶Instr_$SLTIU¶ :: *) = { 24.230 + ProcTypes.rsrc :: ProcTypes.Rindx; 24.231 + ProcTypes.rdst :: ProcTypes.Rindx; 24.232 + ProcTypes.imm :: ProcTypes.Simm 24.233 +}; 24.234 + 24.235 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$SLTIU¶; 24.236 + 24.237 +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$SLTIU¶; 24.238 + 24.239 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$SLTIU¶; 24.240 + 24.241 +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$SLTIU¶; 24.242 + 24.243 +struct (ProcTypes.¶Instr_$ANDI¶ :: *) = { 24.244 + ProcTypes.rsrc :: ProcTypes.Rindx; 24.245 + ProcTypes.rdst :: ProcTypes.Rindx; 24.246 + ProcTypes.imm :: ProcTypes.Zimm 24.247 +}; 24.248 + 24.249 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$ANDI¶; 24.250 + 24.251 +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$ANDI¶; 24.252 + 24.253 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$ANDI¶; 24.254 + 24.255 +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$ANDI¶; 24.256 + 24.257 +struct (ProcTypes.¶Instr_$ORI¶ :: *) = { 24.258 + ProcTypes.rsrc :: ProcTypes.Rindx; 24.259 + ProcTypes.rdst :: ProcTypes.Rindx; 24.260 + ProcTypes.imm :: ProcTypes.Zimm 24.261 +}; 24.262 + 24.263 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$ORI¶; 24.264 + 24.265 +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$ORI¶; 24.266 + 24.267 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$ORI¶; 24.268 + 24.269 +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$ORI¶; 24.270 + 24.271 +struct (ProcTypes.¶Instr_$XORI¶ :: *) = { 24.272 + ProcTypes.rsrc :: ProcTypes.Rindx; 24.273 + ProcTypes.rdst :: ProcTypes.Rindx; 24.274 + ProcTypes.imm :: ProcTypes.Zimm 24.275 +}; 24.276 + 24.277 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$XORI¶; 24.278 + 24.279 +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$XORI¶; 24.280 + 24.281 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$XORI¶; 24.282 + 24.283 +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$XORI¶; 24.284 + 24.285 +struct (ProcTypes.¶Instr_$LUI¶ :: *) = { 24.286 + ProcTypes.rdst :: ProcTypes.Rindx; 24.287 + ProcTypes.imm :: ProcTypes.Zimm 24.288 +}; 24.289 + 24.290 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$LUI¶; 24.291 + 24.292 +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$LUI¶; 24.293 + 24.294 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$LUI¶; 24.295 + 24.296 +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$LUI¶; 24.297 + 24.298 +struct (ProcTypes.¶Instr_$SLL¶ :: *) = { 24.299 + ProcTypes.rsrc :: ProcTypes.Rindx; 24.300 + ProcTypes.rdst :: ProcTypes.Rindx; 24.301 + ProcTypes.shamt :: ProcTypes.Shamt 24.302 +}; 24.303 + 24.304 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$SLL¶; 24.305 + 24.306 +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$SLL¶; 24.307 + 24.308 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$SLL¶; 24.309 + 24.310 +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$SLL¶; 24.311 + 24.312 +struct (ProcTypes.¶Instr_$SRL¶ :: *) = { 24.313 + ProcTypes.rsrc :: ProcTypes.Rindx; 24.314 + ProcTypes.rdst :: ProcTypes.Rindx; 24.315 + ProcTypes.shamt :: ProcTypes.Shamt 24.316 +}; 24.317 + 24.318 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$SRL¶; 24.319 + 24.320 +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$SRL¶; 24.321 + 24.322 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$SRL¶; 24.323 + 24.324 +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$SRL¶; 24.325 + 24.326 +struct (ProcTypes.¶Instr_$SRA¶ :: *) = { 24.327 + ProcTypes.rsrc :: ProcTypes.Rindx; 24.328 + ProcTypes.rdst :: ProcTypes.Rindx; 24.329 + ProcTypes.shamt :: ProcTypes.Shamt 24.330 +}; 24.331 + 24.332 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$SRA¶; 24.333 + 24.334 +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$SRA¶; 24.335 + 24.336 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$SRA¶; 24.337 + 24.338 +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$SRA¶; 24.339 + 24.340 +struct (ProcTypes.¶Instr_$SLLV¶ :: *) = { 24.341 + ProcTypes.rsrc :: ProcTypes.Rindx; 24.342 + ProcTypes.rdst :: ProcTypes.Rindx; 24.343 + ProcTypes.rshamt :: ProcTypes.Rindx 24.344 +}; 24.345 + 24.346 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$SLLV¶; 24.347 + 24.348 +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$SLLV¶; 24.349 + 24.350 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$SLLV¶; 24.351 + 24.352 +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$SLLV¶; 24.353 + 24.354 +struct (ProcTypes.¶Instr_$SRLV¶ :: *) = { 24.355 + ProcTypes.rsrc :: ProcTypes.Rindx; 24.356 + ProcTypes.rdst :: ProcTypes.Rindx; 24.357 + ProcTypes.rshamt :: ProcTypes.Rindx 24.358 +}; 24.359 + 24.360 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$SRLV¶; 24.361 + 24.362 +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$SRLV¶; 24.363 + 24.364 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$SRLV¶; 24.365 + 24.366 +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$SRLV¶; 24.367 + 24.368 +struct (ProcTypes.¶Instr_$SRAV¶ :: *) = { 24.369 + ProcTypes.rsrc :: ProcTypes.Rindx; 24.370 + ProcTypes.rdst :: ProcTypes.Rindx; 24.371 + ProcTypes.rshamt :: ProcTypes.Rindx 24.372 +}; 24.373 + 24.374 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$SRAV¶; 24.375 + 24.376 +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$SRAV¶; 24.377 + 24.378 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$SRAV¶; 24.379 + 24.380 +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$SRAV¶; 24.381 + 24.382 +struct (ProcTypes.¶Instr_$ADDU¶ :: *) = { 24.383 + ProcTypes.rsrc1 :: ProcTypes.Rindx; 24.384 + ProcTypes.rsrc2 :: ProcTypes.Rindx; 24.385 + ProcTypes.rdst :: ProcTypes.Rindx 24.386 +}; 24.387 + 24.388 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$ADDU¶; 24.389 + 24.390 +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$ADDU¶; 24.391 + 24.392 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$ADDU¶; 24.393 + 24.394 +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$ADDU¶; 24.395 + 24.396 +struct (ProcTypes.¶Instr_$SUBU¶ :: *) = { 24.397 + ProcTypes.rsrc1 :: ProcTypes.Rindx; 24.398 + ProcTypes.rsrc2 :: ProcTypes.Rindx; 24.399 + ProcTypes.rdst :: ProcTypes.Rindx 24.400 +}; 24.401 + 24.402 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$SUBU¶; 24.403 + 24.404 +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$SUBU¶; 24.405 + 24.406 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$SUBU¶; 24.407 + 24.408 +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$SUBU¶; 24.409 + 24.410 +struct (ProcTypes.¶Instr_$AND¶ :: *) = { 24.411 + ProcTypes.rsrc1 :: ProcTypes.Rindx; 24.412 + ProcTypes.rsrc2 :: ProcTypes.Rindx; 24.413 + ProcTypes.rdst :: ProcTypes.Rindx 24.414 +}; 24.415 + 24.416 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$AND¶; 24.417 + 24.418 +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$AND¶; 24.419 + 24.420 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$AND¶; 24.421 + 24.422 +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$AND¶; 24.423 + 24.424 +struct (ProcTypes.¶Instr_$OR¶ :: *) = { 24.425 + ProcTypes.rsrc1 :: ProcTypes.Rindx; 24.426 + ProcTypes.rsrc2 :: ProcTypes.Rindx; 24.427 + ProcTypes.rdst :: ProcTypes.Rindx 24.428 +}; 24.429 + 24.430 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$OR¶; 24.431 + 24.432 +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$OR¶; 24.433 + 24.434 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$OR¶; 24.435 + 24.436 +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$OR¶; 24.437 + 24.438 +struct (ProcTypes.¶Instr_$XOR¶ :: *) = { 24.439 + ProcTypes.rsrc1 :: ProcTypes.Rindx; 24.440 + ProcTypes.rsrc2 :: ProcTypes.Rindx; 24.441 + ProcTypes.rdst :: ProcTypes.Rindx 24.442 +}; 24.443 + 24.444 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$XOR¶; 24.445 + 24.446 +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$XOR¶; 24.447 + 24.448 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$XOR¶; 24.449 + 24.450 +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$XOR¶; 24.451 + 24.452 +struct (ProcTypes.¶Instr_$NOR¶ :: *) = { 24.453 + ProcTypes.rsrc1 :: ProcTypes.Rindx; 24.454 + ProcTypes.rsrc2 :: ProcTypes.Rindx; 24.455 + ProcTypes.rdst :: ProcTypes.Rindx 24.456 +}; 24.457 + 24.458 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$NOR¶; 24.459 + 24.460 +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$NOR¶; 24.461 + 24.462 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$NOR¶; 24.463 + 24.464 +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$NOR¶; 24.465 + 24.466 +struct (ProcTypes.¶Instr_$SLT¶ :: *) = { 24.467 + ProcTypes.rsrc1 :: ProcTypes.Rindx; 24.468 + ProcTypes.rsrc2 :: ProcTypes.Rindx; 24.469 + ProcTypes.rdst :: ProcTypes.Rindx 24.470 +}; 24.471 + 24.472 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$SLT¶; 24.473 + 24.474 +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$SLT¶; 24.475 + 24.476 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$SLT¶; 24.477 + 24.478 +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$SLT¶; 24.479 + 24.480 +struct (ProcTypes.¶Instr_$SLTU¶ :: *) = { 24.481 + ProcTypes.rsrc1 :: ProcTypes.Rindx; 24.482 + ProcTypes.rsrc2 :: ProcTypes.Rindx; 24.483 + ProcTypes.rdst :: ProcTypes.Rindx 24.484 +}; 24.485 + 24.486 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$SLTU¶; 24.487 + 24.488 +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$SLTU¶; 24.489 + 24.490 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$SLTU¶; 24.491 + 24.492 +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$SLTU¶; 24.493 + 24.494 +struct (ProcTypes.¶Instr_$J¶ :: *) = { 24.495 + ProcTypes.target :: ProcTypes.Target 24.496 +}; 24.497 + 24.498 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$J¶; 24.499 + 24.500 +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$J¶; 24.501 + 24.502 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$J¶; 24.503 + 24.504 +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$J¶; 24.505 + 24.506 +struct (ProcTypes.¶Instr_$JAL¶ :: *) = { 24.507 + ProcTypes.target :: ProcTypes.Target 24.508 +}; 24.509 + 24.510 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$JAL¶; 24.511 + 24.512 +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$JAL¶; 24.513 + 24.514 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$JAL¶; 24.515 + 24.516 +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$JAL¶; 24.517 + 24.518 +struct (ProcTypes.¶Instr_$JR¶ :: *) = { 24.519 + ProcTypes.rsrc :: ProcTypes.Rindx 24.520 +}; 24.521 + 24.522 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$JR¶; 24.523 + 24.524 +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$JR¶; 24.525 + 24.526 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$JR¶; 24.527 + 24.528 +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$JR¶; 24.529 + 24.530 +struct (ProcTypes.¶Instr_$JALR¶ :: *) = { 24.531 + ProcTypes.rsrc :: ProcTypes.Rindx; 24.532 + ProcTypes.rdst :: ProcTypes.Rindx 24.533 +}; 24.534 + 24.535 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$JALR¶; 24.536 + 24.537 +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$JALR¶; 24.538 + 24.539 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$JALR¶; 24.540 + 24.541 +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$JALR¶; 24.542 + 24.543 +struct (ProcTypes.¶Instr_$BEQ¶ :: *) = { 24.544 + ProcTypes.rsrc1 :: ProcTypes.Rindx; 24.545 + ProcTypes.rsrc2 :: ProcTypes.Rindx; 24.546 + ProcTypes.offset :: ProcTypes.Simm 24.547 +}; 24.548 + 24.549 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$BEQ¶; 24.550 + 24.551 +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$BEQ¶; 24.552 + 24.553 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$BEQ¶; 24.554 + 24.555 +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$BEQ¶; 24.556 + 24.557 +struct (ProcTypes.¶Instr_$BNE¶ :: *) = { 24.558 + ProcTypes.rsrc1 :: ProcTypes.Rindx; 24.559 + ProcTypes.rsrc2 :: ProcTypes.Rindx; 24.560 + ProcTypes.offset :: ProcTypes.Simm 24.561 +}; 24.562 + 24.563 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$BNE¶; 24.564 + 24.565 +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$BNE¶; 24.566 + 24.567 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$BNE¶; 24.568 + 24.569 +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$BNE¶; 24.570 + 24.571 +struct (ProcTypes.¶Instr_$BLEZ¶ :: *) = { 24.572 + ProcTypes.rsrc :: ProcTypes.Rindx; 24.573 + ProcTypes.offset :: ProcTypes.Simm 24.574 +}; 24.575 + 24.576 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$BLEZ¶; 24.577 + 24.578 +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$BLEZ¶; 24.579 + 24.580 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$BLEZ¶; 24.581 + 24.582 +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$BLEZ¶; 24.583 + 24.584 +struct (ProcTypes.¶Instr_$BGTZ¶ :: *) = { 24.585 + ProcTypes.rsrc :: ProcTypes.Rindx; 24.586 + ProcTypes.offset :: ProcTypes.Simm 24.587 +}; 24.588 + 24.589 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$BGTZ¶; 24.590 + 24.591 +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$BGTZ¶; 24.592 + 24.593 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$BGTZ¶; 24.594 + 24.595 +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$BGTZ¶; 24.596 + 24.597 +struct (ProcTypes.¶Instr_$BLTZ¶ :: *) = { 24.598 + ProcTypes.rsrc :: ProcTypes.Rindx; 24.599 + ProcTypes.offset :: ProcTypes.Simm 24.600 +}; 24.601 + 24.602 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$BLTZ¶; 24.603 + 24.604 +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$BLTZ¶; 24.605 + 24.606 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$BLTZ¶; 24.607 + 24.608 +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$BLTZ¶; 24.609 + 24.610 +struct (ProcTypes.¶Instr_$BGEZ¶ :: *) = { 24.611 + ProcTypes.rsrc :: ProcTypes.Rindx; 24.612 + ProcTypes.offset :: ProcTypes.Simm 24.613 +}; 24.614 + 24.615 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$BGEZ¶; 24.616 + 24.617 +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$BGEZ¶; 24.618 + 24.619 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$BGEZ¶; 24.620 + 24.621 +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$BGEZ¶; 24.622 + 24.623 +struct (ProcTypes.¶Instr_$MFC0¶ :: *) = { 24.624 + ProcTypes.rdst :: ProcTypes.Rindx; 24.625 + ProcTypes.cop0src :: ProcTypes.CP0indx 24.626 +}; 24.627 + 24.628 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$MFC0¶; 24.629 + 24.630 +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$MFC0¶; 24.631 + 24.632 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$MFC0¶; 24.633 + 24.634 +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$MFC0¶; 24.635 + 24.636 +struct (ProcTypes.¶Instr_$MTC0¶ :: *) = { 24.637 + ProcTypes.rsrc :: ProcTypes.Rindx; 24.638 + ProcTypes.cop0dst :: ProcTypes.CP0indx 24.639 +}; 24.640 + 24.641 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$MTC0¶; 24.642 + 24.643 +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$MTC0¶; 24.644 + 24.645 +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$MTC0¶; 24.646 + 24.647 +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$MTC0¶; 24.648 + 24.649 +ProcTypes.opFUNC :: ¶Prelude®¶.¶Bit®¶ 6; 24.650 + 24.651 +ProcTypes.fcSLL :: ¶Prelude®¶.¶Bit®¶ 6; 24.652 + 24.653 +ProcTypes.opRT :: ¶Prelude®¶.¶Bit®¶ 6; 24.654 + 24.655 +ProcTypes.fcSRL :: ¶Prelude®¶.¶Bit®¶ 6; 24.656 + 24.657 +ProcTypes.opRS :: ¶Prelude®¶.¶Bit®¶ 6; 24.658 + 24.659 +ProcTypes.fcSRA :: ¶Prelude®¶.¶Bit®¶ 6; 24.660 + 24.661 +ProcTypes.fcSLLV :: ¶Prelude®¶.¶Bit®¶ 6; 24.662 + 24.663 +ProcTypes.opLW :: ¶Prelude®¶.¶Bit®¶ 6; 24.664 + 24.665 +ProcTypes.fcSRLV :: ¶Prelude®¶.¶Bit®¶ 6; 24.666 + 24.667 +ProcTypes.opSW :: ¶Prelude®¶.¶Bit®¶ 6; 24.668 + 24.669 +ProcTypes.fcSRAV :: ¶Prelude®¶.¶Bit®¶ 6; 24.670 + 24.671 +ProcTypes.fcADDU :: ¶Prelude®¶.¶Bit®¶ 6; 24.672 + 24.673 +ProcTypes.opADDIU :: ¶Prelude®¶.¶Bit®¶ 6; 24.674 + 24.675 +ProcTypes.fcSUBU :: ¶Prelude®¶.¶Bit®¶ 6; 24.676 + 24.677 +ProcTypes.opSLTI :: ¶Prelude®¶.¶Bit®¶ 6; 24.678 + 24.679 +ProcTypes.fcAND :: ¶Prelude®¶.¶Bit®¶ 6; 24.680 + 24.681 +ProcTypes.opSLTIU :: ¶Prelude®¶.¶Bit®¶ 6; 24.682 + 24.683 +ProcTypes.fcOR :: ¶Prelude®¶.¶Bit®¶ 6; 24.684 + 24.685 +ProcTypes.opANDI :: ¶Prelude®¶.¶Bit®¶ 6; 24.686 + 24.687 +ProcTypes.fcXOR :: ¶Prelude®¶.¶Bit®¶ 6; 24.688 + 24.689 +ProcTypes.opORI :: ¶Prelude®¶.¶Bit®¶ 6; 24.690 + 24.691 +ProcTypes.fcNOR :: ¶Prelude®¶.¶Bit®¶ 6; 24.692 + 24.693 +ProcTypes.opXORI :: ¶Prelude®¶.¶Bit®¶ 6; 24.694 + 24.695 +ProcTypes.fcSLT :: ¶Prelude®¶.¶Bit®¶ 6; 24.696 + 24.697 +ProcTypes.opLUI :: ¶Prelude®¶.¶Bit®¶ 6; 24.698 + 24.699 +ProcTypes.fcSLTU :: ¶Prelude®¶.¶Bit®¶ 6; 24.700 + 24.701 +ProcTypes.opJ :: ¶Prelude®¶.¶Bit®¶ 6; 24.702 + 24.703 +ProcTypes.opJAL :: ¶Prelude®¶.¶Bit®¶ 6; 24.704 + 24.705 +ProcTypes.fcJR :: ¶Prelude®¶.¶Bit®¶ 6; 24.706 + 24.707 +ProcTypes.fcJALR :: ¶Prelude®¶.¶Bit®¶ 6; 24.708 + 24.709 +ProcTypes.opBEQ :: ¶Prelude®¶.¶Bit®¶ 6; 24.710 + 24.711 +ProcTypes.opBNE :: ¶Prelude®¶.¶Bit®¶ 6; 24.712 + 24.713 +ProcTypes.opBLEZ :: ¶Prelude®¶.¶Bit®¶ 6; 24.714 + 24.715 +ProcTypes.opBGTZ :: ¶Prelude®¶.¶Bit®¶ 6; 24.716 + 24.717 +ProcTypes.rtBLTZ :: ¶Prelude®¶.¶Bit®¶ 5; 24.718 + 24.719 +ProcTypes.rtBGEZ :: ¶Prelude®¶.¶Bit®¶ 5; 24.720 + 24.721 +ProcTypes.rsMFC0 :: ¶Prelude®¶.¶Bit®¶ 5; 24.722 + 24.723 +ProcTypes.rsMTC0 :: ¶Prelude®¶.¶Bit®¶ 5; 24.724 + 24.725 +instance ProcTypes ¶Prelude®¶.¶Bits®¶ ProcTypes.Instr 32; 24.726 + 24.727 +instance ProcTypes Trace.Traceable ProcTypes.Instr 24.728 +}
25.1 Binary file core/sim/bdir_dut/ProcTypes.bo has changed
26.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 26.2 +++ b/core/sim/bdir_dut/Processor.bi Tue Apr 13 17:34:33 2010 -0400 26.3 @@ -0,0 +1,126 @@ 26.4 +signature Processor where { 26.5 +import ¶Assert®¶; 26.6 + 26.7 +import ¶ConfigReg®¶; 26.8 + 26.9 +import ¶Counter®¶; 26.10 + 26.11 +import ¶FIFOF_®¶; 26.12 + 26.13 +import ¶FIFOF®¶; 26.14 + 26.15 +import ¶FIFO®¶; 26.16 + 26.17 +import ¶Inout®¶; 26.18 + 26.19 +import ¶List®¶; 26.20 + 26.21 +import BFIFO; 26.22 + 26.23 +import ¶Clocks®¶; 26.24 + 26.25 +import ¶ListN®¶; 26.26 + 26.27 +import ¶Monad®¶; 26.28 + 26.29 +import ¶PrimArray®¶; 26.30 + 26.31 +import ¶RWire®¶; 26.32 + 26.33 +import ¶RegFile®¶; 26.34 + 26.35 +import SFIFO; 26.36 + 26.37 +import ¶Vector®¶; 26.38 + 26.39 +import ¶Connectable®¶; 26.40 + 26.41 +import ¶GetPut®¶; 26.42 + 26.43 +import ¶ClientServer®¶; 26.44 + 26.45 +import Trace; 26.46 + 26.47 +import MemTypes; 26.48 + 26.49 +import ProcTypes; 26.50 + 26.51 +import BRegFile; 26.52 + 26.53 +import BranchPred; 26.54 + 26.55 +interface (Processor.ProcStats :: *) = { 26.56 + Processor.num_cycles :: ¶GetPut®¶.¶Get®¶ ProcTypes.Stat; 26.57 + Processor.num_inst :: ¶GetPut®¶.¶Get®¶ ProcTypes.Stat 26.58 +}; 26.59 + 26.60 +instance Processor ¶Prelude®¶.¶PrimMakeUndefined®¶ Processor.ProcStats; 26.61 + 26.62 +instance Processor ¶Prelude®¶.¶PrimDeepSeqCond®¶ Processor.ProcStats; 26.63 + 26.64 +instance Processor ¶Prelude®¶.¶PrimMakeUninitialized®¶ Processor.ProcStats; 26.65 + 26.66 +interface (Processor.CPUToHost :: *) = { 26.67 + Processor.cpuToHost :: ¶Prelude®¶.¶Int®¶ 32 -> ¶Prelude®¶.¶Bit®¶ 32 {-# arg_names = [req] #-} 26.68 +}; 26.69 + 26.70 +instance Processor ¶Prelude®¶.¶PrimMakeUndefined®¶ Processor.CPUToHost; 26.71 + 26.72 +instance Processor ¶Prelude®¶.¶PrimDeepSeqCond®¶ Processor.CPUToHost; 26.73 + 26.74 +instance Processor ¶Prelude®¶.¶PrimMakeUninitialized®¶ Processor.CPUToHost; 26.75 + 26.76 +interface (Processor.Proc :: *) = { 26.77 + Processor.dmem_client :: ¶ClientServer®¶.¶Client®¶ MemTypes.DataReq MemTypes.DataResp; 26.78 + Processor.imem_client :: ¶ClientServer®¶.¶Client®¶ MemTypes.InstReq MemTypes.InstResp; 26.79 + Processor.statsEn_get :: ¶GetPut®¶.¶Get®¶ ¶Prelude®¶.¶Bool®¶; 26.80 + Processor.stats :: Processor.ProcStats; 26.81 + Processor.tohost :: Processor.CPUToHost 26.82 +}; 26.83 + 26.84 +instance Processor ¶Prelude®¶.¶PrimMakeUndefined®¶ Processor.Proc; 26.85 + 26.86 +instance Processor ¶Prelude®¶.¶PrimDeepSeqCond®¶ Processor.Proc; 26.87 + 26.88 +instance Processor ¶Prelude®¶.¶PrimMakeUninitialized®¶ Processor.Proc; 26.89 + 26.90 +data (Processor.Stage :: *) = Processor.PCgen () | Processor.Exec () | Processor.Writeback (); 26.91 + 26.92 +instance Processor ¶Prelude®¶.¶PrimMakeUndefined®¶ Processor.Stage; 26.93 + 26.94 +instance Processor ¶Prelude®¶.¶PrimDeepSeqCond®¶ Processor.Stage; 26.95 + 26.96 +instance Processor ¶Prelude®¶.¶PrimMakeUninitialized®¶ Processor.Stage; 26.97 + 26.98 +instance Processor ¶Prelude®¶.¶Eq®¶ Processor.Stage; 26.99 + 26.100 +instance Processor ¶Prelude®¶.¶Bits®¶ Processor.Stage 2; 26.101 + 26.102 +interface (Processor.BRFile :: *) = { 26.103 + Processor.wr :: ProcTypes.Rindx -> 26.104 + ¶Prelude®¶.¶Bit®¶ 32 -> ¶Prelude®¶.¶Action®¶ {-# arg_names = [rindx, ¡data¡] #-}; 26.105 + Processor.rd1 :: ProcTypes.Rindx -> ¶Prelude®¶.¶Bit®¶ 32 {-# arg_names = [rindx] #-}; 26.106 + Processor.rd2 :: ProcTypes.Rindx -> ¶Prelude®¶.¶Bit®¶ 32 {-# arg_names = [rindx] #-} 26.107 +}; 26.108 + 26.109 +instance Processor ¶Prelude®¶.¶PrimMakeUndefined®¶ Processor.BRFile; 26.110 + 26.111 +instance Processor ¶Prelude®¶.¶PrimDeepSeqCond®¶ Processor.BRFile; 26.112 + 26.113 +instance Processor ¶Prelude®¶.¶PrimMakeUninitialized®¶ Processor.BRFile; 26.114 + 26.115 +Processor.mkBRFile :: (¶Prelude®¶.¶IsModule®¶ _m__ _c__) => _m__ Processor.BRFile; 26.116 + 26.117 +Processor.slt :: ¶Prelude®¶.¶Bit®¶ 32 -> ¶Prelude®¶.¶Bit®¶ 32 -> ¶Prelude®¶.¶Bit®¶ 32; 26.118 + 26.119 +Processor.sltu :: ¶Prelude®¶.¶Bit®¶ 32 -> ¶Prelude®¶.¶Bit®¶ 32 -> ¶Prelude®¶.¶Bit®¶ 32; 26.120 + 26.121 +Processor.rshft :: ¶Prelude®¶.¶Bit®¶ 32 -> ¶Prelude®¶.¶Bit®¶ 32; 26.122 + 26.123 +Processor.findwbf :: ProcTypes.Rindx -> ProcTypes.WBResult -> ¶Prelude®¶.¶Bool®¶; 26.124 + 26.125 +Processor.stall :: ProcTypes.Instr -> 26.126 + SFIFO.SFIFO ProcTypes.WBResult ProcTypes.Rindx -> ¶Prelude®¶.¶Bool®¶; 26.127 + 26.128 +Processor.mkProc :: (¶Prelude®¶.¶IsModule®¶ _m__ _c__) => _m__ Processor.Proc 26.129 +}
27.1 Binary file core/sim/bdir_dut/Processor.bo has changed
28.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 28.2 +++ b/core/sim/bdir_dut/SFIFO.bi Tue Apr 13 17:34:33 2010 -0400 28.3 @@ -0,0 +1,51 @@ 28.4 +signature SFIFO where { 28.5 +import ¶ConfigReg®¶; 28.6 + 28.7 +import ¶FIFOF_®¶; 28.8 + 28.9 +import ¶FIFOF®¶; 28.10 + 28.11 +import ¶FIFO®¶; 28.12 + 28.13 +import ¶List®¶; 28.14 + 28.15 +import ¶Monad®¶; 28.16 + 28.17 +import ¶RWire®¶; 28.18 + 28.19 +interface (SFIFO.SFIFO :: * -> * -> *) alpha_T search_T = { 28.20 + SFIFO.enq :: alpha_T -> ¶Prelude®¶.¶Action®¶ {-# arg_names = [x] #-}; 28.21 + SFIFO.deq :: ¶Prelude®¶.¶Action®¶ {-# arg_names = [] #-}; 28.22 + SFIFO.first :: alpha_T {-# arg_names = [] #-}; 28.23 + SFIFO.clear :: ¶Prelude®¶.¶Action®¶ {-# arg_names = [] #-}; 28.24 + SFIFO.find :: search_T -> ¶Prelude®¶.¶Bool®¶ {-# arg_names = [x] #-}; 28.25 + SFIFO.find2 :: search_T -> ¶Prelude®¶.¶Bool®¶ {-# arg_names = [x] #-} 28.26 +}; 28.27 + 28.28 +instance SFIFO (¶Prelude®¶.¶PrimMakeUndefined®¶ alpha_T) => 28.29 + ¶Prelude®¶.¶PrimMakeUndefined®¶ (SFIFO.SFIFO alpha_T search_T); 28.30 + 28.31 +instance SFIFO (¶Prelude®¶.¶PrimDeepSeqCond®¶ alpha_T) => 28.32 + ¶Prelude®¶.¶PrimDeepSeqCond®¶ (SFIFO.SFIFO alpha_T search_T); 28.33 + 28.34 +instance SFIFO (¶Prelude®¶.¶PrimMakeUninitialized®¶ alpha_T) => 28.35 + ¶Prelude®¶.¶PrimMakeUninitialized®¶ (SFIFO.SFIFO alpha_T search_T); 28.36 + 28.37 +SFIFO.mkSFIFO :: (¶Prelude®¶.¶Bits®¶ alpha_T asz, ¶Prelude®¶.¶IsModule®¶ _m__ _c__) => 28.38 + (search_T -> alpha_T -> ¶Prelude®¶.¶Bool®¶) -> _m__ (SFIFO.SFIFO alpha_T search_T); 28.39 + 28.40 +SFIFO.mkSFIFO1 :: (¶Prelude®¶.¶Eq®¶ alpha_T, 28.41 + ¶Prelude®¶.¶Bits®¶ alpha_T asz, 28.42 + ¶Prelude®¶.¶IsModule®¶ _m__ _c__) => 28.43 + (search_T -> alpha_T -> ¶Prelude®¶.¶Bool®¶) -> _m__ (SFIFO.SFIFO alpha_T search_T); 28.44 + 28.45 +SFIFO.mkSizedSFIFOInternal :: (¶Prelude®¶.¶Bits®¶ alpha_T alpha_SZ, 28.46 + ¶Prelude®¶.¶IsModule®¶ _m__ _c__) => 28.47 + ¶Prelude®¶.¶Integer®¶ -> 28.48 + (search_T -> alpha_T -> ¶Prelude®¶.¶Bool®¶) -> 28.49 + (search_T -> alpha_T -> ¶Prelude®¶.¶Bool®¶) -> _m__ (SFIFO.SFIFO alpha_T search_T); 28.50 + 28.51 +SFIFO.mkSizedSFIFO :: (¶Prelude®¶.¶Bits®¶ alpha_T asz, ¶Prelude®¶.¶IsModule®¶ _m__ _c__) => 28.52 + ¶Prelude®¶.¶Integer®¶ -> 28.53 + (search_T -> alpha_T -> ¶Prelude®¶.¶Bool®¶) -> _m__ (SFIFO.SFIFO alpha_T search_T) 28.54 +}
29.1 Binary file core/sim/bdir_dut/SFIFO.bo has changed
30.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 30.2 +++ b/core/sim/bdir_dut/SceMiLayer.bi Tue Apr 13 17:34:33 2010 -0400 30.3 @@ -0,0 +1,174 @@ 30.4 +signature SceMiLayer where { 30.5 +import ¶Assert®¶; 30.6 + 30.7 +import ¶ConfigReg®¶; 30.8 + 30.9 +import ¶Counter®¶; 30.10 + 30.11 +import ¶DReg®¶; 30.12 + 30.13 +import ¶EdgeDetect®¶; 30.14 + 30.15 +import ¶FIFOF_®¶; 30.16 + 30.17 +import ¶FIFOF®¶; 30.18 + 30.19 +import ¶FIFO®¶; 30.20 + 30.21 +import ¶HList®¶; 30.22 + 30.23 +import ¶Inout®¶; 30.24 + 30.25 +import ¶List®¶; 30.26 + 30.27 +import BFIFO; 30.28 + 30.29 +import ¶Clocks®¶; 30.30 + 30.31 +import ¶DiniPCIE®¶; 30.32 + 30.33 +import ¶ListN®¶; 30.34 + 30.35 +import ¶ModuleContextCore®¶; 30.36 + 30.37 +import ¶ModuleContext®¶; 30.38 + 30.39 +import ¶Monad®¶; 30.40 + 30.41 +import ¶PrimArray®¶; 30.42 + 30.43 +import ¶RWire®¶; 30.44 + 30.45 +import ¶RegFile®¶; 30.46 + 30.47 +import ¶Real®¶; 30.48 + 30.49 +import ¶RevertingVirtualReg®¶; 30.50 + 30.51 +import ¶Reserved®¶; 30.52 + 30.53 +import SFIFO; 30.54 + 30.55 +import ¶Vector®¶; 30.56 + 30.57 +import ¶BRAMCore®¶; 30.58 + 30.59 +import ¶BUtils®¶; 30.60 + 30.61 +import ¶Connectable®¶; 30.62 + 30.63 +import ¶DefaultValue®¶; 30.64 + 30.65 +import ¶Gearbox®¶; 30.66 + 30.67 +import ¶GetPut®¶; 30.68 + 30.69 +import ¶AlignedFIFOs®¶; 30.70 + 30.71 +import ¶ClientServer®¶; 30.72 + 30.73 +import ¶FIFOLevel®¶; 30.74 + 30.75 +import ¶SceMiDefines®¶; 30.76 + 30.77 +import ¶SceMiProxies®¶; 30.78 + 30.79 +import ¶SpecialFIFOs®¶; 30.80 + 30.81 +import ¶SceMiInternals®¶; 30.82 + 30.83 +import ¶SceMiAldecMacros®¶; 30.84 + 30.85 +import ¶SceMiEveMacros®¶; 30.86 + 30.87 +import ¶SceMiMacros®¶; 30.88 + 30.89 +import ¶TieOff®¶; 30.90 + 30.91 +import Trace; 30.92 + 30.93 +import MemTypes; 30.94 + 30.95 +import MemArb; 30.96 + 30.97 +import ProcTypes; 30.98 + 30.99 +import BRegFile; 30.100 + 30.101 +import BranchPred; 30.102 + 30.103 +import DataCacheBlocking; 30.104 + 30.105 +import InstCacheBlocking; 30.106 + 30.107 +import Processor; 30.108 + 30.109 +import Core; 30.110 + 30.111 +import ¶UnitAppendList®¶; 30.112 + 30.113 +import ¶XilinxCells®¶; 30.114 + 30.115 +import ¶SceMiClocks®¶; 30.116 + 30.117 +import ¶SceMiDiniPCIE®¶; 30.118 + 30.119 +import ¶SceMiTCP®¶; 30.120 + 30.121 +import ¶XilinxPCIE®¶; 30.122 + 30.123 +import ¶SceMiVirtex5PCIE®¶; 30.124 + 30.125 +import ¶SceMiPCIE®¶; 30.126 + 30.127 +import ¶SceMiCore®¶; 30.128 + 30.129 +import ¶SceMiXactors®¶; 30.130 + 30.131 +import ¶SceMiSerialProbe®¶; 30.132 + 30.133 +import ¶SceMi®¶; 30.134 + 30.135 +interface (SceMiLayer.DutWrapper :: *) = { 30.136 + SceMiLayer.core :: Core.Core; 30.137 + SceMiLayer.doreset :: ¶GetPut®¶.¶Put®¶ (¶Prelude®¶.¶Bit®¶ 1) 30.138 +}; 30.139 + 30.140 +instance SceMiLayer ¶Prelude®¶.¶PrimMakeUndefined®¶ SceMiLayer.DutWrapper; 30.141 + 30.142 +instance SceMiLayer ¶Prelude®¶.¶PrimDeepSeqCond®¶ SceMiLayer.DutWrapper; 30.143 + 30.144 +instance SceMiLayer ¶Prelude®¶.¶PrimMakeUninitialized®¶ SceMiLayer.DutWrapper; 30.145 + 30.146 +SceMiLayer.mkDutWrapper :: ¶Prelude®¶.¶Module®¶ SceMiLayer.DutWrapper; 30.147 + 30.148 +SceMiLayer.mkSceMiLayer :: ¶SceMiInternals®¶.¶SceMiModule®¶ ¶Prelude®¶.¶Empty®¶; 30.149 + 30.150 +SceMiLayer.mkCPUToHostXactor :: Processor.CPUToHost -> 30.151 + ¶SceMiDefines®¶.¶SceMiClockPortIfc®¶ -> 30.152 + ¶SceMiInternals®¶.¶SceMiModule®¶ ¶Prelude®¶.¶Empty®¶; 30.153 + 30.154 +data (SceMiLayer.StatID :: *) = 30.155 + SceMiLayer.DCACHE_ACCESSES () | 30.156 + SceMiLayer.DCACHE_MISSES () | 30.157 + SceMiLayer.DCACHE_WRITEBACKS () | 30.158 + SceMiLayer.ICACHE_ACCESSES () | 30.159 + SceMiLayer.ICACHE_MISSES () | 30.160 + SceMiLayer.ICACHE_EVICTIONS () | 30.161 + SceMiLayer.PROC_INST () | 30.162 + SceMiLayer.PROC_CYCLES (); 30.163 + 30.164 +instance SceMiLayer ¶Prelude®¶.¶PrimMakeUndefined®¶ SceMiLayer.StatID; 30.165 + 30.166 +instance SceMiLayer ¶Prelude®¶.¶PrimDeepSeqCond®¶ SceMiLayer.StatID; 30.167 + 30.168 +instance SceMiLayer ¶Prelude®¶.¶PrimMakeUninitialized®¶ SceMiLayer.StatID; 30.169 + 30.170 +instance SceMiLayer ¶Prelude®¶.¶Bits®¶ SceMiLayer.StatID 3; 30.171 + 30.172 +instance SceMiLayer ¶Prelude®¶.¶Eq®¶ SceMiLayer.StatID; 30.173 + 30.174 +SceMiLayer.mkCoreStatsXactor :: Core.CoreStats -> 30.175 + ¶SceMiDefines®¶.¶SceMiClockPortIfc®¶ -> 30.176 + ¶SceMiInternals®¶.¶SceMiModule®¶ ¶Prelude®¶.¶Empty®¶ 30.177 +}
31.1 Binary file core/sim/bdir_dut/SceMiLayer.bo has changed
32.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 32.2 +++ b/core/sim/bdir_dut/Trace.bi Tue Apr 13 17:34:33 2010 -0400 32.3 @@ -0,0 +1,56 @@ 32.4 +signature Trace where { 32.5 +import ¶Counter®¶; 32.6 + 32.7 +import ¶FIFOF_®¶; 32.8 + 32.9 +import ¶FIFOF®¶; 32.10 + 32.11 +import ¶FIFO®¶; 32.12 + 32.13 +import ¶Inout®¶; 32.14 + 32.15 +import ¶List®¶; 32.16 + 32.17 +import ¶Clocks®¶; 32.18 + 32.19 +import ¶ListN®¶; 32.20 + 32.21 +import ¶PrimArray®¶; 32.22 + 32.23 +import ¶Vector®¶; 32.24 + 32.25 +import ¶Connectable®¶; 32.26 + 32.27 +import ¶GetPut®¶; 32.28 + 32.29 +import ¶ClientServer®¶; 32.30 + 32.31 +class (Trace.Traceable :: * -> *) item_t where { 32.32 + Trace.traceTiny :: ¶Prelude®¶.¶String®¶ -> 32.33 + ¶Prelude®¶.¶String®¶ -> item_t -> ¶Prelude®¶.¶Action®¶ {-# arg_names = [loc, traceTag, item] #-}; 32.34 + Trace.traceFull :: ¶Prelude®¶.¶String®¶ -> 32.35 + ¶Prelude®¶.¶String®¶ -> item_t -> ¶Prelude®¶.¶Action®¶ {-# arg_names = [loc, traceTag, item] #-} 32.36 +}; 32.37 + 32.38 +instance Trace Trace.Traceable ¶Prelude®¶.¶String®¶; 32.39 + 32.40 +instance Trace Trace.Traceable (¶Prelude®¶.¶Bit®¶ n); 32.41 + 32.42 +Trace.traceGet :: (Trace.Traceable item_t) => 32.43 + ¶Prelude®¶.¶String®¶ -> ¶Prelude®¶.¶String®¶ -> ¶GetPut®¶.¶Get®¶ item_t -> ¶GetPut®¶.¶Get®¶ item_t; 32.44 + 32.45 +Trace.tracePut :: (Trace.Traceable item_t) => 32.46 + ¶Prelude®¶.¶String®¶ -> ¶Prelude®¶.¶String®¶ -> ¶GetPut®¶.¶Put®¶ item_t -> ¶GetPut®¶.¶Put®¶ item_t; 32.47 + 32.48 +Trace.traceClient :: (Trace.Traceable resp_t, Trace.Traceable req_t) => 32.49 + ¶Prelude®¶.¶String®¶ -> 32.50 + ¶Prelude®¶.¶String®¶ -> 32.51 + ¶Prelude®¶.¶String®¶ -> 32.52 + ¶ClientServer®¶.¶Client®¶ req_t resp_t -> ¶ClientServer®¶.¶Client®¶ req_t resp_t; 32.53 + 32.54 +Trace.traceServer :: (Trace.Traceable resp_t, Trace.Traceable req_t) => 32.55 + ¶Prelude®¶.¶String®¶ -> 32.56 + ¶Prelude®¶.¶String®¶ -> 32.57 + ¶Prelude®¶.¶String®¶ -> 32.58 + ¶ClientServer®¶.¶Server®¶ req_t resp_t -> ¶ClientServer®¶.¶Server®¶ req_t resp_t 32.59 +}
33.1 Binary file core/sim/bdir_dut/Trace.bo has changed
34.1 Binary file core/sim/bdir_dut/mkBFIFO_16.ba has changed
35.1 Binary file core/sim/bdir_dut/mkBridge.ba has changed
36.1 Binary file core/sim/bdir_dut/mkCore.ba has changed
37.1 Binary file core/sim/bdir_dut/mkDataCache.ba has changed
38.1 Binary file core/sim/bdir_dut/mkDutWrapper.ba has changed
39.1 Binary file core/sim/bdir_dut/mkInstCache.ba has changed
40.1 Binary file core/sim/bdir_dut/mkMemArb.ba has changed
41.1 Binary file core/sim/bdir_dut/mkProc.ba has changed
42.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 42.2 +++ b/core/sim/scemi.params Tue Apr 13 17:34:33 2010 -0400 42.3 @@ -0,0 +1,70 @@ 42.4 +// Sce-Mi parameters file generated on: Mon Apr 12 09:58:28 EDT 2010 42.5 +// By: Bluespec scemilink utility, version 2010.02.beta4 (build 19725, 2010-02-26) 42.6 + 42.7 +// ObjectKind Index AttributeName Value 42.8 + 42.9 +Clock 0 ClockName "scemi_clk_port" 42.10 +Clock 0 RatioNumerator 1 42.11 +Clock 0 RatioDenominator 1 42.12 +Clock 0 DutyHi 0 42.13 +Clock 0 DutyLo 100 42.14 +Clock 0 Phase 0 42.15 +Clock 0 ResetCycles 8 42.16 + 42.17 +MessageOutPort 3 TransactorName "" 42.18 +MessageOutPort 3 PortName "scemi_tohost_response_outport" 42.19 +MessageOutPort 3 PortWidth 32 42.20 +MessageOutPort 3 ChannelId 9 42.21 +MessageOutPort 3 Type "Bit#(32)" 42.22 + 42.23 +MessageOutPort 2 TransactorName "" 42.24 +MessageOutPort 2 PortName "scemi_stats_xx_resp_outport" 42.25 +MessageOutPort 2 PortWidth 18 42.26 +MessageOutPort 2 ChannelId 8 42.27 +MessageOutPort 2 Type "Int#(18)" 42.28 + 42.29 +MessageOutPort 1 TransactorName "" 42.30 +MessageOutPort 1 PortName "scemi_shutdown_ctrl_out" 42.31 +MessageOutPort 1 PortWidth 1 42.32 +MessageOutPort 1 ChannelId 7 42.33 +MessageOutPort 1 Type "Bool" 42.34 + 42.35 +MessageOutPort 0 TransactorName "" 42.36 +MessageOutPort 0 PortName "scemi_mmem_req_outport" 42.37 +MessageOutPort 0 PortWidth 73 42.38 +MessageOutPort 0 ChannelId 6 42.39 +MessageOutPort 0 Type "MemTypes::MemReq#(32,8,32)" 42.40 + 42.41 +MessageInPort 4 TransactorName "" 42.42 +MessageInPort 4 PortName "scemi_tohost_request_inport" 42.43 +MessageInPort 4 PortWidth 32 42.44 +MessageInPort 4 ChannelId 5 42.45 +MessageInPort 4 Type "Int#(32)" 42.46 + 42.47 +MessageInPort 3 TransactorName "" 42.48 +MessageInPort 3 PortName "scemi_stats_xx_req_inport" 42.49 +MessageInPort 3 PortWidth 3 42.50 +MessageInPort 3 ChannelId 4 42.51 +MessageInPort 3 Type "SceMiLayer::StatID" 42.52 + 42.53 +MessageInPort 2 TransactorName "" 42.54 +MessageInPort 2 PortName "scemi_shutdown_ctrl_in" 42.55 +MessageInPort 2 PortWidth 1 42.56 +MessageInPort 2 ChannelId 3 42.57 +MessageInPort 2 Type "Bool" 42.58 + 42.59 +MessageInPort 1 TransactorName "" 42.60 +MessageInPort 1 PortName "scemi_mmem_resp_inport" 42.61 +MessageInPort 1 PortWidth 41 42.62 +MessageInPort 1 ChannelId 2 42.63 +MessageInPort 1 Type "MemTypes::MemResp#(8,32)" 42.64 + 42.65 +MessageInPort 0 TransactorName "" 42.66 +MessageInPort 0 PortName "scemi_doreset_inport" 42.67 +MessageInPort 0 PortWidth 1 42.68 +MessageInPort 0 ChannelId 1 42.69 +MessageInPort 0 Type "Bit#(1)" 42.70 + 42.71 +Link 0 LinkType "TCP" 42.72 +Link 0 TCPAddress "127.0.0.1" 42.73 +Link 0 TCPPort 4321
43.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 43.2 +++ b/core/sim/sim.bspec Tue Apr 13 17:34:33 2010 -0400 43.3 @@ -0,0 +1,86 @@ 43.4 +### Bluespec project file. 43.5 +### Generated by Bluespec Workstation on Fri Mar 19 21:06:20 EDT 2010 43.6 + 43.7 +global PROJECT 43.8 + 43.9 +set PROJECT(COMP_BDIR) "bdir_dut" 43.10 +set PROJECT(COMP_BSC_OPTIONS) "-keep-fires -aggressive-conditions -D SCEMI_TCP" 43.11 +set PROJECT(COMP_BSC_TYPE) "bluesim" 43.12 +set PROJECT(COMP_INFO_DIR) "info_dut" 43.13 +set PROJECT(COMP_RTS_OPTIONS) "" 43.14 +set PROJECT(COMP_SIMDIR) "simdir_dut" 43.15 +set PROJECT(COMP_TYPE) "bsc" 43.16 +set PROJECT(TB_COMP_TYPE) "ccd" 43.17 +set PROJECT(COMP_VDIR) "vlog_dut" 43.18 +set PROJECT(CURRENT_DIR) "" 43.19 +set PROJECT(EDITOR_NAME) "other" 43.20 +set PROJECT(EXCLUDED_FILES) "" 43.21 +set PROJECT(INCLUDED_FILES) "*.bsv" 43.22 +set PROJECT(GEN_FILES) "" 43.23 +set PROJECT(LINK_BSC_OPTIONS) "-keep-fires" 43.24 +set PROJECT(LINK_COMMAND) "build -f link_for_bluesim -t link_for_bluesim" 43.25 +set PROJECT(LINK_MAKEFILE) "Makefile" 43.26 +set PROJECT(LINK_MAKE_OPTIONS) "" 43.27 +set PROJECT(LINK_OUTDIR) "." 43.28 +set PROJECT(LINK_OUTNAME) "out" 43.29 +set PROJECT(LINK_SIM_TARGET) "" 43.30 +set PROJECT(LINK_CLEAN_TARGET) "" 43.31 +set PROJECT(LINK_FULL_CLEAN_TARGET) "" 43.32 +set PROJECT(LINK_TARGET) "" 43.33 +set PROJECT(LINK_TYPE) "custom_command" 43.34 +set PROJECT(MAIN_PLACEMENT) "700x350+0+0" 43.35 +set PROJECT(MAKE_CLEAN) "clean" 43.36 +set PROJECT(MAKE_FILE) "Makefile" 43.37 +set PROJECT(MAKE_FULLCLEAN) "clean" 43.38 +set PROJECT(MAKE_OPTIONS) "" 43.39 +set PROJECT(MAKE_TARGET) "" 43.40 +set PROJECT(MODULE_PLACEMENT) "500x350+50+500" 43.41 +set PROJECT(PATHS) "bdir_dut . %/Prelude %/Libraries %/board_support/bridges ./../scemi ./../src" 43.42 +set PROJECT(PACKAGE_PLACEMENT) "770x420+475+150" 43.43 +set PROJECT(PROJECT_PLACEMENT) "250x460+0+385" 43.44 +set PROJECT(RUN_OPTIONS) "" 43.45 +set PROJECT(SCHEDULE_PLACEMENT) "650x650+500+225" 43.46 +set PROJECT(SCEMI_ENABLE) "1" 43.47 +set PROJECT(SCEMI_LINK_OPTIONS) "--sim --params=scemi.params" 43.48 +set PROJECT(SCEMI_COMP_MAKEFILE) "" 43.49 +set PROJECT(SCEMI_BSVTB) "0" 43.50 +set PROJECT(SCEMI_TB_FILE) "" 43.51 +set PROJECT(SCEMI_TB_MOD) "" 43.52 +set PROJECT(SCEMI_COMPBSC) "off" 43.53 +set PROJECT(SCEMI_COMPOPT) "" 43.54 +set PROJECT(SCEMI_BSC_LINK_NAME) "" 43.55 +set PROJECT(SCEMI_BSC_LINK_ODIR) "" 43.56 +set PROJECT(SCEMI_BSC_LINK_OPTS) "" 43.57 +set PROJECT(SCEMI_BSC_LINK_RUNOPTS) "" 43.58 +set PROJECT(SCEMI_COMP_TARGET) "" 43.59 +set PROJECT(SCEMI_BSC_LINKMK_TARGET) "" 43.60 +set PROJECT(SCEMI_BSC_LINKMK_RUN) "" 43.61 +set PROJECT(SCEMI_TB_CC_CC) "build tb" 43.62 +set PROJECT(SCEMI_TB_CC_LINK) "echo linked" 43.63 +set PROJECT(SCEMI_TB_CC_RUN) "./tb" 43.64 +set PROJECT(SIM_CUSTOM_COMMAND) "./bsim_dut 2> err.txt" 43.65 +set PROJECT(SIM_EXE) "" 43.66 +set PROJECT(SIM_NAME) "cvc" 43.67 +set PROJECT(SIM_OPTIONS) "" 43.68 +set PROJECT(SOURCE) "" 43.69 +set PROJECT(STATUS) "" 43.70 +set PROJECT(TOP_FILE) "../scemi/Bridge.bsv" 43.71 +set PROJECT(TOP_MODULE) "mkBridge" 43.72 +set PROJECT(TYPE_PLACEMENT) "770x420+475+540" 43.73 +set PROJECT(VIEWER_CLOSE) "close" 43.74 +set PROJECT(WIZARD_PLACEMENT) "1024x700+50+50" 43.75 +set PROJECT(EDITOR_GVIM) "gvim" 43.76 +set PROJECT(EDITOR_EMACS) "emacs" 43.77 +set PROJECT(EDITOR_OTHER) "/usr/bin/vim %f" 43.78 +::Waves::set_options {Mentor,Command} {Not supported} 43.79 +::Waves::set_options {GtkWave,Options} {-W} 43.80 +::Waves::set_options {viewer} {Novas} 43.81 +::Waves::set_options {Novas,Command} {nWave} 43.82 +::Waves::set_options {Mentor,Options} {Not supported} 43.83 +::Waves::set_options {ExtendNameMode} {noextend} 43.84 +::Waves::set_options {Novas,Options} {-nologo} 43.85 +::Waves::set_options {BoolDisplayMode} {nobenum} 43.86 +::Waves::set_options {nonbsv_hierarchy} {/main/top} 43.87 +::Waves::set_options {GtkWave,Command} {gtkx} 43.88 +::Waves::set_options {StartTimeout} {20} 43.89 +::Waves::set_options {DumpExtensions} {vcd fsdb wlf}
44.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 44.2 +++ b/core/src/BFIFO.bsv Tue Apr 13 17:34:33 2010 -0400 44.3 @@ -0,0 +1,222 @@ 44.4 +import FIFO::*; 44.5 +import FIFOF::*; 44.6 +import List::*; 44.7 +import Assert::*; 44.8 + 44.9 +module mkBFIFO1( FIFO#(item_t) ) provisos ( Bits#(item_t,item_sz) ); 44.10 + 44.11 + RWire#(item_t) inputWire <- mkRWire(); 44.12 + PulseWire deqEnabled <- mkPulseWire(); 44.13 + PulseWire clearEnabled <- mkPulseWire(); 44.14 + 44.15 + Reg#(item_t) register <- mkRegU(); 44.16 + Reg#(Bool) valid <- mkReg(False); 44.17 + 44.18 + // If there is an input item on the inputWire wire and dequeue did not 44.19 + // execute this cycle then we need to store the item in the register 44.20 + 44.21 + (*fire_when_enabled*) 44.22 + rule update ( True ); 44.23 + case (inputWire.wget()) matches 44.24 + tagged Invalid: 44.25 + if (deqEnabled || clearEnabled) 44.26 + valid <= False; 44.27 + tagged Valid .x: 44.28 + begin 44.29 + register <= x; 44.30 + valid <= !(deqEnabled || clearEnabled); 44.31 + end 44.32 + endcase 44.33 + endrule 44.34 + 44.35 + // On enqueue we write the input item to the inputWire wire 44.36 + 44.37 + method Action enq( item_t item ) if ( !valid ); 44.38 + inputWire.wset(item); 44.39 + endmethod 44.40 + 44.41 + // On dequeue we always invalidate the storage register regardless 44.42 + // of whether or not the item was actually bypassed or not. We also 44.43 + // set a combinational signal so that we know not to move the item 44.44 + // into the register this cycle. 44.45 + 44.46 + method Action deq() if ( valid || isValid(inputWire.wget()) ); 44.47 + deqEnabled.send(); 44.48 + endmethod 44.49 + 44.50 + // We get the item either from the register (if register is valid) or 44.51 + // from the combinational bypasss (if the rwire is valid). 44.52 + 44.53 + method item_t first() if ( valid || isValid(inputWire.wget()) ); 44.54 + if ( valid ) 44.55 + return register; 44.56 + else 44.57 + return unJust(inputWire.wget()); 44.58 + endmethod 44.59 + 44.60 + method Action clear(); 44.61 + clearEnabled.send(); 44.62 + endmethod 44.63 + 44.64 +endmodule 44.65 + 44.66 +module mkSizedBFIFO#(Integer n) ( FIFO#(item_t) ) provisos ( Bits#(item_t,item_sz) ); 44.67 + 44.68 + RWire#(item_t) inputWire <- mkRWire(); 44.69 + PulseWire deqEnabled <- mkPulseWire(); 44.70 + PulseWire clearEnabled <- mkPulseWire(); 44.71 + 44.72 + List#(Reg#(item_t)) registers <- replicateM(n, mkRegU); 44.73 + List#(Reg#(Bool)) valids <- replicateM(n, mkReg(False)); 44.74 + 44.75 + function Nat getNextFree (List#(Reg#(Bool)) vs); 44.76 + 44.77 + Nat res = fromInteger(n - 1); 44.78 + 44.79 + for (Integer x = n - 1; x > -1; x = x - 1) 44.80 + res = !vs[x]._read() ? fromInteger(x) : res; 44.81 + 44.82 + return res; 44.83 + 44.84 + endfunction 44.85 + 44.86 + function Bool notFull(); 44.87 + 44.88 + Bool full = True; 44.89 + 44.90 + for (Integer x = 0; x < length(valids); x = x + 1) 44.91 + full = full && valids[x]._read(); 44.92 + 44.93 + return !full; 44.94 + 44.95 + endfunction 44.96 + // If there is an input item on the inputWire wire and dequeue did not 44.97 + // execute this cycle then we need to store the item in the register 44.98 + 44.99 + rule update ( True ); 44.100 + Nat next = getNextFree(valids); 44.101 + 44.102 + next = (deqEnabled) ? next - 1 : next; 44.103 + 44.104 + (valids[next]) <= isValid(inputWire.wget()); 44.105 + (registers[next]) <= validValue(inputWire.wget()); 44.106 + 44.107 + if (deqEnabled && !clearEnabled) 44.108 + begin 44.109 + 44.110 + for (Nat x = 0; x < (next - 1); x = x + 1) 44.111 + begin 44.112 + (valids[x]) <= valids[x+1]._read(); 44.113 + (registers[x]) <= registers[x+1]._read(); 44.114 + end 44.115 + 44.116 + end 44.117 + else if (clearEnabled) 44.118 + begin 44.119 + 44.120 + for (Integer x = 0; x < n; x = x + 1) 44.121 + (valids[x]) <= False; 44.122 + 44.123 + end 44.124 + endrule 44.125 + 44.126 + // On enqueue we write the input item to the inputWire wire 44.127 + 44.128 + method Action enq( item_t item ) if ( notFull ); 44.129 + inputWire.wset(item); 44.130 + endmethod 44.131 + 44.132 + // On dequeue we always invalidate the storage register regardless 44.133 + // of whether or not the item was actually bypassed or not. We also 44.134 + // set a combinational signal so that we know not to move the item 44.135 + // into the register this cycle. 44.136 + 44.137 + method Action deq() if ( valids[0]._read() || isValid(inputWire.wget()) ); 44.138 + deqEnabled.send(); 44.139 + endmethod 44.140 + 44.141 + // We get the item either from the register (if register is valid) or 44.142 + // from the combinational bypasss (if the rwire is valid). 44.143 + 44.144 + method item_t first() if ( valids[0]._read() || isValid(inputWire.wget()) ); 44.145 + if ( valids[0]._read() ) 44.146 + return registers[0]._read(); 44.147 + else 44.148 + return unJust(inputWire.wget()); 44.149 + endmethod 44.150 + 44.151 + 44.152 + method Action clear(); 44.153 + clearEnabled.send(); 44.154 + endmethod 44.155 + 44.156 +endmodule 44.157 + 44.158 + 44.159 +module mkBFIFOF1( FIFOF#(item_t) ) provisos ( Bits#(item_t,item_sz) ); 44.160 + 44.161 + RWire#(item_t) inputWire <- mkRWire(); 44.162 + RWire#(Bool) deqEnabled <- mkRWire(); 44.163 + 44.164 + Reg#(Maybe#(item_t)) register <- mkReg(Invalid); 44.165 + 44.166 + // If there is an input item on the inputWire wire and dequeue did not 44.167 + // execute this cycle then we need to store the item in the register 44.168 + 44.169 + rule noDeq ( isValid(inputWire.wget()) && !isValid(deqEnabled.wget()) ); 44.170 + register <= inputWire.wget(); 44.171 + endrule 44.172 + 44.173 + // On enqueue we write the input item to the inputWire wire 44.174 + 44.175 + method Action enq( item_t item ) if ( !isValid(register) ); 44.176 + inputWire.wset(item); 44.177 + endmethod 44.178 + 44.179 + // On dequeue we always invalidate the storage register regardless 44.180 + // of whether or not the item was actually bypassed or not. We also 44.181 + // set a combinational signal so that we know not to move the item 44.182 + // into the register this cycle. 44.183 + 44.184 + method Action deq() if ( isValid(register) || isValid(inputWire.wget()) ); 44.185 + register <= Invalid; 44.186 + deqEnabled.wset(True); 44.187 + endmethod 44.188 + 44.189 + // We get the item either from the register (if register is valid) or 44.190 + // from the combinational bypasss (if the rwire is valid). 44.191 + 44.192 + method item_t first() if ( isValid(register) || isValid(inputWire.wget()) ); 44.193 + if ( isValid(register) ) 44.194 + return unJust(register); 44.195 + else 44.196 + return unJust(inputWire.wget()); 44.197 + endmethod 44.198 + 44.199 + // FIFOF adds the following two methods 44.200 + 44.201 + method Bool notFull(); 44.202 + return !isValid(register); 44.203 + endmethod 44.204 + 44.205 + method Bool notEmpty(); 44.206 + return (isValid(register) || isValid(inputWire.wget())); 44.207 + endmethod 44.208 + 44.209 + // Not sure about the clear method ... 44.210 + 44.211 + method Action clear(); 44.212 + dynamicAssert( False, "BFIFO.clear() not implemented yet!" ); 44.213 + endmethod 44.214 + 44.215 +endmodule 44.216 + 44.217 +(* synthesize *) 44.218 +module mkBFIFO_16 (FIFO#(Bit#(16))); 44.219 + 44.220 + let f <- mkBFIFO1(); 44.221 + 44.222 + return f; 44.223 + 44.224 +endmodule 44.225 +
45.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 45.2 +++ b/core/src/BRegFile.bsv Tue Apr 13 17:34:33 2010 -0400 45.3 @@ -0,0 +1,36 @@ 45.4 +import RegFile::*; 45.5 +import RWire::*; 45.6 +import ProcTypes::*; 45.7 + 45.8 +//----------------------------------------------------------- 45.9 +// Register file module 45.10 +//----------------------------------------------------------- 45.11 + 45.12 +interface BRegFile #(type index_t, type data_t); 45.13 + method Action upd(index_t addr, data_t data); 45.14 + method data_t sub(index_t addr); 45.15 +endinterface 45.16 + 45.17 +module mkBRegFile(RegFile#(index_t, data_t)) 45.18 + provisos (Bits#(index_t, size_index), 45.19 + Bits#(data_t, size_data), 45.20 + Eq#(index_t), 45.21 + Bounded#(index_t) ); 45.22 + 45.23 + RegFile#(index_t, data_t) rf <- mkRegFileWCF(minBound, maxBound); 45.24 + RWire#(Tuple2#(index_t, data_t)) rw <-mkRWire(); 45.25 + 45.26 + method Action upd (index_t r, data_t d); 45.27 + rf.upd(r,d); 45.28 + rw.wset(tuple2(r,d)); 45.29 + endmethod 45.30 + 45.31 + method data_t sub (index_t r); 45.32 + case (rw.wget()) matches 45.33 + tagged Valid {.wr, .d} : 45.34 + return (wr == r) ? d : rf.sub(r); 45.35 + tagged Invalid : return rf.sub(r); 45.36 + endcase 45.37 + endmethod 45.38 + 45.39 +endmodule
46.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 46.2 +++ b/core/src/BranchPred.bsv Tue Apr 13 17:34:33 2010 -0400 46.3 @@ -0,0 +1,41 @@ 46.4 +import RegFile::*; 46.5 +import ProcTypes::*; 46.6 +import FIFO::*; 46.7 + 46.8 +typedef Maybe#(Addr) BrPred; 46.9 +typedef Bit#(4) BPindx; 46.10 + 46.11 +typedef struct {Addr brpc; Addr nextpc;} BrPair deriving (Bits,Eq); 46.12 + 46.13 +typedef union tagged 46.14 +{ 46.15 + BrPair Valid; 46.16 + void Invalid; 46.17 +} CBranchPath deriving(Bits, Eq); // have the cache start out invalid and add valid values. 46.18 + 46.19 +interface BranchPred; 46.20 + method BrPred get(Addr pres); //returns a maybe type that is invalid if no predition 46.21 + method Action upd(Addr pres, Addr next); 46.22 +endinterface 46.23 + 46.24 +module mkBranchPred(BranchPred); 46.25 + 46.26 + //state variables 46.27 + RegFile#(BPindx, CBranchPath) bcache <- mkRegFileFull(); // cache to hold 16 (based on BPindx) 46.28 + 46.29 + method Action upd(Addr pres, Addr next); 46.30 + BrPair brp; 46.31 + brp = BrPair {brpc:pres, nextpc:next}; 46.32 + bcache.upd(pres[5:2], tagged Valid brp); 46.33 + endmethod 46.34 + 46.35 + method BrPred get(Addr prespc); 46.36 + BPindx rd = prespc[5:2]; 46.37 + let cbp = bcache.sub(rd); 46.38 + if (cbp matches tagged Valid .bp &&& bp.brpc == prespc) //make sure that the read value was actually put there and the full address matches 46.39 + return tagged Valid bp.nextpc; 46.40 + else return Invalid; 46.41 + endmethod 46.42 + 46.43 +endmodule 46.44 +
47.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 47.2 +++ b/core/src/Core.bsv Tue Apr 13 17:34:33 2010 -0400 47.3 @@ -0,0 +1,81 @@ 47.4 +// The MIT License 47.5 + 47.6 +// Copyright (c) 2009 Massachusetts Institute of Technology 47.7 + 47.8 +// Permission is hereby granted, free of charge, to any person obtaining a copy 47.9 +// of this software and associated documentation files (the "Software"), to deal 47.10 +// in the Software without restriction, including without limitation the rights 47.11 +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 47.12 +// copies of the Software, and to permit persons to whom the Software is 47.13 +// furnished to do so, subject to the following conditions: 47.14 + 47.15 +// The above copyright notice and this permission notice shall be included in 47.16 +// all copies or substantial portions of the Software. 47.17 + 47.18 +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 47.19 +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 47.20 +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 47.21 +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 47.22 +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 47.23 +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 47.24 +// THE SOFTWARE. 47.25 + 47.26 +import Connectable::*; 47.27 +import GetPut::*; 47.28 +import ClientServer::*; 47.29 + 47.30 +import DataCacheBlocking::*; 47.31 +import InstCacheBlocking::*; 47.32 +import Processor::*; 47.33 +import MemArb::*; 47.34 +import MemTypes::*; 47.35 + 47.36 +interface CoreStats; 47.37 + interface DCacheStats dcache; 47.38 + interface ICacheStats icache; 47.39 + interface ProcStats proc; 47.40 +endinterface 47.41 + 47.42 +interface Core; 47.43 + 47.44 + // Interface from core to main memory 47.45 + interface Client#(MainMemReq,MainMemResp) mmem_client; 47.46 + 47.47 + // Statistics 47.48 + interface CoreStats stats; 47.49 + 47.50 + // CPU to Host 47.51 + interface CPUToHost tohost; 47.52 + 47.53 +endinterface 47.54 + 47.55 +(* synthesize *) 47.56 +module mkCore(Core); 47.57 + 47.58 + // Instantiate the modules 47.59 + Proc proc <- mkProc(); 47.60 + ICache#(InstReq,InstResp) icache <- mkInstCache(); 47.61 + DCache#(DataReq,DataResp) dcache <- mkDataCache(); 47.62 + MemArb marb <- mkMemArb(); 47.63 + 47.64 + // Internal connections 47.65 + mkConnection( proc.statsEn_get, icache.statsEn_put ); 47.66 + mkConnection( proc.statsEn_get, dcache.statsEn_put ); 47.67 + mkConnection( proc.imem_client, icache.proc_server ); 47.68 + mkConnection( proc.dmem_client, dcache.proc_server ); 47.69 + mkConnection( icache.mmem_client, marb.cache0_server ); 47.70 + mkConnection( dcache.mmem_client, marb.cache1_server ); 47.71 + 47.72 + // Methods 47.73 + interface mmem_client = marb.mmem_client; 47.74 + 47.75 + interface CoreStats stats; 47.76 + interface dcache = dcache.stats; 47.77 + interface icache = icache.stats; 47.78 + interface proc = proc.stats; 47.79 + endinterface 47.80 + 47.81 + interface CPUToHost tohost = proc.tohost; 47.82 + 47.83 +endmodule 47.84 +
48.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 48.2 +++ b/core/src/DataCacheBlocking.bsv Tue Apr 13 17:34:33 2010 -0400 48.3 @@ -0,0 +1,295 @@ 48.4 +// The MIT License 48.5 + 48.6 +// Copyright (c) 2009 Massachusetts Institute of Technology 48.7 + 48.8 +// Permission is hereby granted, free of charge, to any person obtaining a copy 48.9 +// of this software and associated documentation files (the "Software"), to deal 48.10 +// in the Software without restriction, including without limitation the rights 48.11 +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 48.12 +// copies of the Software, and to permit persons to whom the Software is 48.13 +// furnished to do so, subject to the following conditions: 48.14 + 48.15 +// The above copyright notice and this permission notice shall be included in 48.16 +// all copies or substantial portions of the Software. 48.17 + 48.18 +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 48.19 +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 48.20 +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 48.21 +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 48.22 +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 48.23 +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 48.24 +// THE SOFTWARE. 48.25 + 48.26 +import Connectable::*; 48.27 +import GetPut::*; 48.28 +import ClientServer::*; 48.29 +import RegFile::*; 48.30 +import FIFO::*; 48.31 +import FIFOF::*; 48.32 + 48.33 +import BFIFO::*; 48.34 +import MemTypes::*; 48.35 +import ProcTypes::*; 48.36 +import Trace::*; 48.37 + 48.38 +interface DCacheStats; 48.39 + interface Get#(Stat) num_accesses; 48.40 + interface Get#(Stat) num_misses; 48.41 + interface Get#(Stat) num_writebacks; 48.42 +endinterface 48.43 + 48.44 +interface DCache#( type req_t, type resp_t ); 48.45 + 48.46 + // Interface from processor to cache 48.47 + interface Server#(req_t,resp_t) proc_server; 48.48 + 48.49 + // Interface from cache to main memory 48.50 + interface Client#(MainMemReq,MainMemResp) mmem_client; 48.51 + 48.52 + // Interface for enabling/disabling statistics 48.53 + interface Put#(Bool) statsEn_put; 48.54 + 48.55 + // Interface for collecting statistics 48.56 + interface DCacheStats stats; 48.57 + 48.58 +endinterface 48.59 + 48.60 + 48.61 +//---------------------------------------------------------------------- 48.62 +// Cache Types 48.63 +//---------------------------------------------------------------------- 48.64 + 48.65 +typedef 10 CacheLineIndexSz; 48.66 +typedef 20 CacheLineTagSz; 48.67 +typedef 32 CacheLineSz; 48.68 + 48.69 +typedef Bit#(CacheLineIndexSz) CacheLineIndex; 48.70 +typedef Bit#(CacheLineTagSz) CacheLineTag; 48.71 +typedef Bit#(CacheLineSz) CacheLine; 48.72 + 48.73 +typedef enum 48.74 +{ 48.75 + Init, 48.76 + Access, 48.77 + RefillReq, 48.78 + RefillResp 48.79 +} 48.80 +CacheStage 48.81 +deriving (Eq,Bits); 48.82 + 48.83 +//---------------------------------------------------------------------- 48.84 +// Helper functions 48.85 +//---------------------------------------------------------------------- 48.86 + 48.87 +function Bit#(AddrSz) getAddr( DataReq req ); 48.88 + 48.89 + Bit#(AddrSz) addr = ?; 48.90 + case ( req ) matches 48.91 + tagged LoadReq .ld : addr = ld.addr; 48.92 + tagged StoreReq .st : addr = st.addr; 48.93 + endcase 48.94 + 48.95 + return addr; 48.96 + 48.97 +endfunction 48.98 + 48.99 +function CacheLineIndex getCacheLineIndex( DataReq req ); 48.100 + Bit#(AddrSz) addr = getAddr(req); 48.101 + Bit#(CacheLineIndexSz) index = truncate( addr >> 2 ); 48.102 + return index; 48.103 +endfunction 48.104 + 48.105 +function CacheLineTag getCacheLineTag( DataReq req ); 48.106 + Bit#(AddrSz) addr = getAddr(req); 48.107 + Bit#(CacheLineTagSz) tag = truncate( addr >> fromInteger(valueOf(CacheLineIndexSz)) >> 2 ); 48.108 + return tag; 48.109 +endfunction 48.110 + 48.111 +function Bit#(AddrSz) getCacheLineAddr( DataReq req ); 48.112 + Bit#(AddrSz) addr = getAddr(req); 48.113 + return ((addr >> 2) << 2); 48.114 +endfunction 48.115 + 48.116 +//---------------------------------------------------------------------- 48.117 +// Main module 48.118 +//---------------------------------------------------------------------- 48.119 + 48.120 +(* doc = "synthesis attribute ram_style mkDataCache distributed;" *) 48.121 +(* synthesize *) 48.122 +module mkDataCache( DCache#(DataReq,DataResp) ); 48.123 + 48.124 + //----------------------------------------------------------- 48.125 + // State 48.126 + 48.127 + Reg#(CacheStage) stage <- mkReg(Init); 48.128 + 48.129 + RegFile#(CacheLineIndex,Maybe#(CacheLineTag)) cacheTagRam <- mkRegFileFull(); 48.130 + RegFile#(CacheLineIndex,CacheLine) cacheDataRam <- mkRegFileFull(); 48.131 + 48.132 + FIFO#(DataReq) reqQ <- mkFIFO(); 48.133 + FIFOF#(DataResp) respQ <- mkBFIFOF1(); 48.134 + 48.135 + FIFO#(MainMemReq) mainMemReqQ <- mkBFIFO1(); 48.136 + FIFO#(MainMemResp) mainMemRespQ <- mkFIFO(); 48.137 + 48.138 + Reg#(CacheLineIndex) initCounter <- mkReg(1); 48.139 + 48.140 + // Statistics state 48.141 + 48.142 + Reg#(Bool) statsEn <- mkReg(False); 48.143 + 48.144 + Reg#(Stat) num_accesses <- mkReg(0); 48.145 + Reg#(Stat) num_misses <- mkReg(0); 48.146 + Reg#(Stat) num_writebacks <- mkReg(0); 48.147 + 48.148 + //----------------------------------------------------------- 48.149 + // Name some wires 48.150 + 48.151 + let req = reqQ.first(); 48.152 + let reqIndex = getCacheLineIndex(req); 48.153 + let reqTag = getCacheLineTag(req); 48.154 + let reqCacheLineAddr = getCacheLineAddr(req); 48.155 + 48.156 + //----------------------------------------------------------- 48.157 + // Initialize 48.158 + 48.159 + rule init ( stage == Init ); 48.160 + traceTiny("mkDataCacheBlocking", "stage","i"); 48.161 + initCounter <= initCounter + 1; 48.162 + cacheTagRam.upd(initCounter,Invalid); 48.163 + if ( initCounter == 0 ) 48.164 + stage <= Access; 48.165 + endrule 48.166 + 48.167 + //----------------------------------------------------------- 48.168 + // Access cache rule 48.169 + 48.170 + rule access ( (stage == Access) && respQ.notFull() ); 48.171 + 48.172 + // Statistics 48.173 + 48.174 + if ( statsEn ) 48.175 + num_accesses <= num_accesses + 1; 48.176 + 48.177 + 48.178 + // Get the corresponding tag from the rams 48.179 + 48.180 + Maybe#(CacheLineTag) cacheLineTag = cacheTagRam.sub(reqIndex); 48.181 + 48.182 + // Handle cache hits ... 48.183 + 48.184 + if ( isValid(cacheLineTag) && ( unJust(cacheLineTag) == reqTag ) ) 48.185 + begin 48.186 + traceTiny("mkDataCacheBlocking", "hitMiss","h"); 48.187 + reqQ.deq(); 48.188 + 48.189 + case ( req ) matches 48.190 + 48.191 + tagged LoadReq .ld : 48.192 + respQ.enq( LoadResp { tag: ld.tag, data: cacheDataRam.sub(reqIndex) } ); 48.193 + 48.194 + tagged StoreReq .st : 48.195 + begin 48.196 + respQ.enq( StoreResp { tag : st.tag } ); 48.197 + cacheDataRam.upd(reqIndex,st.data); 48.198 + end 48.199 + 48.200 + endcase 48.201 + 48.202 + end 48.203 + 48.204 + // Handle cache misses ... 48.205 + 48.206 + else 48.207 + begin 48.208 + traceTiny("mkDataCacheBlocking", "hitMiss","m"); 48.209 + if ( statsEn ) 48.210 + num_misses <= num_misses + 1; 48.211 + 48.212 + // Currently we don't use dirty bits so we always writeback the data if it is valid 48.213 + 48.214 + if ( isValid(cacheLineTag) ) 48.215 + begin 48.216 + 48.217 + if ( statsEn ) 48.218 + num_writebacks <= num_writebacks + 1; 48.219 + 48.220 + MainMemReq wbReq 48.221 + = StoreReq { tag : 0, 48.222 + addr : { unJust(cacheLineTag), reqIndex, 2'b0 }, 48.223 + data : cacheDataRam.sub(reqIndex) }; 48.224 + 48.225 + mainMemReqQ.enq(wbReq); 48.226 + stage <= RefillReq; 48.227 + end 48.228 + 48.229 + // Otherwise we can issue the refill request now 48.230 + 48.231 + else 48.232 + begin 48.233 + mainMemReqQ.enq( LoadReq { tag: 0, addr: reqCacheLineAddr } ); 48.234 + stage <= RefillResp; 48.235 + end 48.236 + 48.237 + end 48.238 + 48.239 + endrule 48.240 + 48.241 + //----------------------------------------------------------- 48.242 + // Refill request rule 48.243 + 48.244 + rule refillReq ( stage == RefillReq ); 48.245 + traceTiny("mkDataCacheBlocking", "stage","r"); 48.246 + mainMemReqQ.enq( LoadReq { tag: 0, addr: reqCacheLineAddr } ); 48.247 + stage <= RefillResp; 48.248 + endrule 48.249 + 48.250 + //----------------------------------------------------------- 48.251 + // Refill response rule 48.252 + 48.253 + rule refillResp ( stage == RefillResp ); 48.254 + traceTiny("mkDataCacheBlocking", "stage","R"); 48.255 + traceTiny("mkDataCacheBlocking", "refill",mainMemRespQ.first()); 48.256 + 48.257 + // Write the new data into the cache and update the tag 48.258 + 48.259 + mainMemRespQ.deq(); 48.260 + case ( mainMemRespQ.first() ) matches 48.261 + 48.262 + tagged LoadResp .ld : 48.263 + begin 48.264 + cacheTagRam.upd(reqIndex,Valid(reqTag)); 48.265 + cacheDataRam.upd(reqIndex,ld.data); 48.266 + end 48.267 + 48.268 + tagged StoreResp .st : 48.269 + noAction; 48.270 + 48.271 + endcase 48.272 + 48.273 + stage <= Access; 48.274 + endrule 48.275 + 48.276 + //----------------------------------------------------------- 48.277 + // Methods 48.278 + 48.279 + interface Client mmem_client; 48.280 + interface Get request = toGet(mainMemReqQ); 48.281 + interface Put response = toPut(mainMemRespQ); 48.282 + endinterface 48.283 + 48.284 + interface Server proc_server; 48.285 + interface Put request = tracePut("mkDataCacheBlocking", "reqTiny",toPut(reqQ)); 48.286 + interface Get response = traceGet("mkDataCacheBlocking", "respTiny",toGet(respQ)); 48.287 + endinterface 48.288 + 48.289 + interface Put statsEn_put = toPut(asReg(statsEn)); 48.290 + 48.291 + interface DCacheStats stats; 48.292 + interface Get num_accesses = toGet(asReg(num_accesses)); 48.293 + interface Get num_misses = toGet(asReg(num_misses)); 48.294 + interface Get num_writebacks = toGet(asReg(num_writebacks)); 48.295 + endinterface 48.296 + 48.297 +endmodule 48.298 +
49.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 49.2 +++ b/core/src/InstCacheBlocking.bsv Tue Apr 13 17:34:33 2010 -0400 49.3 @@ -0,0 +1,269 @@ 49.4 +// The MIT License 49.5 + 49.6 +// Copyright (c) 2009 Massachusetts Institute of Technology 49.7 + 49.8 +// Permission is hereby granted, free of charge, to any person obtaining a copy 49.9 +// of this software and associated documentation files (the "Software"), to deal 49.10 +// in the Software without restriction, including without limitation the rights 49.11 +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 49.12 +// copies of the Software, and to permit persons to whom the Software is 49.13 +// furnished to do so, subject to the following conditions: 49.14 + 49.15 +// The above copyright notice and this permission notice shall be included in 49.16 +// all copies or substantial portions of the Software. 49.17 + 49.18 +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 49.19 +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 49.20 +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 49.21 +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 49.22 +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 49.23 +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 49.24 +// THE SOFTWARE. 49.25 + 49.26 +import Connectable::*; 49.27 +import GetPut::*; 49.28 +import ClientServer::*; 49.29 +import RegFile::*; 49.30 +import FIFO::*; 49.31 +import FIFOF::*; 49.32 +import RWire::*; 49.33 + 49.34 +import BFIFO::*; 49.35 +import MemTypes::*; 49.36 +import ProcTypes::*; 49.37 +import Trace::*; 49.38 + 49.39 +interface ICacheStats; 49.40 + interface Get#(Stat) num_accesses; 49.41 + interface Get#(Stat) num_misses; 49.42 + interface Get#(Stat) num_evictions; 49.43 +endinterface 49.44 + 49.45 +interface ICache#( type req_t, type resp_t ); 49.46 + 49.47 + // Interface from processor to cache 49.48 + interface Server#(req_t,resp_t) proc_server; 49.49 + 49.50 + // Interface from cache to main memory 49.51 + interface Client#(MainMemReq,MainMemResp) mmem_client; 49.52 + 49.53 + // Interface for enabling/disabling statistics 49.54 + interface Put#(Bool) statsEn_put; 49.55 + 49.56 + // Interface for collecting statistics 49.57 + interface ICacheStats stats; 49.58 + 49.59 +endinterface 49.60 + 49.61 +//---------------------------------------------------------------------- 49.62 +// Cache Types 49.63 +//---------------------------------------------------------------------- 49.64 + 49.65 +typedef 10 CacheLineIndexSz; 49.66 +typedef 20 CacheLineTagSz; 49.67 +typedef 32 CacheLineSz; 49.68 + 49.69 +typedef Bit#(CacheLineIndexSz) CacheLineIndex; 49.70 +typedef Bit#(CacheLineTagSz) CacheLineTag; 49.71 +typedef Bit#(CacheLineSz) CacheLine; 49.72 + 49.73 +typedef enum 49.74 +{ 49.75 + Init, 49.76 + Access, 49.77 + Evict, 49.78 + RefillReq, 49.79 + RefillResp 49.80 +} 49.81 +CacheStage 49.82 +deriving (Eq,Bits); 49.83 + 49.84 +//---------------------------------------------------------------------- 49.85 +// Helper functions 49.86 +//---------------------------------------------------------------------- 49.87 + 49.88 +function Bit#(AddrSz) getAddr( InstReq req ); 49.89 + 49.90 + Bit#(AddrSz) addr = ?; 49.91 + case ( req ) matches 49.92 + tagged LoadReq .ld : addr = ld.addr; 49.93 + tagged StoreReq .st : addr = st.addr; 49.94 + endcase 49.95 + 49.96 + return addr; 49.97 + 49.98 +endfunction 49.99 + 49.100 +function CacheLineIndex getCacheLineIndex( InstReq req ); 49.101 + Bit#(AddrSz) addr = getAddr(req); 49.102 + Bit#(CacheLineIndexSz) index = truncate( addr >> 2 ); 49.103 + return index; 49.104 +endfunction 49.105 + 49.106 +function CacheLineTag getCacheLineTag( InstReq req ); 49.107 + Bit#(AddrSz) addr = getAddr(req); 49.108 + Bit#(CacheLineTagSz) tag = truncate( addr >> fromInteger(valueOf(CacheLineIndexSz)) >> 2 ); 49.109 + return tag; 49.110 +endfunction 49.111 + 49.112 +function Bit#(AddrSz) getCacheLineAddr( InstReq req ); 49.113 + Bit#(AddrSz) addr = getAddr(req); 49.114 + return ((addr >> 2) << 2); 49.115 +endfunction 49.116 + 49.117 +//---------------------------------------------------------------------- 49.118 +// Main module 49.119 +//---------------------------------------------------------------------- 49.120 + 49.121 +(* doc = "synthesis attribute ram_style mkInstCache distributed;" *) 49.122 +(* synthesize *) 49.123 +module mkInstCache( ICache#(InstReq,InstResp) ); 49.124 + 49.125 + //----------------------------------------------------------- 49.126 + // State 49.127 + 49.128 + Reg#(CacheStage) stage <- mkReg(Init); 49.129 + 49.130 + RegFile#(CacheLineIndex,Maybe#(CacheLineTag)) cacheTagRam <- mkRegFileFull(); 49.131 + RegFile#(CacheLineIndex,CacheLine) cacheDataRam <- mkRegFileFull(); 49.132 + 49.133 + FIFO#(InstReq) reqQ <- mkFIFO(); 49.134 + FIFOF#(InstResp) respQ <- mkBFIFOF1(); 49.135 + 49.136 + FIFO#(MainMemReq) mainMemReqQ <- mkBFIFO1(); 49.137 + FIFO#(MainMemResp) mainMemRespQ <- mkFIFO(); 49.138 + 49.139 + Reg#(CacheLineIndex) initCounter <- mkReg(1); 49.140 + 49.141 + // Statistics state 49.142 + 49.143 + Reg#(Bool) statsEn <- mkReg(False); 49.144 + 49.145 + Reg#(Stat) numAccesses <- mkReg(0); 49.146 + Reg#(Stat) numMisses <- mkReg(0); 49.147 + Reg#(Stat) numEvictions <- mkReg(0); 49.148 + 49.149 + //----------------------------------------------------------- 49.150 + // Name some wires 49.151 + 49.152 + let req = reqQ.first(); 49.153 + let reqIndex = getCacheLineIndex(req); 49.154 + let reqTag = getCacheLineTag(req); 49.155 + let reqCacheLineAddr = getCacheLineAddr(req); 49.156 + let refill = mainMemRespQ.first(); 49.157 + 49.158 + //----------------------------------------------------------- 49.159 + // Initialize 49.160 + 49.161 + rule init ( stage == Init ); 49.162 + traceTiny("mkInstCacheBlocking", "stage","i"); 49.163 + initCounter <= initCounter + 1; 49.164 + cacheTagRam.upd(initCounter,Invalid); 49.165 + if ( initCounter == 0 ) 49.166 + stage <= Access; 49.167 + endrule 49.168 + 49.169 + //----------------------------------------------------------- 49.170 + // Cache access rule 49.171 + 49.172 + rule access ( (stage == Access) && respQ.notFull() ); 49.173 + 49.174 + // Statistics 49.175 + 49.176 + if ( statsEn ) 49.177 + numAccesses <= numAccesses + 1; 49.178 + 49.179 + // Check tag and valid bit to see if this is a hit or a miss 49.180 + 49.181 + Maybe#(CacheLineTag) cacheLineTag = cacheTagRam.sub(reqIndex); 49.182 + 49.183 + // Handle cache hits ... 49.184 + 49.185 + if ( isValid(cacheLineTag) && ( unJust(cacheLineTag) == reqTag ) ) 49.186 + begin 49.187 + traceTiny("mkInstCacheBlocking", "hitMiss","h"); 49.188 + reqQ.deq(); 49.189 + 49.190 + case ( req ) matches 49.191 + 49.192 + tagged LoadReq .ld : 49.193 + respQ.enq( LoadResp { tag : ld.tag, data : cacheDataRam.sub(reqIndex) } ); 49.194 + 49.195 + tagged StoreReq .st : 49.196 + $display( " RTL-ERROR : %m : Stores are not allowed on the inst port!" ); 49.197 + 49.198 + endcase 49.199 + 49.200 + end 49.201 + 49.202 + // Handle cache misses - since lines in instruction cache are 49.203 + // never dirty we can always immediately issue a refill request 49.204 + 49.205 + else 49.206 + begin 49.207 + traceTiny("mkInstCacheBlocking", "hitMiss","m"); 49.208 + if ( statsEn ) 49.209 + numMisses <= numMisses + 1; 49.210 + if ( statsEn ) 49.211 + if ( isJust(cacheLineTag) ) 49.212 + numEvictions <= numEvictions + 1; 49.213 + 49.214 + MainMemReq rfReq 49.215 + = LoadReq { tag : 0, 49.216 + addr : reqCacheLineAddr }; 49.217 + 49.218 + mainMemReqQ.enq(rfReq); 49.219 + stage <= RefillResp; 49.220 + end 49.221 + 49.222 + endrule 49.223 + 49.224 + //----------------------------------------------------------- 49.225 + // Refill response rule 49.226 + 49.227 + rule refillResp ( stage == RefillResp ); 49.228 + traceTiny("mkInstCacheBlocking", "stage","R"); 49.229 + traceTiny("mkInstCacheBlocking", "refill",refill); 49.230 + 49.231 + // Write the new data into the cache and update the tag 49.232 + 49.233 + mainMemRespQ.deq(); 49.234 + case ( mainMemRespQ.first() ) matches 49.235 + 49.236 + tagged LoadResp .ld : 49.237 + begin 49.238 + cacheTagRam.upd(reqIndex,Valid(reqTag)); 49.239 + cacheDataRam.upd(reqIndex,ld.data); 49.240 + end 49.241 + 49.242 + tagged StoreResp .st : 49.243 + noAction; 49.244 + 49.245 + endcase 49.246 + 49.247 + stage <= Access; 49.248 + endrule 49.249 + 49.250 + //----------------------------------------------------------- 49.251 + // Methods 49.252 + 49.253 + interface Client mmem_client; 49.254 + interface Get request = fifoToGet(mainMemReqQ); 49.255 + interface Put response = fifoToPut(mainMemRespQ); 49.256 + endinterface 49.257 + 49.258 + interface Server proc_server; 49.259 + interface Put request = tracePut("mkInstCacheBlocking", "reqTiny",toPut(reqQ)); 49.260 + interface Get response = traceGet("mkInstCacheBlocking", "respTiny",toGet(respQ)); 49.261 + endinterface 49.262 + 49.263 + interface Put statsEn_put = toPut(asReg(statsEn)); 49.264 + 49.265 + interface ICacheStats stats; 49.266 + interface Get num_accesses = toGet(asReg(numAccesses)); 49.267 + interface Get num_misses = toGet(asReg(numMisses)); 49.268 + interface Get num_evictions = toGet(asReg(numEvictions)); 49.269 + endinterface 49.270 + 49.271 +endmodule 49.272 +
50.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 50.2 +++ b/core/src/MemArb.bsv Tue Apr 13 17:34:33 2010 -0400 50.3 @@ -0,0 +1,141 @@ 50.4 +// The MIT License 50.5 + 50.6 +// Copyright (c) 2009 Massachusetts Institute of Technology 50.7 + 50.8 +// Permission is hereby granted, free of charge, to any person obtaining a copy 50.9 +// of this software and associated documentation files (the "Software"), to deal 50.10 +// in the Software without restriction, including without limitation the rights 50.11 +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 50.12 +// copies of the Software, and to permit persons to whom the Software is 50.13 +// furnished to do so, subject to the following conditions: 50.14 + 50.15 +// The above copyright notice and this permission notice shall be included in 50.16 +// all copies or substantial portions of the Software. 50.17 + 50.18 +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 50.19 +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 50.20 +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 50.21 +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 50.22 +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 50.23 +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 50.24 +// THE SOFTWARE. 50.25 + 50.26 +import Connectable::*; 50.27 +import GetPut::*; 50.28 +import ClientServer::*; 50.29 +import FIFOF::*; 50.30 +import FIFO::*; 50.31 + 50.32 +import BFIFO::*; 50.33 +import MemTypes::*; 50.34 +import Trace::*; 50.35 + 50.36 +interface MemArb; 50.37 + 50.38 + interface Server#(MainMemReq,MainMemResp) cache0_server; 50.39 + interface Server#(MainMemReq,MainMemResp) cache1_server; 50.40 + interface Client#(MainMemReq,MainMemResp) mmem_client; 50.41 + 50.42 +endinterface 50.43 + 50.44 +typedef enum { REQ0, REQ1 } ReqPtr deriving(Eq,Bits); 50.45 + 50.46 +(* synthesize *) 50.47 +module mkMemArb( MemArb ); 50.48 + 50.49 + //----------------------------------------------------------- 50.50 + // State 50.51 + 50.52 + FIFOF#(MainMemReq) req0Q <- mkFIFOF1(); 50.53 + FIFO#(MainMemResp) resp0Q <- mkFIFO1(); 50.54 + 50.55 + FIFOF#(MainMemReq) req1Q <- mkFIFOF1(); 50.56 + FIFO#(MainMemResp) resp1Q <- mkFIFO1(); 50.57 + 50.58 + FIFO#(MainMemReq) mreqQ <- mkFIFO1(); 50.59 + FIFO#(MainMemResp) mrespQ <- mkFIFO1(); 50.60 + 50.61 + Reg#(ReqPtr) nextReq <- mkReg(REQ0); 50.62 + 50.63 + //----------------------------------------------------------- 50.64 + // Some wires 50.65 + 50.66 + let req0avail = req0Q.notEmpty(); 50.67 + let req1avail = req1Q.notEmpty(); 50.68 + 50.69 + //----------------------------------------------------------- 50.70 + // Rules 50.71 + 50.72 + rule chooseReq0 ( req0avail && (!req1avail || (nextReq == REQ0)) ); 50.73 + traceTiny("mkMemArb", "memArb req0",req0Q.first()); 50.74 + 50.75 + // Rewrite tag field if this is a load ... 50.76 + MainMemReq mreq 50.77 + = case ( req0Q.first() ) matches 50.78 + tagged LoadReq .ld : return LoadReq { tag:0, addr:ld.addr }; 50.79 + tagged StoreReq .st : return req0Q.first(); 50.80 + endcase; 50.81 + 50.82 + // Send out the request 50.83 + mreqQ.enq(mreq); 50.84 + nextReq <= REQ1; 50.85 + req0Q.deq(); 50.86 + 50.87 + endrule 50.88 + 50.89 + rule chooseReq1 ( req1avail && (!req0avail || (nextReq == REQ1)) ); 50.90 + traceTiny("mkMemArb", "memArb req1",req1Q.first); 50.91 + 50.92 + // Rewrite tag field if this is a load ... 50.93 + MainMemReq mreq 50.94 + = case ( req1Q.first() ) matches 50.95 + tagged LoadReq .ld : return LoadReq { tag:1, addr:ld.addr }; 50.96 + tagged StoreReq .st : return req1Q.first(); 50.97 + endcase; 50.98 + 50.99 + // Send out the request 50.100 + mreqQ.enq(mreq); 50.101 + nextReq <= REQ0; 50.102 + req1Q.deq(); 50.103 + 50.104 + endrule 50.105 + 50.106 + rule returnResp; 50.107 + traceTiny("mkMemArb", "resp",mrespQ.first()); 50.108 + 50.109 + // Use tag to figure out where to send response 50.110 + mrespQ.deq(); 50.111 + let tag 50.112 + = case ( mrespQ.first() ) matches 50.113 + tagged LoadResp .ld : return ld.tag; 50.114 + tagged StoreResp .st : return st.tag; 50.115 + endcase; 50.116 + 50.117 + if ( tag == 0 ) 50.118 + resp0Q.enq(mrespQ.first()); 50.119 + else 50.120 + resp1Q.enq(mrespQ.first()); 50.121 + 50.122 + endrule 50.123 + 50.124 + //----------------------------------------------------------- 50.125 + // Methods 50.126 + 50.127 + interface Server cache0_server; 50.128 + interface Put request = toPut(req0Q); 50.129 + interface Get response = toGet(resp0Q); 50.130 + endinterface 50.131 + 50.132 + interface Server cache1_server; 50.133 + interface Put request = toPut(req1Q); 50.134 + interface Get response = toGet(resp1Q); 50.135 + endinterface 50.136 + 50.137 + interface Client mmem_client; 50.138 + interface Get request = toGet(mreqQ); 50.139 + interface Put response = toPut(mrespQ); 50.140 + endinterface 50.141 + 50.142 +endmodule 50.143 + 50.144 +
51.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 51.2 +++ b/core/src/MemTypes.bsv Tue Apr 13 17:34:33 2010 -0400 51.3 @@ -0,0 +1,93 @@ 51.4 + 51.5 +import Trace::*; 51.6 + 51.7 +//---------------------------------------------------------------------- 51.8 +// Basic memory requests and responses 51.9 +//---------------------------------------------------------------------- 51.10 + 51.11 +typedef union tagged 51.12 +{ 51.13 + struct { Bit#(addrSz) addr; Bit#(tagSz) tag; } LoadReq; 51.14 + struct { Bit#(addrSz) addr; Bit#(tagSz) tag; Bit#(dataSz) data; } StoreReq; 51.15 +} 51.16 +MemReq#( type addrSz, type tagSz, type dataSz ) 51.17 +deriving(Eq,Bits); 51.18 + 51.19 +typedef union tagged 51.20 +{ 51.21 + struct { Bit#(tagSz) tag; Bit#(dataSz) data; } LoadResp; 51.22 + struct { Bit#(tagSz) tag; } StoreResp; 51.23 +} 51.24 +MemResp#( type tagSz, type dataSz ) 51.25 +deriving(Eq,Bits); 51.26 + 51.27 +//---------------------------------------------------------------------- 51.28 +// Specialized req/resp for inst/data/host 51.29 +//---------------------------------------------------------------------- 51.30 + 51.31 +typedef 32 AddrSz; 51.32 +typedef 08 TagSz; 51.33 +typedef 32 DataSz; 51.34 +typedef 32 InstSz; 51.35 +typedef 32 HostDataSz; 51.36 + 51.37 +typedef MemReq#(AddrSz,TagSz,0) InstReq; 51.38 +typedef MemResp#(TagSz,InstSz) InstResp; 51.39 + 51.40 +typedef MemReq#(AddrSz,TagSz,DataSz) DataReq; 51.41 +typedef MemResp#(TagSz,DataSz) DataResp; 51.42 + 51.43 +typedef MemReq#(AddrSz,TagSz,HostDataSz) HostReq; 51.44 +typedef MemResp#(TagSz,HostDataSz) HostResp; 51.45 + 51.46 +//---------------------------------------------------------------------- 51.47 +// Specialized req/resp for main memory 51.48 +//---------------------------------------------------------------------- 51.49 + 51.50 +typedef 32 MainMemAddrSz; 51.51 +typedef 08 MainMemTagSz; 51.52 +typedef 32 MainMemDataSz; 51.53 + 51.54 +typedef MemReq#(MainMemAddrSz,MainMemTagSz,MainMemDataSz) MainMemReq; 51.55 +typedef MemResp#(MainMemTagSz,MainMemDataSz) MainMemResp; 51.56 + 51.57 +//---------------------------------------------------------------------- 51.58 +// Tracing Functions 51.59 +//---------------------------------------------------------------------- 51.60 + 51.61 +instance Traceable#(MemReq#(a,b,c)); 51.62 + 51.63 + function Action traceTiny( String loc, String ttag, MemReq#(a,b,c) req ); 51.64 + case ( req ) matches 51.65 + tagged LoadReq .ld : $fdisplay(stderr, " => %s:%s l%2x", loc, ttag, ld.tag ); 51.66 + tagged StoreReq .st : $fdisplay(stderr, " => %s:%s s%2x", loc, ttag, st.tag ); 51.67 + endcase 51.68 + endfunction 51.69 + 51.70 + function Action traceFull( String loc, String ttag, MemReq#(a,b,c) req ); 51.71 + case ( req ) matches 51.72 + tagged LoadReq .ld : $fdisplay(stderr, " => %s:%s Ld { addr=%x, tag=%x }", loc, ttag, ld.addr, ld.tag ); 51.73 + tagged StoreReq .st : $fdisplay(stderr, " => %s:%s St { addr=%x, tag=%x, data=%x }", loc, ttag, st.addr, st.tag, st.data ); 51.74 + endcase 51.75 + endfunction 51.76 + 51.77 +endinstance 51.78 + 51.79 +instance Traceable#(MemResp#(a,b)); 51.80 + 51.81 + function Action traceTiny( String loc, String ttag, MemResp#(a,b) resp ); 51.82 + case ( resp ) matches 51.83 + tagged LoadResp .ld : $fdisplay(stderr, " => %s:%s l%2x", loc, ttag, ld.tag ); 51.84 + tagged StoreResp .st : $fdisplay(stderr, " => %s:%s s%2x", loc, ttag, st.tag ); 51.85 + endcase 51.86 + endfunction 51.87 + 51.88 + function Action traceFull( String loc, String ttag, MemResp#(a,b) resp ); 51.89 + case ( resp ) matches 51.90 + tagged LoadResp .ld : $fdisplay(stderr, " => %s:%s Ld { tag=%x, data=%x }", loc, ttag, ld.tag, ld.data ); 51.91 + tagged StoreResp .st : $fdisplay(stderr, " => %s:%s St { tag=%x }", loc, ttag, st.tag ); 51.92 + endcase 51.93 + endfunction 51.94 + 51.95 +endinstance 51.96 +
52.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 52.2 +++ b/core/src/PathTypes.bsv Tue Apr 13 17:34:33 2010 -0400 52.3 @@ -0,0 +1,31 @@ 52.4 +import Trace::*; 52.5 +import Vector::*; 52.6 + 52.7 +`define MAX_VOICES 4 52.8 +`define MAX_CORES 16 52.9 +`define MAX_PATH_IDS 18 52.10 +`define MAX_PATH_LENGTH 8 52.11 + 52.12 +// The path is hardwired and so should never be stored in a register. Therefore int type rather than Bit type 52.13 + 52.14 +typedef Bit#(32) MemAddr; 52.15 +typedef Int#(TLog#(`MAX_PATH_IDS)) PathId; 52.16 + 52.17 +//The mixer is identified as PathId 0, path end is max 52.18 +PathId mixerId = 0; 52.19 +PathId endId = `MAX_CORES+1; 52.20 + 52.21 +// Path is array of path ids 52.22 +typedef Vector#(`MAX_PATH_LENGTH, PathId) CorePath; 52.23 +typedef struct 52.24 +{ 52.25 + MemAddr startAddr; 52.26 + CorePath route; 52.27 + } FullPath deriving(Eq, Bits); 52.28 + 52.29 +vector#(`MAX_VOICES, FullPath) routeTable; 52.30 +CorePath aroute = {1, 2}; 52.31 +routeTable = {{12, aroute},{1, aroute}}; 52.32 + 52.33 + 52.34 +
53.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 53.2 +++ b/core/src/ProcTypes.bsv Tue Apr 13 17:34:33 2010 -0400 53.3 @@ -0,0 +1,375 @@ 53.4 + 53.5 +import Trace::*; 53.6 + 53.7 +//---------------------------------------------------------------------- 53.8 +// Other typedefs 53.9 +//---------------------------------------------------------------------- 53.10 + 53.11 +typedef Bit#(32) Addr; 53.12 +typedef Int#(18) Stat; 53.13 + 53.14 +//---------------------------------------------------------------------- 53.15 +// Basic instruction type 53.16 +//---------------------------------------------------------------------- 53.17 + 53.18 +typedef Bit#(5) Rindx; 53.19 +typedef Bit#(16) Simm; 53.20 +typedef Bit#(16) Zimm; 53.21 +typedef Bit#(8) Epoch; 53.22 +typedef Bit#(5) Shamt; 53.23 +typedef Bit#(26) Target; 53.24 +typedef Bit#(5) CP0indx; 53.25 +typedef Bit#(32) Data; 53.26 + 53.27 +typedef enum 53.28 +{ 53.29 + Taken, 53.30 + NotTaken 53.31 +} 53.32 + Direction 53.33 + deriving(Bits,Eq); 53.34 + 53.35 + 53.36 +//---------------------------------------------------------------------- 53.37 +// Pipeline typedefs 53.38 +//---------------------------------------------------------------------- 53.39 + 53.40 +typedef union tagged 53.41 +{ 53.42 + Tuple2#(Rindx,Data) ALUWB; 53.43 + Rindx MemWB; 53.44 + Tuple2#(Rindx,Data) CoWB; 53.45 +} 53.46 + WritebackType 53.47 + deriving(Bits,Eq); 53.48 + 53.49 +//////////////////////// 53.50 +// I Add Writeback queue type 53.51 +//////////// 53.52 +typedef union tagged 53.53 +{ 53.54 + struct {Bit#(32) data; Rindx dest; } WB_ALU; 53.55 + Bit#(32) WB_Host; 53.56 + Rindx WB_Load; 53.57 + void WB_Store; 53.58 +} 53.59 +WBResult deriving(Eq, Bits); 53.60 + 53.61 +typedef struct{Addr qpc; Addr qnxtpc; Epoch qepoch;} PCStat deriving(Eq, Bits); 53.62 +//typedef struct{Addr qpc; Epoch qepoch;} PCStat deriving(Eq, Bits); 53.63 + 53.64 +typedef union tagged 53.65 +{ 53.66 + 53.67 + struct { Rindx rbase; Rindx rdst; Simm offset; } LW; 53.68 + struct { Rindx rbase; Rindx rsrc; Simm offset; } SW; 53.69 + 53.70 + struct { Rindx rsrc; Rindx rdst; Simm imm; } ADDIU; 53.71 + struct { Rindx rsrc; Rindx rdst; Simm imm; } SLTI; 53.72 + struct { Rindx rsrc; Rindx rdst; Simm imm; } SLTIU; 53.73 + struct { Rindx rsrc; Rindx rdst; Zimm imm; } ANDI; 53.74 + struct { Rindx rsrc; Rindx rdst; Zimm imm; } ORI; 53.75 + struct { Rindx rsrc; Rindx rdst; Zimm imm; } XORI; 53.76 + struct { Rindx rdst; Zimm imm; } LUI; 53.77 + 53.78 + struct { Rindx rsrc; Rindx rdst; Shamt shamt; } SLL; 53.79 + struct { Rindx rsrc; Rindx rdst; Shamt shamt; } SRL; 53.80 + struct { Rindx rsrc; Rindx rdst; Shamt shamt; } SRA; 53.81 + struct { Rindx rsrc; Rindx rdst; Rindx rshamt; } SLLV; 53.82 + struct { Rindx rsrc; Rindx rdst; Rindx rshamt; } SRLV; 53.83 + struct { Rindx rsrc; Rindx rdst; Rindx rshamt; } SRAV; 53.84 + struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } ADDU; 53.85 + struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } SUBU; 53.86 + struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } AND; 53.87 + struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } OR; 53.88 + struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } XOR; 53.89 + struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } NOR; 53.90 + struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } SLT; 53.91 + struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } SLTU; 53.92 + 53.93 + struct { Target target; } J; 53.94 + struct { Target target; } JAL; 53.95 + struct { Rindx rsrc; } JR; 53.96 + struct { Rindx rsrc; Rindx rdst; } JALR; 53.97 + struct { Rindx rsrc1; Rindx rsrc2; Simm offset; } BEQ; 53.98 + struct { Rindx rsrc1; Rindx rsrc2; Simm offset; } BNE; 53.99 + struct { Rindx rsrc; Simm offset; } BLEZ; 53.100 + struct { Rindx rsrc; Simm offset; } BGTZ; 53.101 + struct { Rindx rsrc; Simm offset; } BLTZ; 53.102 + struct { Rindx rsrc; Simm offset; } BGEZ; 53.103 + 53.104 + struct { Rindx rdst; CP0indx cop0src; } MFC0; 53.105 + struct { Rindx rsrc; CP0indx cop0dst; } MTC0; 53.106 + 53.107 + void ILLEGAL; 53.108 + 53.109 +} 53.110 +Instr deriving(Eq); 53.111 + 53.112 +//---------------------------------------------------------------------- 53.113 +// Pack and Unpack 53.114 +//---------------------------------------------------------------------- 53.115 + 53.116 +Bit#(6) opFUNC = 6'b000000; Bit#(6) fcSLL = 6'b000000; 53.117 +Bit#(6) opRT = 6'b000001; Bit#(6) fcSRL = 6'b000010; 53.118 +Bit#(6) opRS = 6'b010000; Bit#(6) fcSRA = 6'b000011; 53.119 + Bit#(6) fcSLLV = 6'b000100; 53.120 +Bit#(6) opLW = 6'b100011; Bit#(6) fcSRLV = 6'b000110; 53.121 +Bit#(6) opSW = 6'b101011; Bit#(6) fcSRAV = 6'b000111; 53.122 + Bit#(6) fcADDU = 6'b100001; 53.123 +Bit#(6) opADDIU = 6'b001001; Bit#(6) fcSUBU = 6'b100011; 53.124 +Bit#(6) opSLTI = 6'b001010; Bit#(6) fcAND = 6'b100100; 53.125 +Bit#(6) opSLTIU = 6'b001011; Bit#(6) fcOR = 6'b100101; 53.126 +Bit#(6) opANDI = 6'b001100; Bit#(6) fcXOR = 6'b100110; 53.127 +Bit#(6) opORI = 6'b001101; Bit#(6) fcNOR = 6'b100111; 53.128 +Bit#(6) opXORI = 6'b001110; Bit#(6) fcSLT = 6'b101010; 53.129 +Bit#(6) opLUI = 6'b001111; Bit#(6) fcSLTU = 6'b101011; 53.130 + 53.131 +Bit#(6) opJ = 6'b000010; 53.132 +Bit#(6) opJAL = 6'b000011; 53.133 +Bit#(6) fcJR = 6'b001000; 53.134 +Bit#(6) fcJALR = 6'b001001; 53.135 +Bit#(6) opBEQ = 6'b000100; 53.136 +Bit#(6) opBNE = 6'b000101; 53.137 +Bit#(6) opBLEZ = 6'b000110; 53.138 +Bit#(6) opBGTZ = 6'b000111; 53.139 +Bit#(5) rtBLTZ = 5'b00000; 53.140 +Bit#(5) rtBGEZ = 5'b00001; 53.141 + 53.142 +Bit#(5) rsMFC0 = 5'b00000; 53.143 +Bit#(5) rsMTC0 = 5'b00100; 53.144 + 53.145 +instance Bits#(Instr,32); 53.146 + 53.147 + // Pack Function 53.148 + 53.149 + function Bit#(32) pack( Instr instr ); 53.150 + 53.151 + case ( instr ) matches 53.152 + 53.153 + tagged LW .it : return { opLW, it.rbase, it.rdst, it.offset }; 53.154 + tagged SW .it : return { opSW, it.rbase, it.rsrc, it.offset }; 53.155 + 53.156 + tagged ADDIU .it : return { opADDIU, it.rsrc, it.rdst, it.imm }; 53.157 + tagged SLTI .it : return { opSLTI, it.rsrc, it.rdst, it.imm }; 53.158 + tagged SLTIU .it : return { opSLTIU, it.rsrc, it.rdst, it.imm }; 53.159 + tagged ANDI .it : return { opANDI, it.rsrc, it.rdst, it.imm }; 53.160 + tagged ORI .it : return { opORI, it.rsrc, it.rdst, it.imm }; 53.161 + tagged XORI .it : return { opXORI, it.rsrc, it.rdst, it.imm }; 53.162 + tagged LUI .it : return { opLUI, 5'b0, it.rdst, it.imm }; 53.163 + 53.164 + tagged SLL .it : return { opFUNC, 5'b0, it.rsrc, it.rdst, it.shamt, fcSLL }; 53.165 + tagged SRL .it : return { opFUNC, 5'b0, it.rsrc, it.rdst, it.shamt, fcSRL }; 53.166 + tagged SRA .it : return { opFUNC, 5'b0, it.rsrc, it.rdst, it.shamt, fcSRA }; 53.167 + 53.168 + tagged SLLV .it : return { opFUNC, it.rshamt, it.rsrc, it.rdst, 5'b0, fcSLLV }; 53.169 + tagged SRLV .it : return { opFUNC, it.rshamt, it.rsrc, it.rdst, 5'b0, fcSRLV }; 53.170 + tagged SRAV .it : return { opFUNC, it.rshamt, it.rsrc, it.rdst, 5'b0, fcSRAV }; 53.171 + 53.172 + tagged ADDU .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcADDU }; 53.173 + tagged SUBU .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcSUBU }; 53.174 + tagged AND .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcAND }; 53.175 + tagged OR .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcOR }; 53.176 + tagged XOR .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcXOR }; 53.177 + tagged NOR .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcNOR }; 53.178 + tagged SLT .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcSLT }; 53.179 + tagged SLTU .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcSLTU }; 53.180 + 53.181 + tagged J .it : return { opJ, it.target }; 53.182 + tagged JAL .it : return { opJAL, it.target }; 53.183 + tagged JR .it : return { opFUNC, it.rsrc, 5'b0, 5'b0, 5'b0, fcJR }; 53.184 + tagged JALR .it : return { opFUNC, it.rsrc, 5'b0, it.rdst, 5'b0, fcJALR }; 53.185 + tagged BEQ .it : return { opBEQ, it.rsrc1, it.rsrc2, it.offset }; 53.186 + tagged BNE .it : return { opBNE, it.rsrc1, it.rsrc2, it.offset }; 53.187 + tagged BLEZ .it : return { opBLEZ, it.rsrc, 5'b0, it.offset }; 53.188 + tagged BGTZ .it : return { opBGTZ, it.rsrc, 5'b0, it.offset }; 53.189 + tagged BLTZ .it : return { opRT, it.rsrc, rtBLTZ, it.offset }; 53.190 + tagged BGEZ .it : return { opRT, it.rsrc, rtBGEZ, it.offset }; 53.191 + 53.192 + tagged MFC0 .it : return { opRS, rsMFC0, it.rdst, it.cop0src, 11'b0 }; 53.193 + tagged MTC0 .it : return { opRS, rsMTC0, it.rsrc, it.cop0dst, 11'b0 }; 53.194 + 53.195 + endcase 53.196 + 53.197 + endfunction 53.198 + 53.199 + // Unpack Function 53.200 + 53.201 + function Instr unpack( Bit#(32) instrBits ); 53.202 + 53.203 + let opcode = instrBits[ 31 : 26 ]; 53.204 + let rs = instrBits[ 25 : 21 ]; 53.205 + let rt = instrBits[ 20 : 16 ]; 53.206 + let rd = instrBits[ 15 : 11 ]; 53.207 + let shamt = instrBits[ 10 : 6 ]; 53.208 + let funct = instrBits[ 5 : 0 ]; 53.209 + let imm = instrBits[ 15 : 0 ]; 53.210 + let target = instrBits[ 25 : 0 ]; 53.211 + 53.212 + case ( opcode ) 53.213 + 53.214 + opLW : return LW { rbase:rs, rdst:rt, offset:imm }; 53.215 + opSW : return SW { rbase:rs, rsrc:rt, offset:imm }; 53.216 + opADDIU : return ADDIU { rsrc:rs, rdst:rt, imm:imm }; 53.217 + opSLTI : return SLTI { rsrc:rs, rdst:rt, imm:imm }; 53.218 + opSLTIU : return SLTIU { rsrc:rs, rdst:rt, imm:imm }; 53.219 + opANDI : return ANDI { rsrc:rs, rdst:rt, imm:imm }; 53.220 + opORI : return ORI { rsrc:rs, rdst:rt, imm:imm }; 53.221 + opXORI : return XORI { rsrc:rs, rdst:rt, imm:imm }; 53.222 + opLUI : return LUI { rdst:rt, imm:imm }; 53.223 + opJ : return J { target:target }; 53.224 + opJAL : return JAL { target:target }; 53.225 + opBEQ : return BEQ { rsrc1:rs, rsrc2:rt, offset:imm }; 53.226 + opBNE : return BNE { rsrc1:rs, rsrc2:rt, offset:imm }; 53.227 + opBLEZ : return BLEZ { rsrc:rs, offset:imm }; 53.228 + opBGTZ : return BGTZ { rsrc:rs, offset:imm }; 53.229 + 53.230 + opFUNC : 53.231 + case ( funct ) 53.232 + fcSLL : return SLL { rsrc:rt, rdst:rd, shamt:shamt }; 53.233 + fcSRL : return SRL { rsrc:rt, rdst:rd, shamt:shamt }; 53.234 + fcSRA : return SRA { rsrc:rt, rdst:rd, shamt:shamt }; 53.235 + fcSLLV : return SLLV { rsrc:rt, rdst:rd, rshamt:rs }; 53.236 + fcSRLV : return SRLV { rsrc:rt, rdst:rd, rshamt:rs }; 53.237 + fcSRAV : return SRAV { rsrc:rt, rdst:rd, rshamt:rs }; 53.238 + fcADDU : return ADDU { rsrc1:rs, rsrc2:rt, rdst:rd }; 53.239 + fcSUBU : return SUBU { rsrc1:rs, rsrc2:rt, rdst:rd }; 53.240 + fcAND : return AND { rsrc1:rs, rsrc2:rt, rdst:rd }; 53.241 + fcOR : return OR { rsrc1:rs, rsrc2:rt, rdst:rd }; 53.242 + fcXOR : return XOR { rsrc1:rs, rsrc2:rt, rdst:rd }; 53.243 + fcNOR : return NOR { rsrc1:rs, rsrc2:rt, rdst:rd }; 53.244 + fcSLT : return SLT { rsrc1:rs, rsrc2:rt, rdst:rd }; 53.245 + fcSLTU : return SLTU { rsrc1:rs, rsrc2:rt, rdst:rd }; 53.246 + fcJR : return JR { rsrc:rs }; 53.247 + fcJALR : return JALR { rsrc:rs, rdst:rd }; 53.248 + default : return ILLEGAL; 53.249 + endcase 53.250 + 53.251 + opRT : 53.252 + case ( rt ) 53.253 + rtBLTZ : return BLTZ { rsrc:rs, offset:imm }; 53.254 + rtBGEZ : return BGEZ { rsrc:rs, offset:imm }; 53.255 + default : return ILLEGAL; 53.256 + endcase 53.257 + 53.258 + opRS : 53.259 + case ( rs ) 53.260 + rsMFC0 : return MFC0 { rdst:rt, cop0src:rd }; 53.261 + rsMTC0 : return MTC0 { rsrc:rt, cop0dst:rd }; 53.262 + default : return ILLEGAL; 53.263 + endcase 53.264 + 53.265 + default : return ILLEGAL; 53.266 + 53.267 + endcase 53.268 + 53.269 + endfunction 53.270 + 53.271 +endinstance 53.272 + 53.273 +//---------------------------------------------------------------------- 53.274 +// Trace 53.275 +//---------------------------------------------------------------------- 53.276 + 53.277 +instance Traceable#(Instr); 53.278 + 53.279 + function Action traceTiny( String loc, String ttag, Instr inst ); 53.280 + case ( inst ) matches 53.281 + 53.282 + tagged LW .it : $fdisplay(stderr, " => %s:%s lw", loc, ttag ); 53.283 + tagged SW .it : $fdisplay(stderr, " => %s:%s sw", loc, ttag ); 53.284 + 53.285 + tagged ADDIU .it : $fdisplay(stderr, " => %s:%s addi", loc, ttag ); 53.286 + tagged SLTI .it : $fdisplay(stderr, " => %s:%s sli", loc, ttag ); 53.287 + tagged SLTIU .it : $fdisplay(stderr, " => %s:%s sliu", loc, ttag ); 53.288 + tagged ANDI .it : $fdisplay(stderr, " => %s:%s andi", loc, ttag ); 53.289 + tagged ORI .it : $fdisplay(stderr, " => %s:%s ori", loc, ttag ); 53.290 + tagged XORI .it : $fdisplay(stderr, " => %s:%s xori", loc, ttag ); 53.291 + tagged LUI .it : $fdisplay(stderr, " => %s:%s lui", loc, ttag ); 53.292 + 53.293 + tagged SLL .it : $fdisplay(stderr, " => %s:%s sll", loc, ttag ); 53.294 + tagged SRL .it : $fdisplay(stderr, " => %s:%s srl", loc, ttag ); 53.295 + tagged SRA .it : $fdisplay(stderr, " => %s:%s sra", loc, ttag ); 53.296 + tagged SLLV .it : $fdisplay(stderr, " => %s:%s sllv", loc, ttag ); 53.297 + tagged SRLV .it : $fdisplay(stderr, " => %s:%s srlv", loc, ttag ); 53.298 + tagged SRAV .it : $fdisplay(stderr, " => %s:%s srav", loc, ttag ); 53.299 + 53.300 + tagged ADDU .it : $fdisplay(stderr, " => %s:%s addu", loc, ttag ); 53.301 + tagged SUBU .it : $fdisplay(stderr, " => %s:%s subu", loc, ttag ); 53.302 + tagged AND .it : $fdisplay(stderr, " => %s:%s and", loc, ttag ); 53.303 + tagged OR .it : $fdisplay(stderr, " => %s:%s or", loc, ttag ); 53.304 + tagged XOR .it : $fdisplay(stderr, " => %s:%s xor", loc, ttag ); 53.305 + tagged NOR .it : $fdisplay(stderr, " => %s:%s nor", loc, ttag ); 53.306 + tagged SLT .it : $fdisplay(stderr, " => %s:%s slt", loc, ttag ); 53.307 + tagged SLTU .it : $fdisplay(stderr, " => %s:%s sltu", loc, ttag ); 53.308 + 53.309 + tagged J .it : $fdisplay(stderr, " => %s:%s j", loc, ttag ); 53.310 + tagged JAL .it : $fdisplay(stderr, " => %s:%s jal", loc, ttag ); 53.311 + tagged JR .it : $fdisplay(stderr, " => %s:%s jr", loc, ttag ); 53.312 + tagged JALR .it : $fdisplay(stderr, " => %s:%s jalr", loc, ttag ); 53.313 + tagged BEQ .it : $fdisplay(stderr, " => %s:%s beq", loc, ttag ); 53.314 + tagged BNE .it : $fdisplay(stderr, " => %s:%s bne", loc, ttag ); 53.315 + tagged BLEZ .it : $fdisplay(stderr, " => %s:%s blez", loc, ttag ); 53.316 + tagged BGTZ .it : $fdisplay(stderr, " => %s:%s bgtz", loc, ttag ); 53.317 + tagged BLTZ .it : $fdisplay(stderr, " => %s:%s bltz", loc, ttag ); 53.318 + tagged BGEZ .it : $fdisplay(stderr, " => %s:%s bgez", loc, ttag ); 53.319 + 53.320 + tagged MFC0 .it : $fdisplay(stderr, " => %s:%s mfc0", loc, ttag ); 53.321 + tagged MTC0 .it : $fdisplay(stderr, " => %s:%s mtc0", loc, ttag ); 53.322 + 53.323 + tagged ILLEGAL : $fdisplay(stderr, " => %s:%s ill", loc, ttag ); 53.324 + 53.325 + endcase 53.326 + endfunction 53.327 + 53.328 + function Action traceFull( String loc, String ttag, Instr inst ); 53.329 + case ( inst ) matches 53.330 + 53.331 + tagged LW .it : $fdisplay(stderr, " => %s:%s lw r%0d, 0x%x(r%0d)", loc, ttag, it.rdst, it.offset, it.rbase ); 53.332 + tagged SW .it : $fdisplay(stderr, " => %s:%s sw r%0d, 0x%x(r%0d)", loc, ttag, it.rsrc, it.offset, it.rbase ); 53.333 + 53.334 + tagged ADDIU .it : $fdisplay(stderr, " => %s:%s addiu r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); 53.335 + tagged SLTI .it : $fdisplay(stderr, " => %s:%s slti r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); 53.336 + tagged SLTIU .it : $fdisplay(stderr, " => %s:%s sltiu r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); 53.337 + tagged ANDI .it : $fdisplay(stderr, " => %s:%s andi r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); 53.338 + tagged ORI .it : $fdisplay(stderr, " => %s:%s ori r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); 53.339 + tagged XORI .it : $fdisplay(stderr, " => %s:%s xori r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); 53.340 + tagged LUI .it : $fdisplay(stderr, " => %s:%s lui r%0d, 0x%x", loc, ttag, it.rdst, it.imm ); 53.341 + 53.342 + tagged SLL .it : $fdisplay(stderr, " => %s:%s sll r%0d, r%0d, %0d", loc, ttag, it.rdst, it.rsrc, it.shamt ); 53.343 + tagged SRL .it : $fdisplay(stderr, " => %s:%s srl r%0d, r%0d, %0d", loc, ttag, it.rdst, it.rsrc, it.shamt ); 53.344 + tagged SRA .it : $fdisplay(stderr, " => %s:%s sra r%0d, r%0d, %0d", loc, ttag, it.rdst, it.rsrc, it.shamt ); 53.345 + tagged SLLV .it : $fdisplay(stderr, " => %s:%s sllv r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc, it.rshamt ); 53.346 + tagged SRLV .it : $fdisplay(stderr, " => %s:%s srlv r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc, it.rshamt ); 53.347 + tagged SRAV .it : $fdisplay(stderr, " => %s:%s srav r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc, it.rshamt ); 53.348 + 53.349 + tagged ADDU .it : $fdisplay(stderr, " => %s:%s addu r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); 53.350 + tagged SUBU .it : $fdisplay(stderr, " => %s:%s subu r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); 53.351 + tagged AND .it : $fdisplay(stderr, " => %s:%s and r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); 53.352 + tagged OR .it : $fdisplay(stderr, " => %s:%s or r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); 53.353 + tagged XOR .it : $fdisplay(stderr, " => %s:%s xor r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); 53.354 + tagged NOR .it : $fdisplay(stderr, " => %s:%s nor r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); 53.355 + tagged SLT .it : $fdisplay(stderr, " => %s:%s slt r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); 53.356 + tagged SLTU .it : $fdisplay(stderr, " => %s:%s sltu r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); 53.357 + 53.358 + tagged J .it : $fdisplay(stderr, " => %s:%s j 0x%x", loc, ttag, it.target ); 53.359 + tagged JAL .it : $fdisplay(stderr, " => %s:%s jal 0x%x", loc, ttag, it.target ); 53.360 + tagged JR .it : $fdisplay(stderr, " => %s:%s jr r%0d", loc, ttag, it.rsrc ); 53.361 + tagged JALR .it : $fdisplay(stderr, " => %s:%s jalr r%0d", loc, ttag, it.rsrc ); 53.362 + tagged BEQ .it : $fdisplay(stderr, " => %s:%s beq r%0d, r%0d, 0x%x", loc, ttag, it.rsrc1, it.rsrc2, it.offset ); 53.363 + tagged BNE .it : $fdisplay(stderr, " => %s:%s bne r%0d, r%0d, 0x%x", loc, ttag, it.rsrc1, it.rsrc2, it.offset ); 53.364 + tagged BLEZ .it : $fdisplay(stderr, " => %s:%s blez r%0d, 0x%x", loc, ttag, it.rsrc, it.offset ); 53.365 + tagged BGTZ .it : $fdisplay(stderr, " => %s:%s bgtz r%0d, 0x%x", loc, ttag, it.rsrc, it.offset ); 53.366 + tagged BLTZ .it : $fdisplay(stderr, " => %s:%s bltz r%0d, 0x%x", loc, ttag, it.rsrc, it.offset ); 53.367 + tagged BGEZ .it : $fdisplay(stderr, " => %s:%s bgez r%0d, 0x%x", loc, ttag, it.rsrc, it.offset ); 53.368 + 53.369 + tagged MFC0 .it : $fdisplay(stderr, " => %s:%s mfc0 r%0d, cpr%0d", loc, ttag, it.rdst, it.cop0src ); 53.370 + tagged MTC0 .it : $fdisplay(stderr, " => %s:%s mtc0 r%0d, cpr%0d", loc, ttag, it.rsrc, it.cop0dst ); 53.371 + 53.372 + tagged ILLEGAL : $fdisplay(stderr, " => %s:%s illegal instruction", loc, ttag ); 53.373 + 53.374 + endcase 53.375 + endfunction 53.376 + 53.377 +endinstance 53.378 +
54.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 54.2 +++ b/core/src/Processor.bsv Tue Apr 13 17:34:33 2010 -0400 54.3 @@ -0,0 +1,559 @@ 54.4 +/// The MIT License 54.5 + 54.6 +// Copyright (c) 2009 Massachusetts Institute of Technology 54.7 + 54.8 +// Permission is hereby granted, free of charge, to any person obtaining a copy 54.9 +// of this software and associated documentation files (the "Software"), to deal 54.10 +// in the Software without restriction, including without limitation the rights 54.11 +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 54.12 +// copies of the Software, and to permit persons to whom the Software is 54.13 +// furnished to do so, subject to the following conditions: 54.14 + 54.15 +// The above copyright notice and this permission notice shall be included in 54.16 +// all copies or substantial portions of the Software. 54.17 + 54.18 +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 54.19 +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 54.20 +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 54.21 +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 54.22 +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 54.23 +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 54.24 +// THE SOFTWARE. 54.25 + 54.26 +import Connectable::*; 54.27 +import GetPut::*; 54.28 +import ClientServer::*; 54.29 +import RegFile::*; 54.30 +import BRegFile::*; 54.31 +import FIFO::*; 54.32 +import FIFOF::*; 54.33 +import SFIFO::*; 54.34 +import RWire::*; 54.35 + 54.36 +import BFIFO::*; 54.37 +import MemTypes::*; 54.38 +import ProcTypes::*; 54.39 +import BranchPred::*; 54.40 +import PathTypes::*; 54.41 + 54.42 +import Trace::*; 54.43 + 54.44 +interface ProcStats; 54.45 + interface Get#(Stat) num_cycles; 54.46 + interface Get#(Stat) num_inst; 54.47 +endinterface 54.48 + 54.49 +interface CPUToHost; 54.50 + method Bit#(32) cpuToHost(int req); 54.51 +endinterface 54.52 + 54.53 +interface Proc; 54.54 + 54.55 + // Interface from processor to caches 54.56 + interface Client#(DataReq,DataResp) dmem_client; 54.57 + interface Client#(InstReq,InstResp) imem_client; 54.58 + 54.59 + // Interface for enabling/disabling statistics on the rest of the core 54.60 + interface Get#(Bool) statsEn_get; 54.61 + 54.62 + // Interface for collecting statistics. 54.63 + interface ProcStats stats; 54.64 + 54.65 + // Interface to host 54.66 + interface CPUToHost tohost; 54.67 + 54.68 +endinterface 54.69 + 54.70 + 54.71 +typedef enum { PCgen, Exec, Writeback } Stage deriving(Eq,Bits); 54.72 + 54.73 +//----------------------------------------------------------- 54.74 +// Register file module 54.75 +//----------------------------------------------------------- 54.76 + 54.77 +interface BRFile; 54.78 + method Action wr( Rindx rindx, Bit#(32) data ); 54.79 + method Bit#(32) rd1( Rindx rindx ); 54.80 + method Bit#(32) rd2( Rindx rindx ); 54.81 +endinterface 54.82 + 54.83 +module mkBRFile( BRFile ); 54.84 + 54.85 + RegFile#(Rindx,Bit#(32)) rfile <- mkBRegFile(); 54.86 + 54.87 + method Action wr( Rindx rindx, Bit#(32) data ); 54.88 + rfile.upd( rindx, data ); 54.89 + endmethod 54.90 + 54.91 + method Bit#(32) rd1( Rindx rindx ); 54.92 + return ( rindx == 0 ) ? 0 : rfile.sub(rindx); 54.93 + endmethod 54.94 + 54.95 + method Bit#(32) rd2( Rindx rindx ); 54.96 + return ( rindx == 0 ) ? 0 : rfile.sub(rindx); 54.97 + endmethod 54.98 + 54.99 +endmodule 54.100 + 54.101 +//----------------------------------------------------------- 54.102 +// Helper functions 54.103 +//----------------------------------------------------------- 54.104 + 54.105 +function Bit#(32) slt( Bit#(32) val1, Bit#(32) val2 ); 54.106 + return zeroExtend( pack( signedLT(val1,val2) ) ); 54.107 +endfunction 54.108 + 54.109 +function Bit#(32) sltu( Bit#(32) val1, Bit#(32) val2 ); 54.110 + return zeroExtend( pack( val1 < val2 ) ); 54.111 +endfunction 54.112 + 54.113 +function Bit#(32) rshft( Bit#(32) val ); 54.114 + return zeroExtend(val[4:0]); 54.115 +endfunction 54.116 + 54.117 + 54.118 +//----------------------------------------------------------- 54.119 +// Find funct for wbQ 54.120 +//----------------------------------------------------------- 54.121 +function Bool findwbf(Rindx fVal, WBResult cmpVal); 54.122 + case (cmpVal) matches 54.123 + tagged WB_ALU {data:.res, dest:.rd} : 54.124 + return (fVal == rd); 54.125 + tagged WB_Load .rd : 54.126 + return (fVal == rd); 54.127 + tagged WB_Store .st : 54.128 + return False; 54.129 + tagged WB_Host .x : 54.130 + return False; 54.131 + endcase 54.132 +endfunction 54.133 + 54.134 + 54.135 +//----------------------------------------------------------- 54.136 +// Stall funct for wbQ 54.137 +//----------------------------------------------------------- 54.138 +function Bool stall(Instr inst, SFIFO#(WBResult, Rindx) f); 54.139 + case (inst) matches 54.140 + // -- Memory Ops ------------------------------------------------ 54.141 + tagged LW .it : 54.142 + return f.find(it.rbase); 54.143 + tagged SW {rsrc:.dreg, rbase:.addr, offset:.o} : 54.144 + return (f.find(addr) || f.find2(dreg)); 54.145 + 54.146 + // -- Simple Ops ------------------------------------------------ 54.147 + tagged ADDIU .it : return f.find(it.rsrc); 54.148 + tagged SLTI .it : return f.find(it.rsrc); 54.149 + tagged SLTIU .it : return f.find(it.rsrc); 54.150 + tagged ANDI .it : return f.find(it.rsrc); 54.151 + tagged ORI .it : return f.find(it.rsrc); 54.152 + tagged XORI .it : return f.find(it.rsrc); 54.153 + 54.154 + tagged LUI .it : return f.find(it.rdst); //this rds/wrs itself 54.155 + tagged SLL .it : return f.find(it.rsrc); 54.156 + tagged SRL .it : return f.find(it.rsrc); 54.157 + tagged SRA .it : return f.find(it.rsrc); 54.158 + tagged SLLV .it : return (f.find(it.rsrc) || f.find(it.rshamt)); 54.159 + tagged SRLV .it : return (f.find(it.rsrc) || f.find(it.rshamt)); 54.160 + tagged SRAV .it : return (f.find(it.rsrc) || f.find(it.rshamt)); 54.161 + tagged ADDU .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); 54.162 + tagged SUBU .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); 54.163 + tagged AND .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); 54.164 + tagged OR .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); 54.165 + tagged XOR .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); 54.166 + tagged NOR .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); 54.167 + tagged SLT .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); 54.168 + tagged SLTU .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); 54.169 + 54.170 + 54.171 + // -- Branches -------------------------------------------------- 54.172 + 54.173 + tagged BLEZ .it : return (f.find(it.rsrc)); 54.174 + tagged BGTZ .it : return (f.find(it.rsrc)); 54.175 + tagged BLTZ .it : return (f.find(it.rsrc)); 54.176 + tagged BGEZ .it : return (f.find(it.rsrc)); 54.177 + tagged BEQ .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); 54.178 + tagged BNE .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); 54.179 + 54.180 + // -- Jumps ----------------------------------------------------- 54.181 + 54.182 + tagged J .it : return False; 54.183 + tagged JR .it : return f.find(it.rsrc); 54.184 + tagged JALR .it : return f.find(it.rsrc); 54.185 + tagged JAL .it : return False; 54.186 + 54.187 + // -- Cop0 ------------------------------------------------------ 54.188 + 54.189 + tagged MTC0 .it : return f.find(it.rsrc); 54.190 + tagged MFC0 .it : return False; 54.191 + 54.192 + // -- Illegal --------------------------------------------------- 54.193 + 54.194 + default : return False; 54.195 + 54.196 + endcase 54.197 +endfunction 54.198 +//----------------------------------------------------------- 54.199 +// Reference processor 54.200 +//----------------------------------------------------------- 54.201 + 54.202 + 54.203 +(* doc = "synthesis attribute ram_style mkProc distributed;" *) 54.204 +(* synthesize *) 54.205 +module mkProc( Proc ); 54.206 + 54.207 + //----------------------------------------------------------- 54.208 + // State 54.209 + 54.210 + // Standard processor state 54.211 + 54.212 + Reg#(Addr) pc <- mkReg(32'h00001000); 54.213 + Reg#(Epoch) epoch <- mkReg(0); 54.214 + Reg#(Stage) stage <- mkReg(PCgen); 54.215 + BRFile rf <- mkBRFile; 54.216 + 54.217 + // Branch Prediction 54.218 + BranchPred bp <- mkBranchPred(); 54.219 + FIFO#(PCStat) execpc <- mkLFIFO(); 54.220 + 54.221 + // Pipelines 54.222 + FIFO#(PCStat) pcQ <-mkSizedFIFO(3); 54.223 + SFIFO#(WBResult, Rindx) wbQ <-mkSFIFO(findwbf); 54.224 + 54.225 + Reg#(Bit#(32)) cp0_tohost <- mkReg(0); 54.226 + Reg#(Bit#(32)) cp0_fromhost <- mkReg(0); 54.227 + Reg#(Bool) cp0_statsEn <- mkReg(False); 54.228 + 54.229 + // Memory request/response state 54.230 + 54.231 + FIFO#(InstReq) instReqQ <- mkBFIFO1(); 54.232 + FIFO#(InstResp) instRespQ <- mkFIFO(); 54.233 + 54.234 + FIFO#(DataReq) dataReqQ <- mkBFIFO1(); 54.235 + FIFO#(DataResp) dataRespQ <- mkFIFO(); 54.236 + 54.237 + // Statistics state 54.238 + Reg#(Stat) num_cycles <- mkReg(0); 54.239 + Reg#(Stat) num_inst <- mkReg(0); 54.240 + 54.241 + //----------------------------------------------------------- 54.242 + // Rules 54.243 + 54.244 + (* descending_urgency = "exec, pcgen" *) 54.245 + rule pcgen; //( stage == PCgen ); 54.246 + let pc_plus4 = pc + 4; 54.247 + 54.248 + traceTiny("mkProc", "pc",pc); 54.249 + traceTiny("mkProc", "pcgen","P"); 54.250 + instReqQ.enq( LoadReq{ addr:pc, tag:epoch} ); 54.251 + 54.252 + let next_pc = bp.get(pc); 54.253 + if (next_pc matches tagged Valid .npc) 54.254 + begin 54.255 + pcQ.enq(PCStat {qpc:pc, qnxtpc:npc, qepoch:epoch}); 54.256 + pc <= npc; 54.257 + end 54.258 + else 54.259 + begin 54.260 + pcQ.enq(PCStat {qpc:pc, qnxtpc:pc_plus4, qepoch:epoch}); 54.261 + pc <= pc_plus4; 54.262 + end 54.263 + 54.264 + endrule 54.265 + 54.266 + rule discard (instRespQ.first() matches tagged LoadResp .ld 54.267 + &&& ld.tag != epoch); 54.268 + traceTiny("mkProc", "stage", "D"); 54.269 + instRespQ.deq(); 54.270 + endrule 54.271 + 54.272 + (* conflict_free = "exec, writeback" *) 54.273 + rule exec (instRespQ.first() matches tagged LoadResp.ld 54.274 + &&& (ld.tag == epoch) 54.275 + &&& unpack(ld.data) matches .inst 54.276 + &&& !stall(inst, wbQ)); 54.277 + 54.278 + // Some abbreviations 54.279 + let sext = signExtend; 54.280 + let zext = zeroExtend; 54.281 + let sra = signedShiftRight; 54.282 + 54.283 + // Get the instruction 54.284 + 54.285 + instRespQ.deq(); 54.286 + Instr inst 54.287 + = case ( instRespQ.first() ) matches 54.288 + tagged LoadResp .ld : return unpack(ld.data); 54.289 + tagged StoreResp .st : return ?; 54.290 + endcase; 54.291 + 54.292 + // Get the PC info 54.293 + let instrpc = pcQ.first().qpc; 54.294 + let pc_plus4 = instrpc + 4; 54.295 + 54.296 + Bool branchTaken = False; 54.297 + Addr newPC = pc_plus4; 54.298 + 54.299 + // Tracing 54.300 + traceTiny("mkProc", "exec","X"); 54.301 + traceTiny("mkProc", "exInstTiny",inst); 54.302 + traceFull("mkProc", "exInstFull",inst); 54.303 + 54.304 + case ( inst ) matches 54.305 + 54.306 + // -- Memory Ops ------------------------------------------------ 54.307 + 54.308 + tagged LW .it : 54.309 + begin 54.310 + Addr addr = rf.rd1(it.rbase) + sext(it.offset); 54.311 + dataReqQ.enq( LoadReq{ addr:addr, tag:zeroExtend(it.rdst) } ); 54.312 + wbQ.enq(tagged WB_Load it.rdst); 54.313 + end 54.314 + 54.315 + tagged SW .it : 54.316 + begin 54.317 + Addr addr = rf.rd1(it.rbase) + sext(it.offset); 54.318 + dataReqQ.enq( StoreReq{ tag:0, addr:addr, data:rf.rd2(it.rsrc) } ); 54.319 + wbQ.enq(tagged WB_Store); 54.320 + end 54.321 + 54.322 + // -- Simple Ops ------------------------------------------------ 54.323 + 54.324 + tagged ADDIU .it : 54.325 + begin 54.326 + Bit#(32) result = rf.rd1(it.rsrc) + sext(it.imm); 54.327 + wbQ.enq(tagged WB_ALU {data:result, dest:it.rdst}); 54.328 + end 54.329 + tagged SLTI .it : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:slt( rf.rd1(it.rsrc), sext(it.imm) )}); 54.330 + tagged SLTIU .it : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:sltu( rf.rd1(it.rsrc), sext(it.imm) ) }); 54.331 + tagged ANDI .it : 54.332 + begin 54.333 + Bit#(32) zext_it_imm = zext(it.imm); 54.334 + wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(rf.rd1(it.rsrc) & zext_it_imm)} ); 54.335 + end 54.336 + tagged ORI .it : 54.337 + begin 54.338 + Bit#(32) zext_it_imm = zext(it.imm); 54.339 + wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(rf.rd1(it.rsrc) | zext_it_imm)} ); 54.340 + end 54.341 + tagged XORI .it : 54.342 + begin 54.343 + Bit#(32) zext_it_imm = zext(it.imm); 54.344 + wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) ^ zext_it_imm )}); 54.345 + end 54.346 + tagged LUI .it : 54.347 + begin 54.348 + Bit#(32) zext_it_imm = zext(it.imm); 54.349 + wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(zext_it_imm << 32'd16) }); 54.350 + end 54.351 + 54.352 + tagged SLL .it : 54.353 + begin 54.354 + Bit#(32) zext_it_shamt = zext(it.shamt); 54.355 + wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) << zext_it_shamt )} ); 54.356 + end 54.357 + tagged SRL .it : 54.358 + begin 54.359 + Bit#(32) zext_it_shamt = zext(it.shamt); 54.360 + wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) >> zext_it_shamt )}); 54.361 + end 54.362 + tagged SRA .it : 54.363 + begin 54.364 + Bit#(32) zext_it_shamt = zext(it.shamt); 54.365 + wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( rf.rd1(it.rsrc), zext_it_shamt )}); 54.366 + end 54.367 + tagged SLLV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) << rshft(rf.rd2(it.rshamt)) )}); 54.368 + tagged SRLV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) >> rshft(rf.rd2(it.rshamt)) )} ); 54.369 + tagged SRAV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( rf.rd1(it.rsrc), rshft(rf.rd2(it.rshamt)) ) }); 54.370 + tagged ADDU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) + rf.rd2(it.rsrc2) )} ); 54.371 + tagged SUBU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) - rf.rd2(it.rsrc2) )} ); 54.372 + tagged AND .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) & rf.rd2(it.rsrc2) )} ); 54.373 + tagged OR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) | rf.rd2(it.rsrc2) )} ); 54.374 + tagged XOR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) ^ rf.rd2(it.rsrc2) )} ); 54.375 + tagged NOR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(~(rf.rd1(it.rsrc1) | rf.rd2(it.rsrc2)) )} ); 54.376 + tagged SLT .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:slt( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) }); 54.377 + tagged SLTU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sltu( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) }); 54.378 + 54.379 + // -- Branches -------------------------------------------------- 54.380 + 54.381 + tagged BLEZ .it : 54.382 + if ( signedLE( rf.rd1(it.rsrc), 0 ) ) 54.383 + begin 54.384 + newPC = pc_plus4 + (sext(it.offset) << 2); 54.385 + branchTaken = True; 54.386 + end 54.387 + 54.388 + tagged BGTZ .it : 54.389 + if ( signedGT( rf.rd1(it.rsrc), 0 ) ) 54.390 + begin 54.391 + newPC = pc_plus4 + (sext(it.offset) << 2); 54.392 + branchTaken = True; 54.393 + end 54.394 + 54.395 + tagged BLTZ .it : 54.396 + if ( signedLT( rf.rd1(it.rsrc), 0 ) ) 54.397 + begin 54.398 + newPC = pc_plus4 + (sext(it.offset) << 2); 54.399 + branchTaken = True; 54.400 + end 54.401 + 54.402 + tagged BGEZ .it : 54.403 + if ( signedGE( rf.rd1(it.rsrc), 0 ) ) 54.404 + begin 54.405 + newPC = pc_plus4 + (sext(it.offset) << 2); 54.406 + branchTaken = True; 54.407 + end 54.408 + 54.409 + tagged BEQ .it : 54.410 + if ( rf.rd1(it.rsrc1) == rf.rd2(it.rsrc2) ) 54.411 + begin 54.412 + newPC = pc_plus4 + (sext(it.offset) << 2); 54.413 + branchTaken = True; 54.414 + end 54.415 + 54.416 + tagged BNE .it : 54.417 + if ( rf.rd1(it.rsrc1) != rf.rd2(it.rsrc2) ) 54.418 + begin 54.419 + newPC = pc_plus4 + (sext(it.offset) << 2); 54.420 + branchTaken = True; 54.421 + end 54.422 + 54.423 + // -- Jumps ----------------------------------------------------- 54.424 + 54.425 + tagged J .it : 54.426 + begin 54.427 + newPC = { pc_plus4[31:28], it.target, 2'b0 }; 54.428 + branchTaken = True; 54.429 + end 54.430 + 54.431 + tagged JR .it : 54.432 + begin 54.433 + newPC = rf.rd1(it.rsrc); 54.434 + branchTaken = True; 54.435 + end 54.436 + 54.437 + tagged JAL .it : 54.438 + begin 54.439 + wbQ.enq(tagged WB_ALU {dest:31, data:pc_plus4 }); 54.440 + newPC = { pc_plus4[31:28], it.target, 2'b0 }; 54.441 + branchTaken = True; 54.442 + end 54.443 + 54.444 + tagged JALR .it : 54.445 + begin 54.446 + wbQ.enq(tagged WB_ALU {dest:it.rdst, data:pc_plus4 }); 54.447 + newPC = rf.rd1(it.rsrc); 54.448 + branchTaken = True; 54.449 + end 54.450 + 54.451 + // -- Cop0 ------------------------------------------------------ 54.452 + 54.453 + tagged MTC0 .it : 54.454 + begin 54.455 + case ( it.cop0dst ) 54.456 + 5'd10 : cp0_statsEn <= unpack(truncate(rf.rd1(it.rsrc))); 54.457 + 5'd21 : cp0_tohost <= truncate(rf.rd1(it.rsrc)); 54.458 + default : 54.459 + $display( " RTL-ERROR : %m : Illegal MTC0 cop0dst register!" ); 54.460 + endcase 54.461 + wbQ.enq(tagged WB_Host 0); //no idea wwhat this actually should be. 54.462 + end 54.463 + 54.464 +//this is host stuff? 54.465 + tagged MFC0 .it : 54.466 + begin 54.467 + case ( it.cop0src ) 54.468 + // not actually an ALU instruction but don't have the format otherwise 54.469 + 5'd10 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(cp0_statsEn)) }); 54.470 + 5'd20 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_fromhost }); 54.471 + 5'd21 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_tohost }); 54.472 + default : 54.473 + $display( " RTL-ERROR : %m : Illegal MFC0 cop0src register!" ); 54.474 + endcase 54.475 + end 54.476 + 54.477 + // -- Illegal --------------------------------------------------- 54.478 + 54.479 + default : 54.480 + $display( " RTL-ERROR : %m : Illegal instruction !" ); 54.481 + 54.482 + endcase 54.483 + 54.484 +//evaluate branch prediction 54.485 + Addr ppc = pcQ.first().qnxtpc; //predicted branch 54.486 + if (ppc != newPC) //prediction wrong 54.487 + begin 54.488 + epoch <= pcQ.first().qepoch + 1; 54.489 + bp.upd(instrpc, newPC); //update branch predictor 54.490 + pcQ.clear(); 54.491 + pc <= newPC; 54.492 + end 54.493 + else 54.494 + pcQ.deq(); 54.495 + 54.496 + if ( cp0_statsEn ) 54.497 + num_inst <= num_inst+1; 54.498 + 54.499 + endrule 54.500 + 54.501 + rule writeback; // ( stage == Writeback ); 54.502 + traceTiny("mkProc", "writeback","W"); 54.503 + 54.504 + 54.505 + // get what to do off the writeback queue 54.506 + wbQ.deq(); 54.507 + case (wbQ.first()) matches 54.508 + tagged WB_ALU {data:.res, dest:.rdst} : rf.wr(rdst, res); 54.509 + tagged WB_Load .regWr : 54.510 + begin 54.511 + dataRespQ.deq(); 54.512 + if (dataRespQ.first() matches tagged LoadResp .ld) 54.513 + rf.wr(truncate(ld.tag), ld.data); // no need to use Rindx from queue? Duplicate? 54.514 + end 54.515 + tagged WB_Store : dataRespQ.deq(); 54.516 + tagged WB_Host .dat : noAction; 54.517 + endcase 54.518 + 54.519 + endrule 54.520 + 54.521 + rule inc_num_cycles; 54.522 + if ( cp0_statsEn ) 54.523 + num_cycles <= num_cycles+1; 54.524 + endrule 54.525 + 54.526 + 54.527 +//----------------------------------------------------------- 54.528 +// My Adds 54.529 +//----------------------------------------------------------- 54.530 + 54.531 + //----------------------------------------------------------- 54.532 + // Methods 54.533 + 54.534 + interface Client imem_client; 54.535 + interface Get request = toGet(instReqQ); 54.536 + interface Put response = toPut(instRespQ); 54.537 + endinterface 54.538 + 54.539 + interface Client dmem_client; 54.540 + interface Get request = toGet(dataReqQ); 54.541 + interface Put response = toPut(dataRespQ); 54.542 + endinterface 54.543 + 54.544 + interface Get statsEn_get = toGet(asReg(cp0_statsEn)); 54.545 + 54.546 + interface ProcStats stats; 54.547 + interface Get num_cycles = toGet(asReg(num_cycles)); 54.548 + interface Get num_inst = toGet(asReg(num_inst)); 54.549 + endinterface 54.550 + 54.551 + interface CPUToHost tohost; 54.552 + method Bit#(32) cpuToHost(int req); 54.553 + return (case (req) 54.554 + 0: cp0_tohost; 54.555 + 1: pc; 54.556 + 2: zeroExtend(pack(stage)); 54.557 + endcase); 54.558 + endmethod 54.559 + endinterface 54.560 + 54.561 +endmodule 54.562 +
55.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 55.2 +++ b/core/src/SFIFO.bsv Tue Apr 13 17:34:33 2010 -0400 55.3 @@ -0,0 +1,213 @@ 55.4 + 55.5 +import FIFO::*; 55.6 +import ConfigReg::*; 55.7 +import RWire::*; 55.8 + 55.9 +import List::*; 55.10 +import Monad::*; 55.11 + 55.12 +interface SFIFO#(type alpha_T, type search_T); 55.13 + method Action enq(alpha_T x); 55.14 + method Action deq(); 55.15 + method alpha_T first(); 55.16 + method Action clear(); 55.17 + method Bool find(search_T x); 55.18 + method Bool find2(search_T x); 55.19 + 55.20 +endinterface 55.21 + 55.22 +module mkSFIFO#(function Bool searchfunc(search_T s, alpha_T x)) (SFIFO#(alpha_T, search_T)) 55.23 + provisos 55.24 + (Bits#(alpha_T,asz)); 55.25 + 55.26 + Reg#(alpha_T) f0 <- mkConfigRegU(); 55.27 + Reg#(alpha_T) f1 <- mkConfigRegU(); 55.28 + 55.29 + Reg#(Bool) vf0 <- mkConfigReg(False); 55.30 + Reg#(Bool) vf1 <- mkConfigReg(False); 55.31 + 55.32 + PulseWire edge1 <- mkPulseWire(); 55.33 + 55.34 + method Action enq(alpha_T x) if (!(vf0 && vf1)); 55.35 + if (edge1 || !vf0)//empty or we're dequeueing 55.36 + begin 55.37 + vf0 <= True; //True 55.38 + vf1 <= False; 55.39 + f0 <= x; 55.40 + end 55.41 + else // !vf1 55.42 + begin 55.43 + vf1 <= True; 55.44 + f1 <= x; 55.45 + end 55.46 + endmethod 55.47 + 55.48 + method Action deq() if (vf0); 55.49 + edge1.send(); 55.50 + vf0 <= vf1; 55.51 + f0 <= f1; 55.52 + vf1 <= False; 55.53 + endmethod 55.54 + 55.55 + method alpha_T first() if(vf0); 55.56 + return (f0); 55.57 + endmethod 55.58 + 55.59 + method Action clear(); 55.60 + vf0 <= False; 55.61 + vf1 <= False; 55.62 + endmethod 55.63 + 55.64 + method Bool find(search_T sv); 55.65 + Bool nvf0 = edge1 ? False: vf0; 55.66 + Bool nvf1 = vf1; 55.67 + 55.68 + return (nvf0 && searchfunc(sv, f0) || 55.69 + nvf1 && searchfunc(sv, f1)); 55.70 + endmethod 55.71 + 55.72 + method Bool find2(search_T sv); 55.73 + Bool nvf0 = edge1 ? False: vf0; 55.74 + Bool nvf1 = vf1; 55.75 + 55.76 + return (nvf0 && searchfunc(sv, f0) || 55.77 + nvf1 && searchfunc(sv, f1)); 55.78 + endmethod 55.79 + 55.80 +endmodule 55.81 + 55.82 +module mkSFIFO1#(function Bool searchfunc(search_T s, alpha_T x)) (SFIFO#(alpha_T, search_T)) 55.83 + provisos 55.84 + (Bits#(alpha_T,asz), Eq#(alpha_T)); 55.85 + 55.86 + Reg#(alpha_T) f0 <- mkConfigRegU; 55.87 + 55.88 + Reg#(Bool) vf0 <- mkConfigReg(False); 55.89 + 55.90 + PulseWire edge1 <- mkPulseWire(); 55.91 + 55.92 + method Action enq(alpha_T x) if (!vf0); 55.93 + vf0 <= True; //True 55.94 + f0 <= x; 55.95 + endmethod 55.96 + 55.97 + method Action deq() if (vf0); 55.98 + edge1.send(); 55.99 + vf0 <= False; 55.100 + endmethod 55.101 + 55.102 + method alpha_T first() if(vf0); 55.103 + return (f0); 55.104 + endmethod 55.105 + 55.106 + method Action clear(); 55.107 + vf0 <= False; 55.108 + endmethod 55.109 + 55.110 + method Bool find(search_T sv); 55.111 + Bool nvf0 = edge1 ? False: vf0; 55.112 + 55.113 + return (nvf0 && searchfunc(sv, f0)); 55.114 + endmethod 55.115 + 55.116 + method Bool find2(search_T sv); 55.117 + Bool nvf0 = edge1 ? False: vf0; 55.118 + return (nvf0 && searchfunc(sv, f0)); 55.119 + endmethod 55.120 + 55.121 +endmodule 55.122 + 55.123 +module mkSizedSFIFOInternal#(Integer n, 55.124 + function Bool searchfunc1(search_T s, alpha_T x), 55.125 + function Bool searchfunc2(search_T s, alpha_T x)) (SFIFO#(alpha_T, search_T)) 55.126 + 55.127 + provisos ( Bits#(alpha_T,alpha_SZ) ); 55.128 + 55.129 + List#(Reg#(alpha_T)) registers <- replicateM(n, mkRegU); 55.130 + List#(Reg#(Bool)) valids <- replicateM(n, mkReg(False)); 55.131 + 55.132 + function Nat getNextFree (List#(Reg#(Bool)) vs); 55.133 + 55.134 + Nat res = fromInteger(n - 1); 55.135 + 55.136 + for (Integer x = n - 1; x > -1; x = x - 1) 55.137 + res = !vs[x]._read() ? fromInteger(x) : res; 55.138 + 55.139 + return res; 55.140 + 55.141 + endfunction 55.142 + 55.143 + function Bool notFull(); 55.144 + 55.145 + Bool full = True; 55.146 + 55.147 + for (Integer x = 0; x < n; x = x + 1) 55.148 + full = full && valids[x]._read(); 55.149 + 55.150 + return !full; 55.151 + 55.152 + endfunction 55.153 + 55.154 + method Action enq( alpha_T item ) if ( notFull() ); 55.155 + 55.156 + Nat k = getNextFree(valids); 55.157 + select(valids, k)._write(True); 55.158 + select(registers, k)._write(item); 55.159 + 55.160 + endmethod 55.161 + 55.162 + method Action deq() if ( valids[0]._read() ); 55.163 + 55.164 + for (Integer x = 0; x < (n-1); x = x + 1) 55.165 + begin 55.166 + 55.167 + (registers[x]) <= registers[x + 1]._read(); 55.168 + (valids[x]) <= valids[x + 1]._read(); 55.169 + 55.170 + end 55.171 + (valids[n-1]) <= False; 55.172 + endmethod 55.173 + 55.174 + method alpha_T first() if ( valids[0]._read() ); 55.175 + return registers[0]._read(); 55.176 + endmethod 55.177 + 55.178 + method Bool find(search_T sv); 55.179 + Bool res = False; 55.180 + 55.181 + for (Integer x = 0; x < n; x = x + 1) 55.182 + if ( valids[x]._read() && searchfunc1(sv, registers[x]._read()) ) 55.183 + res = True; 55.184 + 55.185 + return res; 55.186 + 55.187 + endmethod 55.188 + 55.189 + method Bool find2(search_T sv); 55.190 + Bool res = False; 55.191 + 55.192 + for (Integer x = 0; x < n; x = x + 1) 55.193 + if ( valids[x]._read() && searchfunc2(sv, registers[x]._read()) ) 55.194 + res = True; 55.195 + 55.196 + return res; 55.197 + 55.198 + endmethod 55.199 + 55.200 + method Action clear(); 55.201 + 55.202 + for (Integer x = 0; x < n; x = x + 1) 55.203 + (valids[x]) <= False; 55.204 + 55.205 + endmethod 55.206 + 55.207 +endmodule 55.208 + 55.209 +module mkSizedSFIFO#(Integer n, function Bool searchfunc(search_T s, alpha_T x)) (SFIFO#(alpha_T, search_T)) 55.210 + provisos 55.211 + (Bits#(alpha_T,asz)); 55.212 + 55.213 + let foo <- mkSizedSFIFOInternal(n, searchfunc, searchfunc); 55.214 + return foo; 55.215 + 55.216 +endmodule
56.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 56.2 +++ b/core/src/Trace.bsv Tue Apr 13 17:34:33 2010 -0400 56.3 @@ -0,0 +1,92 @@ 56.4 + 56.5 +import ClientServer::*; 56.6 +import GetPut::*; 56.7 + 56.8 +//---------------------------------------------------------------------- 56.9 +// ToString typeclass 56.10 +//---------------------------------------------------------------------- 56.11 + 56.12 +typeclass Traceable#( type item_t ); 56.13 + function Action traceTiny( String loc, String traceTag, item_t item ); 56.14 + function Action traceFull( String loc, String traceTag, item_t item ); 56.15 +endtypeclass 56.16 + 56.17 +instance Traceable#(String); 56.18 + 56.19 + function Action traceTiny( String loc, String ttag, String str ); 56.20 + $fdisplay(stderr, " => %s:%s %s", loc, ttag, str ); 56.21 + endfunction 56.22 + 56.23 + function Action traceFull( String loc, String ttag, String str ); 56.24 + $fdisplay(stderr, " => %s:%s %s", loc, ttag, str ); 56.25 + endfunction 56.26 + 56.27 +endinstance 56.28 + 56.29 +instance Traceable#(Bit#(n)); 56.30 + 56.31 + function Action traceTiny( String loc, String ttag, Bit#(n) b ); 56.32 + $fdisplay(stderr, " => %s:%s %x", loc, ttag, b ); 56.33 + endfunction 56.34 + 56.35 + function Action traceFull( String loc, String ttag, Bit#(n) b ); 56.36 + $fdisplay(stderr, " => %s:%s %x", loc, ttag, b ); 56.37 + endfunction 56.38 + 56.39 +endinstance 56.40 + 56.41 +//---------------------------------------------------------------------- 56.42 +// Tracing interface wrappers 56.43 +//---------------------------------------------------------------------- 56.44 + 56.45 +function Get#(item_t) traceGet( String locStr, String tagStr, Get#(item_t) g ) 56.46 + provisos ( Traceable#(item_t) ); 56.47 + return 56.48 + ( 56.49 + interface Get 56.50 + method ActionValue#(item_t) get(); 56.51 + item_t item <- g.get(); 56.52 + traceTiny(locStr, tagStr,item); 56.53 + return item; 56.54 + endmethod 56.55 + endinterface 56.56 + ); 56.57 +endfunction 56.58 + 56.59 +function Put#(item_t) tracePut( String locStr, String tagStr, Put#(item_t) p ) 56.60 + provisos ( Traceable#(item_t) ); 56.61 + return 56.62 + ( 56.63 + interface Put 56.64 + method Action put( item_t item ); 56.65 + traceTiny(locStr, tagStr,item); 56.66 + p.put(item); 56.67 + endmethod 56.68 + endinterface 56.69 + ); 56.70 +endfunction 56.71 + 56.72 +function Client#(req_t,resp_t) traceClient( String locStr, String reqTagStr, String respTagStr, 56.73 + Client#(req_t,resp_t) c ) 56.74 + provisos ( Traceable#(req_t), Traceable#(resp_t) ); 56.75 + return 56.76 + ( 56.77 + interface Client 56.78 + interface Get request = traceGet(locStr, reqTagStr,c.request); 56.79 + interface Put response = tracePut(locStr, respTagStr,c.response); 56.80 + endinterface 56.81 + ); 56.82 +endfunction 56.83 + 56.84 +function Server#(req_t,resp_t) traceServer( String locStr, String reqTagStr, String respTagStr, 56.85 + Server#(req_t,resp_t) c ) 56.86 + provisos ( Traceable#(req_t), Traceable#(resp_t) ); 56.87 + return 56.88 + ( 56.89 + interface Server 56.90 + interface Put request = tracePut(locStr, reqTagStr,c.request); 56.91 + interface Get response = traceGet(locStr, respTagStr,c.response); 56.92 + endinterface 56.93 + ); 56.94 +endfunction 56.95 +