# HG changeset patch # User punk # Date 1271194473 14400 # Node ID 91a1f76ddd62f343cc5f7fcf41f38928852a1390 # Parent 6d1ff93e3afab2d18b03ff9caa8d3f1abf5754f2 [svn r2] Adding initial lab 5 source diff -r 6d1ff93e3afa -r 91a1f76ddd62 common/BranchPred.bsv --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/common/BranchPred.bsv Tue Apr 13 17:34:33 2010 -0400 @@ -0,0 +1,41 @@ +import RegFile::*; +import ProcTypes::*; +import FIFO::*; + +typedef Maybe#(Addr) BrPred; +typedef Bit#(4) BPindx; + +typedef struct {Addr brpc; Addr nextpc;} BrPair deriving (Bits,Eq); + +typedef union tagged +{ + BrPair Valid; + void Invalid; +} CBranchPath deriving(Bits, Eq); // have the cache start out invalid and add valid values. + +interface BranchPred; + method BrPred get(Addr pres); //returns a maybe type that is invalid if no predition + method Action upd(Addr pres, Addr next); +endinterface + +module mkBranchPred(BranchPred); + + //state variables + RegFile#(BPindx, CBranchPath) bcache <- mkRegFileFull(); // cache to hold 16 (based on BPindx) + + method Action upd(Addr pres, Addr next); + BrPair brp; + brp = BrPair {brpc:pres, nextpc:next}; + bcache.upd(pres[5:2], tagged Valid brp); + endmethod + + method BrPred get(Addr prespc); + BPindx rd = prespc[5:2]; + let cbp = bcache.sub(rd); + if (cbp matches tagged Valid .bp &&& bp.brpc == prespc) //make sure that the read value was actually put there and the full address matches + return tagged Valid bp.nextpc; + else return Invalid; + endmethod + +endmodule + diff -r 6d1ff93e3afa -r 91a1f76ddd62 common/InterfaceTypes.bsv --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/common/InterfaceTypes.bsv Tue Apr 13 17:34:33 2010 -0400 @@ -0,0 +1,28 @@ +import Trace::*; + +`define MAX_VOICES 4 +`define MAX_CORES 16 +`define MAX_PATH_LENGTH 8 + +// The path is hardwired and so should never be stored in a register. Therefore int type rather than Bit type + +typedef Bit#(32) MemAddr; +typedef Int#(TLog#(MAX_CORES+2)) PathId; + +//The mixer is identified as PathId 0, path end is max +PathId mixerId = 0; +PathId endId = MAX_CORES+1; + +// Path is array of path ids +typedef Vector#(MAX_PATH_LENGTH, PathId) CorePath; +typedef struct +{ + MemAddr startAddr; + CorePath route; + } FullPath deriving(Eq, Bits); + +Vector#(MAX_VOICES, FullPath) routeTable; +routeTable[0] = {startAddr: 12, route: {1, 2, 3, 0, endId, endId, endId, endId}} + + + diff -r 6d1ff93e3afa -r 91a1f76ddd62 common/ProcTypes.bsv --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/common/ProcTypes.bsv Tue Apr 13 17:34:33 2010 -0400 @@ -0,0 +1,375 @@ + +import Trace::*; + +//---------------------------------------------------------------------- +// Other typedefs +//---------------------------------------------------------------------- + +typedef Bit#(32) Addr; +typedef Int#(18) Stat; + +//---------------------------------------------------------------------- +// Basic instruction type +//---------------------------------------------------------------------- + +typedef Bit#(5) Rindx; +typedef Bit#(16) Simm; +typedef Bit#(16) Zimm; +typedef Bit#(8) Epoch; +typedef Bit#(5) Shamt; +typedef Bit#(26) Target; +typedef Bit#(5) CP0indx; +typedef Bit#(32) Data; + +typedef enum +{ + Taken, + NotTaken +} + Direction + deriving(Bits,Eq); + + +//---------------------------------------------------------------------- +// Pipeline typedefs +//---------------------------------------------------------------------- + +typedef union tagged +{ + Tuple2#(Rindx,Data) ALUWB; + Rindx MemWB; + Tuple2#(Rindx,Data) CoWB; +} + WritebackType + deriving(Bits,Eq); + +//////////////////////// +// I Add Writeback queue type +//////////// +typedef union tagged +{ + struct {Bit#(32) data; Rindx dest; } WB_ALU; + Bit#(32) WB_Host; + Rindx WB_Load; + void WB_Store; +} +WBResult deriving(Eq, Bits); + +//typedef struct{Addr qpc; Addr qnxtpc; Epoch qepoch;} PCStat deriving(Eq, Bits); +typedef struct{Addr qpc; Epoch qepoch;} PCStat deriving(Eq, Bits); + +typedef union tagged +{ + + struct { Rindx rbase; Rindx rdst; Simm offset; } LW; + struct { Rindx rbase; Rindx rsrc; Simm offset; } SW; + + struct { Rindx rsrc; Rindx rdst; Simm imm; } ADDIU; + struct { Rindx rsrc; Rindx rdst; Simm imm; } SLTI; + struct { Rindx rsrc; Rindx rdst; Simm imm; } SLTIU; + struct { Rindx rsrc; Rindx rdst; Zimm imm; } ANDI; + struct { Rindx rsrc; Rindx rdst; Zimm imm; } ORI; + struct { Rindx rsrc; Rindx rdst; Zimm imm; } XORI; + struct { Rindx rdst; Zimm imm; } LUI; + + struct { Rindx rsrc; Rindx rdst; Shamt shamt; } SLL; + struct { Rindx rsrc; Rindx rdst; Shamt shamt; } SRL; + struct { Rindx rsrc; Rindx rdst; Shamt shamt; } SRA; + struct { Rindx rsrc; Rindx rdst; Rindx rshamt; } SLLV; + struct { Rindx rsrc; Rindx rdst; Rindx rshamt; } SRLV; + struct { Rindx rsrc; Rindx rdst; Rindx rshamt; } SRAV; + struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } ADDU; + struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } SUBU; + struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } AND; + struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } OR; + struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } XOR; + struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } NOR; + struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } SLT; + struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } SLTU; + + struct { Target target; } J; + struct { Target target; } JAL; + struct { Rindx rsrc; } JR; + struct { Rindx rsrc; Rindx rdst; } JALR; + struct { Rindx rsrc1; Rindx rsrc2; Simm offset; } BEQ; + struct { Rindx rsrc1; Rindx rsrc2; Simm offset; } BNE; + struct { Rindx rsrc; Simm offset; } BLEZ; + struct { Rindx rsrc; Simm offset; } BGTZ; + struct { Rindx rsrc; Simm offset; } BLTZ; + struct { Rindx rsrc; Simm offset; } BGEZ; + + struct { Rindx rdst; CP0indx cop0src; } MFC0; + struct { Rindx rsrc; CP0indx cop0dst; } MTC0; + + void ILLEGAL; + +} +Instr deriving(Eq); + +//---------------------------------------------------------------------- +// Pack and Unpack +//---------------------------------------------------------------------- + +Bit#(6) opFUNC = 6'b000000; Bit#(6) fcSLL = 6'b000000; +Bit#(6) opRT = 6'b000001; Bit#(6) fcSRL = 6'b000010; +Bit#(6) opRS = 6'b010000; Bit#(6) fcSRA = 6'b000011; + Bit#(6) fcSLLV = 6'b000100; +Bit#(6) opLW = 6'b100011; Bit#(6) fcSRLV = 6'b000110; +Bit#(6) opSW = 6'b101011; Bit#(6) fcSRAV = 6'b000111; + Bit#(6) fcADDU = 6'b100001; +Bit#(6) opADDIU = 6'b001001; Bit#(6) fcSUBU = 6'b100011; +Bit#(6) opSLTI = 6'b001010; Bit#(6) fcAND = 6'b100100; +Bit#(6) opSLTIU = 6'b001011; Bit#(6) fcOR = 6'b100101; +Bit#(6) opANDI = 6'b001100; Bit#(6) fcXOR = 6'b100110; +Bit#(6) opORI = 6'b001101; Bit#(6) fcNOR = 6'b100111; +Bit#(6) opXORI = 6'b001110; Bit#(6) fcSLT = 6'b101010; +Bit#(6) opLUI = 6'b001111; Bit#(6) fcSLTU = 6'b101011; + +Bit#(6) opJ = 6'b000010; +Bit#(6) opJAL = 6'b000011; +Bit#(6) fcJR = 6'b001000; +Bit#(6) fcJALR = 6'b001001; +Bit#(6) opBEQ = 6'b000100; +Bit#(6) opBNE = 6'b000101; +Bit#(6) opBLEZ = 6'b000110; +Bit#(6) opBGTZ = 6'b000111; +Bit#(5) rtBLTZ = 5'b00000; +Bit#(5) rtBGEZ = 5'b00001; + +Bit#(5) rsMFC0 = 5'b00000; +Bit#(5) rsMTC0 = 5'b00100; + +instance Bits#(Instr,32); + + // Pack Function + + function Bit#(32) pack( Instr instr ); + + case ( instr ) matches + + tagged LW .it : return { opLW, it.rbase, it.rdst, it.offset }; + tagged SW .it : return { opSW, it.rbase, it.rsrc, it.offset }; + + tagged ADDIU .it : return { opADDIU, it.rsrc, it.rdst, it.imm }; + tagged SLTI .it : return { opSLTI, it.rsrc, it.rdst, it.imm }; + tagged SLTIU .it : return { opSLTIU, it.rsrc, it.rdst, it.imm }; + tagged ANDI .it : return { opANDI, it.rsrc, it.rdst, it.imm }; + tagged ORI .it : return { opORI, it.rsrc, it.rdst, it.imm }; + tagged XORI .it : return { opXORI, it.rsrc, it.rdst, it.imm }; + tagged LUI .it : return { opLUI, 5'b0, it.rdst, it.imm }; + + tagged SLL .it : return { opFUNC, 5'b0, it.rsrc, it.rdst, it.shamt, fcSLL }; + tagged SRL .it : return { opFUNC, 5'b0, it.rsrc, it.rdst, it.shamt, fcSRL }; + tagged SRA .it : return { opFUNC, 5'b0, it.rsrc, it.rdst, it.shamt, fcSRA }; + + tagged SLLV .it : return { opFUNC, it.rshamt, it.rsrc, it.rdst, 5'b0, fcSLLV }; + tagged SRLV .it : return { opFUNC, it.rshamt, it.rsrc, it.rdst, 5'b0, fcSRLV }; + tagged SRAV .it : return { opFUNC, it.rshamt, it.rsrc, it.rdst, 5'b0, fcSRAV }; + + tagged ADDU .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcADDU }; + tagged SUBU .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcSUBU }; + tagged AND .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcAND }; + tagged OR .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcOR }; + tagged XOR .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcXOR }; + tagged NOR .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcNOR }; + tagged SLT .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcSLT }; + tagged SLTU .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcSLTU }; + + tagged J .it : return { opJ, it.target }; + tagged JAL .it : return { opJAL, it.target }; + tagged JR .it : return { opFUNC, it.rsrc, 5'b0, 5'b0, 5'b0, fcJR }; + tagged JALR .it : return { opFUNC, it.rsrc, 5'b0, it.rdst, 5'b0, fcJALR }; + tagged BEQ .it : return { opBEQ, it.rsrc1, it.rsrc2, it.offset }; + tagged BNE .it : return { opBNE, it.rsrc1, it.rsrc2, it.offset }; + tagged BLEZ .it : return { opBLEZ, it.rsrc, 5'b0, it.offset }; + tagged BGTZ .it : return { opBGTZ, it.rsrc, 5'b0, it.offset }; + tagged BLTZ .it : return { opRT, it.rsrc, rtBLTZ, it.offset }; + tagged BGEZ .it : return { opRT, it.rsrc, rtBGEZ, it.offset }; + + tagged MFC0 .it : return { opRS, rsMFC0, it.rdst, it.cop0src, 11'b0 }; + tagged MTC0 .it : return { opRS, rsMTC0, it.rsrc, it.cop0dst, 11'b0 }; + + endcase + + endfunction + + // Unpack Function + + function Instr unpack( Bit#(32) instrBits ); + + let opcode = instrBits[ 31 : 26 ]; + let rs = instrBits[ 25 : 21 ]; + let rt = instrBits[ 20 : 16 ]; + let rd = instrBits[ 15 : 11 ]; + let shamt = instrBits[ 10 : 6 ]; + let funct = instrBits[ 5 : 0 ]; + let imm = instrBits[ 15 : 0 ]; + let target = instrBits[ 25 : 0 ]; + + case ( opcode ) + + opLW : return LW { rbase:rs, rdst:rt, offset:imm }; + opSW : return SW { rbase:rs, rsrc:rt, offset:imm }; + opADDIU : return ADDIU { rsrc:rs, rdst:rt, imm:imm }; + opSLTI : return SLTI { rsrc:rs, rdst:rt, imm:imm }; + opSLTIU : return SLTIU { rsrc:rs, rdst:rt, imm:imm }; + opANDI : return ANDI { rsrc:rs, rdst:rt, imm:imm }; + opORI : return ORI { rsrc:rs, rdst:rt, imm:imm }; + opXORI : return XORI { rsrc:rs, rdst:rt, imm:imm }; + opLUI : return LUI { rdst:rt, imm:imm }; + opJ : return J { target:target }; + opJAL : return JAL { target:target }; + opBEQ : return BEQ { rsrc1:rs, rsrc2:rt, offset:imm }; + opBNE : return BNE { rsrc1:rs, rsrc2:rt, offset:imm }; + opBLEZ : return BLEZ { rsrc:rs, offset:imm }; + opBGTZ : return BGTZ { rsrc:rs, offset:imm }; + + opFUNC : + case ( funct ) + fcSLL : return SLL { rsrc:rt, rdst:rd, shamt:shamt }; + fcSRL : return SRL { rsrc:rt, rdst:rd, shamt:shamt }; + fcSRA : return SRA { rsrc:rt, rdst:rd, shamt:shamt }; + fcSLLV : return SLLV { rsrc:rt, rdst:rd, rshamt:rs }; + fcSRLV : return SRLV { rsrc:rt, rdst:rd, rshamt:rs }; + fcSRAV : return SRAV { rsrc:rt, rdst:rd, rshamt:rs }; + fcADDU : return ADDU { rsrc1:rs, rsrc2:rt, rdst:rd }; + fcSUBU : return SUBU { rsrc1:rs, rsrc2:rt, rdst:rd }; + fcAND : return AND { rsrc1:rs, rsrc2:rt, rdst:rd }; + fcOR : return OR { rsrc1:rs, rsrc2:rt, rdst:rd }; + fcXOR : return XOR { rsrc1:rs, rsrc2:rt, rdst:rd }; + fcNOR : return NOR { rsrc1:rs, rsrc2:rt, rdst:rd }; + fcSLT : return SLT { rsrc1:rs, rsrc2:rt, rdst:rd }; + fcSLTU : return SLTU { rsrc1:rs, rsrc2:rt, rdst:rd }; + fcJR : return JR { rsrc:rs }; + fcJALR : return JALR { rsrc:rs, rdst:rd }; + default : return ILLEGAL; + endcase + + opRT : + case ( rt ) + rtBLTZ : return BLTZ { rsrc:rs, offset:imm }; + rtBGEZ : return BGEZ { rsrc:rs, offset:imm }; + default : return ILLEGAL; + endcase + + opRS : + case ( rs ) + rsMFC0 : return MFC0 { rdst:rt, cop0src:rd }; + rsMTC0 : return MTC0 { rsrc:rt, cop0dst:rd }; + default : return ILLEGAL; + endcase + + default : return ILLEGAL; + + endcase + + endfunction + +endinstance + +//---------------------------------------------------------------------- +// Trace +//---------------------------------------------------------------------- + +instance Traceable#(Instr); + + function Action traceTiny( String loc, String ttag, Instr inst ); + case ( inst ) matches + + tagged LW .it : $fdisplay(stderr, " => %s:%s lw", loc, ttag ); + tagged SW .it : $fdisplay(stderr, " => %s:%s sw", loc, ttag ); + + tagged ADDIU .it : $fdisplay(stderr, " => %s:%s addi", loc, ttag ); + tagged SLTI .it : $fdisplay(stderr, " => %s:%s sli", loc, ttag ); + tagged SLTIU .it : $fdisplay(stderr, " => %s:%s sliu", loc, ttag ); + tagged ANDI .it : $fdisplay(stderr, " => %s:%s andi", loc, ttag ); + tagged ORI .it : $fdisplay(stderr, " => %s:%s ori", loc, ttag ); + tagged XORI .it : $fdisplay(stderr, " => %s:%s xori", loc, ttag ); + tagged LUI .it : $fdisplay(stderr, " => %s:%s lui", loc, ttag ); + + tagged SLL .it : $fdisplay(stderr, " => %s:%s sll", loc, ttag ); + tagged SRL .it : $fdisplay(stderr, " => %s:%s srl", loc, ttag ); + tagged SRA .it : $fdisplay(stderr, " => %s:%s sra", loc, ttag ); + tagged SLLV .it : $fdisplay(stderr, " => %s:%s sllv", loc, ttag ); + tagged SRLV .it : $fdisplay(stderr, " => %s:%s srlv", loc, ttag ); + tagged SRAV .it : $fdisplay(stderr, " => %s:%s srav", loc, ttag ); + + tagged ADDU .it : $fdisplay(stderr, " => %s:%s addu", loc, ttag ); + tagged SUBU .it : $fdisplay(stderr, " => %s:%s subu", loc, ttag ); + tagged AND .it : $fdisplay(stderr, " => %s:%s and", loc, ttag ); + tagged OR .it : $fdisplay(stderr, " => %s:%s or", loc, ttag ); + tagged XOR .it : $fdisplay(stderr, " => %s:%s xor", loc, ttag ); + tagged NOR .it : $fdisplay(stderr, " => %s:%s nor", loc, ttag ); + tagged SLT .it : $fdisplay(stderr, " => %s:%s slt", loc, ttag ); + tagged SLTU .it : $fdisplay(stderr, " => %s:%s sltu", loc, ttag ); + + tagged J .it : $fdisplay(stderr, " => %s:%s j", loc, ttag ); + tagged JAL .it : $fdisplay(stderr, " => %s:%s jal", loc, ttag ); + tagged JR .it : $fdisplay(stderr, " => %s:%s jr", loc, ttag ); + tagged JALR .it : $fdisplay(stderr, " => %s:%s jalr", loc, ttag ); + tagged BEQ .it : $fdisplay(stderr, " => %s:%s beq", loc, ttag ); + tagged BNE .it : $fdisplay(stderr, " => %s:%s bne", loc, ttag ); + tagged BLEZ .it : $fdisplay(stderr, " => %s:%s blez", loc, ttag ); + tagged BGTZ .it : $fdisplay(stderr, " => %s:%s bgtz", loc, ttag ); + tagged BLTZ .it : $fdisplay(stderr, " => %s:%s bltz", loc, ttag ); + tagged BGEZ .it : $fdisplay(stderr, " => %s:%s bgez", loc, ttag ); + + tagged MFC0 .it : $fdisplay(stderr, " => %s:%s mfc0", loc, ttag ); + tagged MTC0 .it : $fdisplay(stderr, " => %s:%s mtc0", loc, ttag ); + + tagged ILLEGAL : $fdisplay(stderr, " => %s:%s ill", loc, ttag ); + + endcase + endfunction + + function Action traceFull( String loc, String ttag, Instr inst ); + case ( inst ) matches + + tagged LW .it : $fdisplay(stderr, " => %s:%s lw r%0d, 0x%x(r%0d)", loc, ttag, it.rdst, it.offset, it.rbase ); + tagged SW .it : $fdisplay(stderr, " => %s:%s sw r%0d, 0x%x(r%0d)", loc, ttag, it.rsrc, it.offset, it.rbase ); + + tagged ADDIU .it : $fdisplay(stderr, " => %s:%s addiu r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); + tagged SLTI .it : $fdisplay(stderr, " => %s:%s slti r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); + tagged SLTIU .it : $fdisplay(stderr, " => %s:%s sltiu r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); + tagged ANDI .it : $fdisplay(stderr, " => %s:%s andi r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); + tagged ORI .it : $fdisplay(stderr, " => %s:%s ori r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); + tagged XORI .it : $fdisplay(stderr, " => %s:%s xori r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); + tagged LUI .it : $fdisplay(stderr, " => %s:%s lui r%0d, 0x%x", loc, ttag, it.rdst, it.imm ); + + tagged SLL .it : $fdisplay(stderr, " => %s:%s sll r%0d, r%0d, %0d", loc, ttag, it.rdst, it.rsrc, it.shamt ); + tagged SRL .it : $fdisplay(stderr, " => %s:%s srl r%0d, r%0d, %0d", loc, ttag, it.rdst, it.rsrc, it.shamt ); + tagged SRA .it : $fdisplay(stderr, " => %s:%s sra r%0d, r%0d, %0d", loc, ttag, it.rdst, it.rsrc, it.shamt ); + tagged SLLV .it : $fdisplay(stderr, " => %s:%s sllv r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc, it.rshamt ); + tagged SRLV .it : $fdisplay(stderr, " => %s:%s srlv r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc, it.rshamt ); + tagged SRAV .it : $fdisplay(stderr, " => %s:%s srav r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc, it.rshamt ); + + tagged ADDU .it : $fdisplay(stderr, " => %s:%s addu r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); + tagged SUBU .it : $fdisplay(stderr, " => %s:%s subu r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); + tagged AND .it : $fdisplay(stderr, " => %s:%s and r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); + tagged OR .it : $fdisplay(stderr, " => %s:%s or r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); + tagged XOR .it : $fdisplay(stderr, " => %s:%s xor r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); + tagged NOR .it : $fdisplay(stderr, " => %s:%s nor r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); + tagged SLT .it : $fdisplay(stderr, " => %s:%s slt r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); + tagged SLTU .it : $fdisplay(stderr, " => %s:%s sltu r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); + + tagged J .it : $fdisplay(stderr, " => %s:%s j 0x%x", loc, ttag, it.target ); + tagged JAL .it : $fdisplay(stderr, " => %s:%s jal 0x%x", loc, ttag, it.target ); + tagged JR .it : $fdisplay(stderr, " => %s:%s jr r%0d", loc, ttag, it.rsrc ); + tagged JALR .it : $fdisplay(stderr, " => %s:%s jalr r%0d", loc, ttag, it.rsrc ); + tagged BEQ .it : $fdisplay(stderr, " => %s:%s beq r%0d, r%0d, 0x%x", loc, ttag, it.rsrc1, it.rsrc2, it.offset ); + tagged BNE .it : $fdisplay(stderr, " => %s:%s bne r%0d, r%0d, 0x%x", loc, ttag, it.rsrc1, it.rsrc2, it.offset ); + tagged BLEZ .it : $fdisplay(stderr, " => %s:%s blez r%0d, 0x%x", loc, ttag, it.rsrc, it.offset ); + tagged BGTZ .it : $fdisplay(stderr, " => %s:%s bgtz r%0d, 0x%x", loc, ttag, it.rsrc, it.offset ); + tagged BLTZ .it : $fdisplay(stderr, " => %s:%s bltz r%0d, 0x%x", loc, ttag, it.rsrc, it.offset ); + tagged BGEZ .it : $fdisplay(stderr, " => %s:%s bgez r%0d, 0x%x", loc, ttag, it.rsrc, it.offset ); + + tagged MFC0 .it : $fdisplay(stderr, " => %s:%s mfc0 r%0d, cpr%0d", loc, ttag, it.rdst, it.cop0src ); + tagged MTC0 .it : $fdisplay(stderr, " => %s:%s mtc0 r%0d, cpr%0d", loc, ttag, it.rsrc, it.cop0dst ); + + tagged ILLEGAL : $fdisplay(stderr, " => %s:%s illegal instruction", loc, ttag ); + + endcase + endfunction + +endinstance + diff -r 6d1ff93e3afa -r 91a1f76ddd62 core/scemi/Bridge.bsv --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/core/scemi/Bridge.bsv Tue Apr 13 17:34:33 2010 -0400 @@ -0,0 +1,21 @@ +`ifdef SCEMI_PCIE_VIRTEX5 +`ifdef BOARD_ML507 +`include "Bridge_VIRTEX5_ML50X.bsv" +`endif +`ifdef BOARD_XUPV5 +`include "Bridge_VIRTEX5_ML50X.bsv" +`endif +`endif + +`ifdef SCEMI_PCIE_DINI +`ifdef BOARD_7002 +`include "Bridge_DINI_7002.bsv" +`endif +`ifdef BOARD_7006 +`include "Bridge_DINI_7006.bsv" +`endif +`endif + +`ifdef SCEMI_TCP +`include "Bridge_TCP.bsv" +`endif diff -r 6d1ff93e3afa -r 91a1f76ddd62 core/scemi/SceMiLayer.bsv --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/core/scemi/SceMiLayer.bsv Tue Apr 13 17:34:33 2010 -0400 @@ -0,0 +1,150 @@ + +import ClientServer::*; +import FIFO::*; +import GetPut::*; +import DefaultValue::*; +import SceMi::*; +import Clocks::*; + +import Core::*; +import ProcTypes::*; +import Processor::*; +import DataCacheBlocking::*; +import InstCacheBlocking::*; + +interface DutWrapper; + interface Core core; + + // We use a Bit#(1) instead of void because Bluespec Sce-Mi doesn't appear + // to support sending void over the PCIe link yet. + interface Put#(Bit#(1)) doreset; +endinterface + +(* synthesize *) +module [Module] mkDutWrapper (DutWrapper); + + Clock clk <- exposeCurrentClock; + MakeResetIfc myrst <- mkReset(2000, True, clk); + + Core coreifc <- mkCore(reset_by myrst.new_rst); + + // For tracing + Reg#(int) cycle <- mkReg(0); + rule printCycles; + cycle <= cycle + 1; + $fdisplay(stderr, " => Cycle = %d", cycle); + endrule + + interface Core core = coreifc; + + interface Put doreset; + method Action put(Bit#(1) x); + cycle <= 0; + myrst.assertReset(); + endmethod + endinterface + +endmodule + +module [SceMiModule] mkSceMiLayer(); + + SceMiClockConfiguration conf = defaultValue; + + SceMiClockPortIfc clk_port <- mkSceMiClockPort(conf); + DutWrapper dut <- buildDut(mkDutWrapper, clk_port); + + Empty mmem <- mkClientXactor(dut.core.mmem_client, clk_port); + Empty tohost <- mkCPUToHostXactor(dut.core.tohost, clk_port); + Empty stats <- mkCoreStatsXactor(dut.core.stats, clk_port); + Empty doreset <- mkPutXactor(dut.doreset, clk_port); + + Empty shutdown <- mkShutdownXactor(); + +endmodule + +module [SceMiModule] mkCPUToHostXactor#(CPUToHost tohost, SceMiClockPortIfc clk_port ) (Empty); + + // Access the controlled clock and reset + Clock cclock = clk_port.cclock; + Reset creset = clk_port.creset; + + // req belongs entirely to the controlled clock domain. We'll use the + // clock domain crossings already implemented by the Bluespec people (in + // the Put and Get transactors), because they know about such things + // better than I do. + FIFO#(int) req <- mkFIFO(clocked_by cclock, reset_by creset); + + Get#(Bit#(32)) resp = interface Get; + method ActionValue#(Bit#(32)) get(); + req.deq(); + return tohost.cpuToHost(req.first()); + endmethod + endinterface; + + Empty request <- mkPutXactor(toPut(req), clk_port); + Empty response <- mkGetXactor(resp, clk_port); + +endmodule + +typedef enum { + DCACHE_ACCESSES, DCACHE_MISSES, DCACHE_WRITEBACKS, + ICACHE_ACCESSES, ICACHE_MISSES, ICACHE_EVICTIONS, + PROC_INST, PROC_CYCLES +} StatID deriving(Bits, Eq); + +module [SceMiModule] mkCoreStatsXactor#(CoreStats stats, SceMiClockPortIfc clk_port) (Empty); + + // Access the controlled clock and reset + Clock cclock = clk_port.cclock; + Reset creset = clk_port.creset; + + // Again, req and resp belong to the controlled clock domain. + FIFO#(StatID) req <- mkFIFO(clocked_by cclock, reset_by creset); + FIFO#(Stat) resp <- mkFIFO(clocked_by cclock, reset_by creset); + + rule handleRequest (True); + case (req.first()) + DCACHE_ACCESSES: begin + let x <- stats.dcache.num_accesses.get(); + resp.enq(x); + end + DCACHE_MISSES: begin + let x <- stats.dcache.num_misses.get(); + resp.enq(x); + end + DCACHE_WRITEBACKS: begin + let x <- stats.dcache.num_writebacks.get(); + resp.enq(x); + end + ICACHE_ACCESSES: begin + let x <- stats.icache.num_accesses.get(); + resp.enq(x); + end + ICACHE_MISSES: begin + let x <- stats.icache.num_misses.get(); + resp.enq(x); + end + ICACHE_EVICTIONS: begin + let x <- stats.icache.num_evictions.get(); + resp.enq(x); + end + PROC_INST: begin + let x <- stats.proc.num_inst.get(); + resp.enq(x); + end + PROC_CYCLES: begin + let x <- stats.proc.num_cycles.get(); + resp.enq(x); + end + endcase + req.deq(); + endrule + + Server#(StatID, Stat) server = interface Server; + interface Get response = toGet(resp); + interface Put request = toPut(req); + endinterface; + + Empty xx <- mkServerXactor(server, clk_port); +endmodule + diff -r 6d1ff93e3afa -r 91a1f76ddd62 core/sim/bdir_dut/BFIFO.bi --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/core/sim/bdir_dut/BFIFO.bi Tue Apr 13 17:34:33 2010 -0400 @@ -0,0 +1,23 @@ +signature BFIFO where { +import ¶Assert®¶; + +import ¶FIFOF_®¶; + +import ¶FIFOF®¶; + +import ¶FIFO®¶; + +import ¶List®¶; + +BFIFO.mkBFIFO1 :: (¶Prelude®¶.¶Bits®¶ item_t item_sz, ¶Prelude®¶.¶IsModule®¶ _m__ _c__) => + _m__ (¶FIFO®¶.¶FIFO®¶ item_t); + +BFIFO.mkSizedBFIFO :: (¶Prelude®¶.¶Bits®¶ item_t item_sz, ¶Prelude®¶.¶IsModule®¶ _m__ _c__) => + ¶Prelude®¶.¶Integer®¶ -> _m__ (¶FIFO®¶.¶FIFO®¶ item_t); + +BFIFO.mkBFIFOF1 :: (¶Prelude®¶.¶Bits®¶ item_t item_sz, ¶Prelude®¶.¶IsModule®¶ _m__ _c__) => + _m__ (¶FIFOF®¶.¶FIFOF®¶ item_t); + +BFIFO.mkBFIFO_16 :: (¶Prelude®¶.¶IsModule®¶ _m__ _c__) => + _m__ (¶FIFO®¶.¶FIFO®¶ (¶Prelude®¶.¶Bit®¶ 16)) +} diff -r 6d1ff93e3afa -r 91a1f76ddd62 core/sim/bdir_dut/BFIFO.bo Binary file core/sim/bdir_dut/BFIFO.bo has changed diff -r 6d1ff93e3afa -r 91a1f76ddd62 core/sim/bdir_dut/BRegFile.bi --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/core/sim/bdir_dut/BRegFile.bi Tue Apr 13 17:34:33 2010 -0400 @@ -0,0 +1,54 @@ +signature BRegFile where { +import ¶Counter®¶; + +import ¶FIFOF_®¶; + +import ¶FIFOF®¶; + +import ¶FIFO®¶; + +import ¶Inout®¶; + +import ¶List®¶; + +import ¶Clocks®¶; + +import ¶ListN®¶; + +import ¶PrimArray®¶; + +import ¶RWire®¶; + +import ¶RegFile®¶; + +import ¶Vector®¶; + +import ¶Connectable®¶; + +import ¶GetPut®¶; + +import ¶ClientServer®¶; + +import Trace; + +import ProcTypes; + +interface (BRegFile.BRegFile :: * -> * -> *) index_t data_t = { + BRegFile.upd :: index_t -> data_t -> ¶Prelude®¶.¶Action®¶ {-# arg_names = [addr, ¡data¡] #-}; + BRegFile.sub :: index_t -> data_t {-# arg_names = [addr] #-} +}; + +instance BRegFile (¶Prelude®¶.¶PrimMakeUndefined®¶ data_t) => + ¶Prelude®¶.¶PrimMakeUndefined®¶ (BRegFile.BRegFile index_t data_t); + +instance BRegFile ¶Prelude®¶.¶PrimDeepSeqCond®¶ (BRegFile.BRegFile index_t data_t); + +instance BRegFile ¶Prelude®¶.¶PrimMakeUninitialized®¶ (BRegFile.BRegFile index_t data_t); + +BRegFile.mkBRegFile :: (¶Prelude®¶.¶Bounded®¶ index_t, + ¶Prelude®¶.¶Eq®¶ index_t, + ¶Prelude®¶.¶Bits®¶ data_t size_data, + ¶Prelude®¶.¶Bits®¶ index_t size_index, + ¶Prelude®¶.¶IsModule®¶ _m__ _c__) => + _m__ (¶RegFile®¶.¶RegFile®¶ index_t data_t) +} diff -r 6d1ff93e3afa -r 91a1f76ddd62 core/sim/bdir_dut/BRegFile.bo Binary file core/sim/bdir_dut/BRegFile.bo has changed diff -r 6d1ff93e3afa -r 91a1f76ddd62 core/sim/bdir_dut/BranchPred.bi --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/core/sim/bdir_dut/BranchPred.bi Tue Apr 13 17:34:33 2010 -0400 @@ -0,0 +1,78 @@ +signature BranchPred where { +import ¶Counter®¶; + +import ¶FIFOF_®¶; + +import ¶FIFOF®¶; + +import ¶FIFO®¶; + +import ¶Inout®¶; + +import ¶List®¶; + +import ¶Clocks®¶; + +import ¶ListN®¶; + +import ¶PrimArray®¶; + +import ¶RegFile®¶; + +import ¶Vector®¶; + +import ¶Connectable®¶; + +import ¶GetPut®¶; + +import ¶ClientServer®¶; + +import Trace; + +import ProcTypes; + +type (BranchPred.BrPred :: *) = ¶Prelude®¶.¶Maybe®¶ ProcTypes.Addr; + +type (BranchPred.BPindx :: *) = ¶Prelude®¶.¶Bit®¶ 4; + +struct (BranchPred.BrPair :: *) = { + BranchPred.brpc :: ProcTypes.Addr; + BranchPred.nextpc :: ProcTypes.Addr +}; + +instance BranchPred ¶Prelude®¶.¶PrimMakeUndefined®¶ BranchPred.BrPair; + +instance BranchPred ¶Prelude®¶.¶PrimDeepSeqCond®¶ BranchPred.BrPair; + +instance BranchPred ¶Prelude®¶.¶PrimMakeUninitialized®¶ BranchPred.BrPair; + +instance BranchPred ¶Prelude®¶.¶Bits®¶ BranchPred.BrPair 64; + +instance BranchPred ¶Prelude®¶.¶Eq®¶ BranchPred.BrPair; + +data (BranchPred.CBranchPath :: *) = BranchPred.Valid BranchPred.BrPair | BranchPred.Invalid (); + +instance BranchPred ¶Prelude®¶.¶PrimMakeUndefined®¶ BranchPred.CBranchPath; + +instance BranchPred ¶Prelude®¶.¶PrimDeepSeqCond®¶ BranchPred.CBranchPath; + +instance BranchPred ¶Prelude®¶.¶PrimMakeUninitialized®¶ BranchPred.CBranchPath; + +instance BranchPred ¶Prelude®¶.¶Bits®¶ BranchPred.CBranchPath 65; + +instance BranchPred ¶Prelude®¶.¶Eq®¶ BranchPred.CBranchPath; + +interface (BranchPred.BranchPred :: *) = { + BranchPred.get :: ProcTypes.Addr -> BranchPred.BrPred {-# arg_names = [pres] #-}; + BranchPred.upd :: ProcTypes.Addr -> ProcTypes.Addr -> ¶Prelude®¶.¶Action®¶ {-# arg_names = [pres, + next] #-} +}; + +instance BranchPred ¶Prelude®¶.¶PrimMakeUndefined®¶ BranchPred.BranchPred; + +instance BranchPred ¶Prelude®¶.¶PrimDeepSeqCond®¶ BranchPred.BranchPred; + +instance BranchPred ¶Prelude®¶.¶PrimMakeUninitialized®¶ BranchPred.BranchPred; + +BranchPred.mkBranchPred :: (¶Prelude®¶.¶IsModule®¶ _m__ _c__) => _m__ BranchPred.BranchPred +} diff -r 6d1ff93e3afa -r 91a1f76ddd62 core/sim/bdir_dut/BranchPred.bo Binary file core/sim/bdir_dut/BranchPred.bo has changed diff -r 6d1ff93e3afa -r 91a1f76ddd62 core/sim/bdir_dut/Bridge.bi --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/core/sim/bdir_dut/Bridge.bi Tue Apr 13 17:34:33 2010 -0400 @@ -0,0 +1,137 @@ +signature Bridge where { +import ¶Assert®¶; + +import ¶ConfigReg®¶; + +import ¶Counter®¶; + +import ¶DReg®¶; + +import ¶EdgeDetect®¶; + +import ¶FIFOF_®¶; + +import ¶FIFOF®¶; + +import ¶FIFO®¶; + +import ¶HList®¶; + +import ¶Inout®¶; + +import ¶List®¶; + +import BFIFO; + +import ¶Clocks®¶; + +import ¶DiniPCIE®¶; + +import ¶ListN®¶; + +import ¶ModuleContextCore®¶; + +import ¶ModuleContext®¶; + +import ¶Monad®¶; + +import ¶PrimArray®¶; + +import ¶RWire®¶; + +import ¶RegFile®¶; + +import ¶Real®¶; + +import ¶RevertingVirtualReg®¶; + +import ¶Reserved®¶; + +import SFIFO; + +import ¶Vector®¶; + +import ¶BRAMCore®¶; + +import ¶BUtils®¶; + +import ¶Connectable®¶; + +import ¶DefaultValue®¶; + +import ¶Gearbox®¶; + +import ¶GetPut®¶; + +import ¶AlignedFIFOs®¶; + +import ¶ClientServer®¶; + +import ¶FIFOLevel®¶; + +import ¶SceMiDefines®¶; + +import ¶SceMiProxies®¶; + +import ¶SpecialFIFOs®¶; + +import ¶SceMiInternals®¶; + +import ¶SceMiAldecMacros®¶; + +import ¶SceMiEveMacros®¶; + +import ¶SceMiMacros®¶; + +import ¶TieOff®¶; + +import Trace; + +import MemTypes; + +import MemArb; + +import ProcTypes; + +import BRegFile; + +import BranchPred; + +import DataCacheBlocking; + +import InstCacheBlocking; + +import Processor; + +import Core; + +import ¶UnitAppendList®¶; + +import ¶XilinxCells®¶; + +import ¶SceMiClocks®¶; + +import ¶SceMiDiniPCIE®¶; + +import ¶SceMiTCP®¶; + +import ¶XilinxPCIE®¶; + +import ¶SceMiVirtex5PCIE®¶; + +import ¶SceMiPCIE®¶; + +import ¶SceMiCore®¶; + +import ¶SceMiXactors®¶; + +import ¶SceMiSerialProbe®¶; + +import ¶SceMi®¶; + +import SceMiLayer; + +Bridge.lt :: ¶SceMiDefines®¶.¶SceMiLinkType®¶; + +Bridge.mkBridge :: (¶Prelude®¶.¶IsModule®¶ _m__ _c__) => _m__ ¶Prelude®¶.¶Empty®¶ +} diff -r 6d1ff93e3afa -r 91a1f76ddd62 core/sim/bdir_dut/Bridge.bo Binary file core/sim/bdir_dut/Bridge.bo has changed diff -r 6d1ff93e3afa -r 91a1f76ddd62 core/sim/bdir_dut/Core.bi --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/core/sim/bdir_dut/Core.bi Tue Apr 13 17:34:33 2010 -0400 @@ -0,0 +1,85 @@ +signature Core where { +import ¶Assert®¶; + +import ¶ConfigReg®¶; + +import ¶Counter®¶; + +import ¶FIFOF_®¶; + +import ¶FIFOF®¶; + +import ¶FIFO®¶; + +import ¶Inout®¶; + +import ¶List®¶; + +import BFIFO; + +import ¶Clocks®¶; + +import ¶ListN®¶; + +import ¶Monad®¶; + +import ¶PrimArray®¶; + +import ¶RWire®¶; + +import ¶RegFile®¶; + +import SFIFO; + +import ¶Vector®¶; + +import ¶Connectable®¶; + +import ¶GetPut®¶; + +import ¶ClientServer®¶; + +import Trace; + +import MemTypes; + +import MemArb; + +import ProcTypes; + +import BRegFile; + +import BranchPred; + +import DataCacheBlocking; + +import InstCacheBlocking; + +import Processor; + +interface (Core.CoreStats :: *) = { + Core.dcache :: DataCacheBlocking.DCacheStats; + Core.icache :: InstCacheBlocking.ICacheStats; + Core.proc :: Processor.ProcStats +}; + +instance Core ¶Prelude®¶.¶PrimMakeUndefined®¶ Core.CoreStats; + +instance Core ¶Prelude®¶.¶PrimDeepSeqCond®¶ Core.CoreStats; + +instance Core ¶Prelude®¶.¶PrimMakeUninitialized®¶ Core.CoreStats; + +interface (Core.Core :: *) = { + Core.mmem_client :: ¶ClientServer®¶.¶Client®¶ MemTypes.MainMemReq MemTypes.MainMemResp; + Core.stats :: Core.CoreStats; + Core.tohost :: Processor.CPUToHost +}; + +instance Core ¶Prelude®¶.¶PrimMakeUndefined®¶ Core.Core; + +instance Core ¶Prelude®¶.¶PrimDeepSeqCond®¶ Core.Core; + +instance Core ¶Prelude®¶.¶PrimMakeUninitialized®¶ Core.Core; + +Core.mkCore :: (¶Prelude®¶.¶IsModule®¶ _m__ _c__) => _m__ Core.Core +} diff -r 6d1ff93e3afa -r 91a1f76ddd62 core/sim/bdir_dut/Core.bo Binary file core/sim/bdir_dut/Core.bo has changed diff -r 6d1ff93e3afa -r 91a1f76ddd62 core/sim/bdir_dut/DataCacheBlocking.bi --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/core/sim/bdir_dut/DataCacheBlocking.bi Tue Apr 13 17:34:33 2010 -0400 @@ -0,0 +1,106 @@ +signature DataCacheBlocking where { +import ¶Assert®¶; + +import ¶Counter®¶; + +import ¶FIFOF_®¶; + +import ¶FIFOF®¶; + +import ¶FIFO®¶; + +import ¶Inout®¶; + +import ¶List®¶; + +import BFIFO; + +import ¶Clocks®¶; + +import ¶ListN®¶; + +import ¶PrimArray®¶; + +import ¶RegFile®¶; + +import ¶Vector®¶; + +import ¶Connectable®¶; + +import ¶GetPut®¶; + +import ¶ClientServer®¶; + +import Trace; + +import MemTypes; + +import ProcTypes; + +interface (DataCacheBlocking.DCacheStats :: *) = { + DataCacheBlocking.num_accesses :: ¶GetPut®¶.¶Get®¶ ProcTypes.Stat; + DataCacheBlocking.num_misses :: ¶GetPut®¶.¶Get®¶ ProcTypes.Stat; + DataCacheBlocking.num_writebacks :: ¶GetPut®¶.¶Get®¶ ProcTypes.Stat +}; + +instance DataCacheBlocking ¶Prelude®¶.¶PrimMakeUndefined®¶ DataCacheBlocking.DCacheStats; + +instance DataCacheBlocking ¶Prelude®¶.¶PrimDeepSeqCond®¶ DataCacheBlocking.DCacheStats; + +instance DataCacheBlocking ¶Prelude®¶.¶PrimMakeUninitialized®¶ DataCacheBlocking.DCacheStats; + +interface (DataCacheBlocking.DCache :: * -> * -> *) req_t resp_t = { + DataCacheBlocking.proc_server :: ¶ClientServer®¶.¶Server®¶ req_t resp_t; + DataCacheBlocking.mmem_client :: ¶ClientServer®¶.¶Client®¶ MemTypes.MainMemReq MemTypes.MainMemResp; + DataCacheBlocking.statsEn_put :: ¶GetPut®¶.¶Put®¶ ¶Prelude®¶.¶Bool®¶; + DataCacheBlocking.stats :: DataCacheBlocking.DCacheStats +}; + +instance DataCacheBlocking (¶Prelude®¶.¶PrimMakeUndefined®¶ resp_t) => + ¶Prelude®¶.¶PrimMakeUndefined®¶ (DataCacheBlocking.DCache req_t resp_t); + +instance DataCacheBlocking (¶Prelude®¶.¶PrimDeepSeqCond®¶ resp_t) => + ¶Prelude®¶.¶PrimDeepSeqCond®¶ (DataCacheBlocking.DCache req_t resp_t); + +instance DataCacheBlocking ¶Prelude®¶.¶PrimMakeUninitialized®¶ + (DataCacheBlocking.DCache req_t resp_t); + +type (DataCacheBlocking.CacheLineIndexSz :: #) = 10; + +type (DataCacheBlocking.CacheLineTagSz :: #) = 20; + +type (DataCacheBlocking.CacheLineSz :: #) = 32; + +type (DataCacheBlocking.CacheLineIndex :: *) = ¶Prelude®¶.¶Bit®¶ DataCacheBlocking.CacheLineIndexSz; + +type (DataCacheBlocking.CacheLineTag :: *) = ¶Prelude®¶.¶Bit®¶ DataCacheBlocking.CacheLineTagSz; + +type (DataCacheBlocking.CacheLine :: *) = ¶Prelude®¶.¶Bit®¶ DataCacheBlocking.CacheLineSz; + +data (DataCacheBlocking.CacheStage :: *) = + DataCacheBlocking.Init () | + DataCacheBlocking.Access () | + DataCacheBlocking.RefillReq () | + DataCacheBlocking.RefillResp (); + +instance DataCacheBlocking ¶Prelude®¶.¶PrimMakeUndefined®¶ DataCacheBlocking.CacheStage; + +instance DataCacheBlocking ¶Prelude®¶.¶PrimDeepSeqCond®¶ DataCacheBlocking.CacheStage; + +instance DataCacheBlocking ¶Prelude®¶.¶PrimMakeUninitialized®¶ DataCacheBlocking.CacheStage; + +instance DataCacheBlocking ¶Prelude®¶.¶Eq®¶ DataCacheBlocking.CacheStage; + +instance DataCacheBlocking ¶Prelude®¶.¶Bits®¶ DataCacheBlocking.CacheStage 2; + +DataCacheBlocking.getAddr :: MemTypes.DataReq -> ¶Prelude®¶.¶Bit®¶ MemTypes.AddrSz; + +DataCacheBlocking.getCacheLineIndex :: MemTypes.DataReq -> DataCacheBlocking.CacheLineIndex; + +DataCacheBlocking.getCacheLineTag :: MemTypes.DataReq -> DataCacheBlocking.CacheLineTag; + +DataCacheBlocking.getCacheLineAddr :: MemTypes.DataReq -> ¶Prelude®¶.¶Bit®¶ MemTypes.AddrSz; + +DataCacheBlocking.mkDataCache :: (¶Prelude®¶.¶IsModule®¶ _m__ _c__) => + _m__ (DataCacheBlocking.DCache MemTypes.DataReq MemTypes.DataResp) +} diff -r 6d1ff93e3afa -r 91a1f76ddd62 core/sim/bdir_dut/DataCacheBlocking.bo Binary file core/sim/bdir_dut/DataCacheBlocking.bo has changed diff -r 6d1ff93e3afa -r 91a1f76ddd62 core/sim/bdir_dut/InstCacheBlocking.bi --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/core/sim/bdir_dut/InstCacheBlocking.bi Tue Apr 13 17:34:33 2010 -0400 @@ -0,0 +1,109 @@ +signature InstCacheBlocking where { +import ¶Assert®¶; + +import ¶Counter®¶; + +import ¶FIFOF_®¶; + +import ¶FIFOF®¶; + +import ¶FIFO®¶; + +import ¶Inout®¶; + +import ¶List®¶; + +import BFIFO; + +import ¶Clocks®¶; + +import ¶ListN®¶; + +import ¶PrimArray®¶; + +import ¶RWire®¶; + +import ¶RegFile®¶; + +import ¶Vector®¶; + +import ¶Connectable®¶; + +import ¶GetPut®¶; + +import ¶ClientServer®¶; + +import Trace; + +import MemTypes; + +import ProcTypes; + +interface (InstCacheBlocking.ICacheStats :: *) = { + InstCacheBlocking.num_accesses :: ¶GetPut®¶.¶Get®¶ ProcTypes.Stat; + InstCacheBlocking.num_misses :: ¶GetPut®¶.¶Get®¶ ProcTypes.Stat; + InstCacheBlocking.num_evictions :: ¶GetPut®¶.¶Get®¶ ProcTypes.Stat +}; + +instance InstCacheBlocking ¶Prelude®¶.¶PrimMakeUndefined®¶ InstCacheBlocking.ICacheStats; + +instance InstCacheBlocking ¶Prelude®¶.¶PrimDeepSeqCond®¶ InstCacheBlocking.ICacheStats; + +instance InstCacheBlocking ¶Prelude®¶.¶PrimMakeUninitialized®¶ InstCacheBlocking.ICacheStats; + +interface (InstCacheBlocking.ICache :: * -> * -> *) req_t resp_t = { + InstCacheBlocking.proc_server :: ¶ClientServer®¶.¶Server®¶ req_t resp_t; + InstCacheBlocking.mmem_client :: ¶ClientServer®¶.¶Client®¶ MemTypes.MainMemReq MemTypes.MainMemResp; + InstCacheBlocking.statsEn_put :: ¶GetPut®¶.¶Put®¶ ¶Prelude®¶.¶Bool®¶; + InstCacheBlocking.stats :: InstCacheBlocking.ICacheStats +}; + +instance InstCacheBlocking (¶Prelude®¶.¶PrimMakeUndefined®¶ resp_t) => + ¶Prelude®¶.¶PrimMakeUndefined®¶ (InstCacheBlocking.ICache req_t resp_t); + +instance InstCacheBlocking (¶Prelude®¶.¶PrimDeepSeqCond®¶ resp_t) => + ¶Prelude®¶.¶PrimDeepSeqCond®¶ (InstCacheBlocking.ICache req_t resp_t); + +instance InstCacheBlocking ¶Prelude®¶.¶PrimMakeUninitialized®¶ + (InstCacheBlocking.ICache req_t resp_t); + +type (InstCacheBlocking.CacheLineIndexSz :: #) = 10; + +type (InstCacheBlocking.CacheLineTagSz :: #) = 20; + +type (InstCacheBlocking.CacheLineSz :: #) = 32; + +type (InstCacheBlocking.CacheLineIndex :: *) = ¶Prelude®¶.¶Bit®¶ InstCacheBlocking.CacheLineIndexSz; + +type (InstCacheBlocking.CacheLineTag :: *) = ¶Prelude®¶.¶Bit®¶ InstCacheBlocking.CacheLineTagSz; + +type (InstCacheBlocking.CacheLine :: *) = ¶Prelude®¶.¶Bit®¶ InstCacheBlocking.CacheLineSz; + +data (InstCacheBlocking.CacheStage :: *) = + InstCacheBlocking.Init () | + InstCacheBlocking.Access () | + InstCacheBlocking.Evict () | + InstCacheBlocking.RefillReq () | + InstCacheBlocking.RefillResp (); + +instance InstCacheBlocking ¶Prelude®¶.¶PrimMakeUndefined®¶ InstCacheBlocking.CacheStage; + +instance InstCacheBlocking ¶Prelude®¶.¶PrimDeepSeqCond®¶ InstCacheBlocking.CacheStage; + +instance InstCacheBlocking ¶Prelude®¶.¶PrimMakeUninitialized®¶ InstCacheBlocking.CacheStage; + +instance InstCacheBlocking ¶Prelude®¶.¶Eq®¶ InstCacheBlocking.CacheStage; + +instance InstCacheBlocking ¶Prelude®¶.¶Bits®¶ InstCacheBlocking.CacheStage 3; + +InstCacheBlocking.getAddr :: MemTypes.InstReq -> ¶Prelude®¶.¶Bit®¶ MemTypes.AddrSz; + +InstCacheBlocking.getCacheLineIndex :: MemTypes.InstReq -> InstCacheBlocking.CacheLineIndex; + +InstCacheBlocking.getCacheLineTag :: MemTypes.InstReq -> InstCacheBlocking.CacheLineTag; + +InstCacheBlocking.getCacheLineAddr :: MemTypes.InstReq -> ¶Prelude®¶.¶Bit®¶ MemTypes.AddrSz; + +InstCacheBlocking.mkInstCache :: (¶Prelude®¶.¶IsModule®¶ _m__ _c__) => + _m__ (InstCacheBlocking.ICache MemTypes.InstReq MemTypes.InstResp) +} diff -r 6d1ff93e3afa -r 91a1f76ddd62 core/sim/bdir_dut/InstCacheBlocking.bo Binary file core/sim/bdir_dut/InstCacheBlocking.bo has changed diff -r 6d1ff93e3afa -r 91a1f76ddd62 core/sim/bdir_dut/MemArb.bi --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/core/sim/bdir_dut/MemArb.bi Tue Apr 13 17:34:33 2010 -0400 @@ -0,0 +1,61 @@ +signature MemArb where { +import ¶Assert®¶; + +import ¶Counter®¶; + +import ¶FIFOF_®¶; + +import ¶FIFOF®¶; + +import ¶FIFO®¶; + +import ¶Inout®¶; + +import ¶List®¶; + +import BFIFO; + +import ¶Clocks®¶; + +import ¶ListN®¶; + +import ¶PrimArray®¶; + +import ¶Vector®¶; + +import ¶Connectable®¶; + +import ¶GetPut®¶; + +import ¶ClientServer®¶; + +import Trace; + +import MemTypes; + +interface (MemArb.MemArb :: *) = { + MemArb.cache0_server :: ¶ClientServer®¶.¶Server®¶ MemTypes.MainMemReq MemTypes.MainMemResp; + MemArb.cache1_server :: ¶ClientServer®¶.¶Server®¶ MemTypes.MainMemReq MemTypes.MainMemResp; + MemArb.mmem_client :: ¶ClientServer®¶.¶Client®¶ MemTypes.MainMemReq MemTypes.MainMemResp +}; + +instance MemArb ¶Prelude®¶.¶PrimMakeUndefined®¶ MemArb.MemArb; + +instance MemArb ¶Prelude®¶.¶PrimDeepSeqCond®¶ MemArb.MemArb; + +instance MemArb ¶Prelude®¶.¶PrimMakeUninitialized®¶ MemArb.MemArb; + +data (MemArb.ReqPtr :: *) = MemArb.REQ0 () | MemArb.REQ1 (); + +instance MemArb ¶Prelude®¶.¶PrimMakeUndefined®¶ MemArb.ReqPtr; + +instance MemArb ¶Prelude®¶.¶PrimDeepSeqCond®¶ MemArb.ReqPtr; + +instance MemArb ¶Prelude®¶.¶PrimMakeUninitialized®¶ MemArb.ReqPtr; + +instance MemArb ¶Prelude®¶.¶Eq®¶ MemArb.ReqPtr; + +instance MemArb ¶Prelude®¶.¶Bits®¶ MemArb.ReqPtr 1; + +MemArb.mkMemArb :: (¶Prelude®¶.¶IsModule®¶ _m__ _c__) => _m__ MemArb.MemArb +} diff -r 6d1ff93e3afa -r 91a1f76ddd62 core/sim/bdir_dut/MemArb.bo Binary file core/sim/bdir_dut/MemArb.bo has changed diff -r 6d1ff93e3afa -r 91a1f76ddd62 core/sim/bdir_dut/MemTypes.bi --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/core/sim/bdir_dut/MemTypes.bi Tue Apr 13 17:34:33 2010 -0400 @@ -0,0 +1,171 @@ +signature MemTypes where { +import ¶Counter®¶; + +import ¶FIFOF_®¶; + +import ¶FIFOF®¶; + +import ¶FIFO®¶; + +import ¶Inout®¶; + +import ¶List®¶; + +import ¶Clocks®¶; + +import ¶ListN®¶; + +import ¶PrimArray®¶; + +import ¶Vector®¶; + +import ¶Connectable®¶; + +import ¶GetPut®¶; + +import ¶ClientServer®¶; + +import Trace; + +data (MemTypes.MemReq :: # -> # -> # -> *) addrSz tagSz dataSz = + MemTypes.LoadReq (MemTypes.¶MemReq_$LoadReq¶ addrSz tagSz dataSz) | + MemTypes.StoreReq (MemTypes.¶MemReq_$StoreReq¶ addrSz tagSz dataSz); + +instance MemTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ (MemTypes.MemReq addrSz tagSz dataSz); + +instance MemTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ (MemTypes.MemReq addrSz tagSz dataSz); + +instance MemTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ (MemTypes.MemReq addrSz tagSz dataSz); + +instance MemTypes ¶Prelude®¶.¶Eq®¶ (MemTypes.MemReq addrSz tagSz dataSz); + +instance MemTypes (¶Prelude®¶.¶Add®¶ 1 _v103 _v100, + ¶Prelude®¶.¶Max®¶ _v101 _v104 _v103, + ¶Prelude®¶.¶Add®¶ _v105 _v104 _v103, + ¶Prelude®¶.¶Add®¶ _v102 _v101 _v103, + ¶Prelude®¶.¶Add®¶ addrSz _v106 _v104, + ¶Prelude®¶.¶Add®¶ tagSz dataSz _v106, + ¶Prelude®¶.¶Add®¶ addrSz tagSz _v101) => + ¶Prelude®¶.¶Bits®¶ (MemTypes.MemReq addrSz tagSz dataSz) _v100; + +struct (MemTypes.¶MemReq_$LoadReq¶ :: # -> # -> # -> *) addrSz tagSz dataSz = { + MemTypes.addr :: ¶Prelude®¶.¶Bit®¶ addrSz; + MemTypes.tag :: ¶Prelude®¶.¶Bit®¶ tagSz +}; + +instance MemTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ (MemTypes.¶MemReq_$LoadReq¶ addrSz tagSz dataSz); + +instance MemTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ (MemTypes.¶MemReq_$LoadReq¶ addrSz tagSz dataSz); + +instance MemTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ + (MemTypes.¶MemReq_$LoadReq¶ addrSz tagSz dataSz); + +instance MemTypes ¶Prelude®¶.¶Eq®¶ (MemTypes.¶MemReq_$LoadReq¶ addrSz tagSz dataSz); + +instance MemTypes (¶Prelude®¶.¶Add®¶ _v101 _v104 _v100) => + ¶Prelude®¶.¶Bits®¶ (MemTypes.¶MemReq_$LoadReq¶ _v101 _v104 dataSz) _v100; + +struct (MemTypes.¶MemReq_$StoreReq¶ :: # -> # -> # -> *) addrSz tagSz dataSz = { + MemTypes.addr :: ¶Prelude®¶.¶Bit®¶ addrSz; + MemTypes.tag :: ¶Prelude®¶.¶Bit®¶ tagSz; + MemTypes.¡data¡ :: ¶Prelude®¶.¶Bit®¶ dataSz +}; + +instance MemTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ (MemTypes.¶MemReq_$StoreReq¶ addrSz tagSz dataSz); + +instance MemTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ (MemTypes.¶MemReq_$StoreReq¶ addrSz tagSz dataSz); + +instance MemTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ + (MemTypes.¶MemReq_$StoreReq¶ addrSz tagSz dataSz); + +instance MemTypes ¶Prelude®¶.¶Eq®¶ (MemTypes.¶MemReq_$StoreReq¶ addrSz tagSz dataSz); + +instance MemTypes (¶Prelude®¶.¶Add®¶ _v101 _v100 _v103, ¶Prelude®¶.¶Add®¶ _v104 _v107 _v100) => + ¶Prelude®¶.¶Bits®¶ (MemTypes.¶MemReq_$StoreReq¶ _v101 _v104 _v107) _v103; + +data (MemTypes.MemResp :: # -> # -> *) tagSz dataSz = + MemTypes.LoadResp (MemTypes.¶MemResp_$LoadResp¶ tagSz dataSz) | + MemTypes.StoreResp (MemTypes.¶MemResp_$StoreResp¶ tagSz dataSz); + +instance MemTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ (MemTypes.MemResp tagSz dataSz); + +instance MemTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ (MemTypes.MemResp tagSz dataSz); + +instance MemTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ (MemTypes.MemResp tagSz dataSz); + +instance MemTypes ¶Prelude®¶.¶Eq®¶ (MemTypes.MemResp tagSz dataSz); + +instance MemTypes (¶Prelude®¶.¶Add®¶ 1 _v103 _v100, + ¶Prelude®¶.¶Max®¶ _v101 _v104 _v103, + ¶Prelude®¶.¶Add®¶ _v105 _v104 _v103, + ¶Prelude®¶.¶Add®¶ _v102 _v101 _v103, + ¶Prelude®¶.¶Add®¶ _v104 dataSz _v101) => + ¶Prelude®¶.¶Bits®¶ (MemTypes.MemResp _v104 dataSz) _v100; + +struct (MemTypes.¶MemResp_$LoadResp¶ :: # -> # -> *) tagSz dataSz = { + MemTypes.tag :: ¶Prelude®¶.¶Bit®¶ tagSz; + MemTypes.¡data¡ :: ¶Prelude®¶.¶Bit®¶ dataSz +}; + +instance MemTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ (MemTypes.¶MemResp_$LoadResp¶ tagSz dataSz); + +instance MemTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ (MemTypes.¶MemResp_$LoadResp¶ tagSz dataSz); + +instance MemTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ (MemTypes.¶MemResp_$LoadResp¶ tagSz dataSz); + +instance MemTypes ¶Prelude®¶.¶Eq®¶ (MemTypes.¶MemResp_$LoadResp¶ tagSz dataSz); + +instance MemTypes (¶Prelude®¶.¶Add®¶ _v101 _v104 _v100) => + ¶Prelude®¶.¶Bits®¶ (MemTypes.¶MemResp_$LoadResp¶ _v101 _v104) _v100; + +struct (MemTypes.¶MemResp_$StoreResp¶ :: # -> # -> *) tagSz dataSz = { + MemTypes.tag :: ¶Prelude®¶.¶Bit®¶ tagSz +}; + +instance MemTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ (MemTypes.¶MemResp_$StoreResp¶ tagSz dataSz); + +instance MemTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ (MemTypes.¶MemResp_$StoreResp¶ tagSz dataSz); + +instance MemTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ (MemTypes.¶MemResp_$StoreResp¶ tagSz dataSz); + +instance MemTypes ¶Prelude®¶.¶Eq®¶ (MemTypes.¶MemResp_$StoreResp¶ tagSz dataSz); + +instance MemTypes ¶Prelude®¶.¶Bits®¶ (MemTypes.¶MemResp_$StoreResp¶ _v101 dataSz) _v101; + +type (MemTypes.AddrSz :: #) = 32; + +type (MemTypes.TagSz :: #) = 8; + +type (MemTypes.DataSz :: #) = 32; + +type (MemTypes.InstSz :: #) = 32; + +type (MemTypes.HostDataSz :: #) = 32; + +type (MemTypes.InstReq :: *) = MemTypes.MemReq MemTypes.AddrSz MemTypes.TagSz 0; + +type (MemTypes.InstResp :: *) = MemTypes.MemResp MemTypes.TagSz MemTypes.InstSz; + +type (MemTypes.DataReq :: *) = MemTypes.MemReq MemTypes.AddrSz MemTypes.TagSz MemTypes.DataSz; + +type (MemTypes.DataResp :: *) = MemTypes.MemResp MemTypes.TagSz MemTypes.DataSz; + +type (MemTypes.HostReq :: *) = MemTypes.MemReq MemTypes.AddrSz MemTypes.TagSz MemTypes.HostDataSz; + +type (MemTypes.HostResp :: *) = MemTypes.MemResp MemTypes.TagSz MemTypes.HostDataSz; + +type (MemTypes.MainMemAddrSz :: #) = 32; + +type (MemTypes.MainMemTagSz :: #) = 8; + +type (MemTypes.MainMemDataSz :: #) = 32; + +type (MemTypes.MainMemReq :: *) = + MemTypes.MemReq MemTypes.MainMemAddrSz MemTypes.MainMemTagSz MemTypes.MainMemDataSz; + +type (MemTypes.MainMemResp :: *) = MemTypes.MemResp MemTypes.MainMemTagSz MemTypes.MainMemDataSz; + +instance MemTypes Trace.Traceable (MemTypes.MemReq a b c); + +instance MemTypes Trace.Traceable (MemTypes.MemResp a b) +} diff -r 6d1ff93e3afa -r 91a1f76ddd62 core/sim/bdir_dut/MemTypes.bo Binary file core/sim/bdir_dut/MemTypes.bo has changed diff -r 6d1ff93e3afa -r 91a1f76ddd62 core/sim/bdir_dut/ProcTypes.bi --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/core/sim/bdir_dut/ProcTypes.bi Tue Apr 13 17:34:33 2010 -0400 @@ -0,0 +1,725 @@ +signature ProcTypes where { +import ¶Counter®¶; + +import ¶FIFOF_®¶; + +import ¶FIFOF®¶; + +import ¶FIFO®¶; + +import ¶Inout®¶; + +import ¶List®¶; + +import ¶Clocks®¶; + +import ¶ListN®¶; + +import ¶PrimArray®¶; + +import ¶Vector®¶; + +import ¶Connectable®¶; + +import ¶GetPut®¶; + +import ¶ClientServer®¶; + +import Trace; + +type (ProcTypes.Addr :: *) = ¶Prelude®¶.¶Bit®¶ 32; + +type (ProcTypes.Stat :: *) = ¶Prelude®¶.¶Int®¶ 18; + +type (ProcTypes.Rindx :: *) = ¶Prelude®¶.¶Bit®¶ 5; + +type (ProcTypes.Simm :: *) = ¶Prelude®¶.¶Bit®¶ 16; + +type (ProcTypes.Zimm :: *) = ¶Prelude®¶.¶Bit®¶ 16; + +type (ProcTypes.Epoch :: *) = ¶Prelude®¶.¶Bit®¶ 8; + +type (ProcTypes.Shamt :: *) = ¶Prelude®¶.¶Bit®¶ 5; + +type (ProcTypes.Target :: *) = ¶Prelude®¶.¶Bit®¶ 26; + +type (ProcTypes.CP0indx :: *) = ¶Prelude®¶.¶Bit®¶ 5; + +type (ProcTypes.Data :: *) = ¶Prelude®¶.¶Bit®¶ 32; + +data (ProcTypes.Direction :: *) = ProcTypes.Taken () | ProcTypes.NotTaken (); + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.Direction; + +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.Direction; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.Direction; + +instance ProcTypes ¶Prelude®¶.¶Bits®¶ ProcTypes.Direction 1; + +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.Direction; + +data (ProcTypes.WritebackType :: *) = + ProcTypes.ALUWB (¶Prelude®¶.¶Tuple2®¶ ProcTypes.Rindx ProcTypes.Data) | + ProcTypes.MemWB ProcTypes.Rindx | + ProcTypes.CoWB (¶Prelude®¶.¶Tuple2®¶ ProcTypes.Rindx ProcTypes.Data); + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.WritebackType; + +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.WritebackType; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.WritebackType; + +instance ProcTypes ¶Prelude®¶.¶Bits®¶ ProcTypes.WritebackType 39; + +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.WritebackType; + +data (ProcTypes.WBResult :: *) = + ProcTypes.WB_ALU ProcTypes.¶WBResult_$WB_ALU¶ | + ProcTypes.WB_Host (¶Prelude®¶.¶Bit®¶ 32) | + ProcTypes.WB_Load ProcTypes.Rindx | + ProcTypes.WB_Store (); + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.WBResult; + +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.WBResult; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.WBResult; + +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.WBResult; + +instance ProcTypes ¶Prelude®¶.¶Bits®¶ ProcTypes.WBResult 39; + +struct (ProcTypes.¶WBResult_$WB_ALU¶ :: *) = { + ProcTypes.¡data¡ :: ¶Prelude®¶.¶Bit®¶ 32; + ProcTypes.dest :: ProcTypes.Rindx +}; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶WBResult_$WB_ALU¶; + +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶WBResult_$WB_ALU¶; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶WBResult_$WB_ALU¶; + +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶WBResult_$WB_ALU¶; + +instance ProcTypes ¶Prelude®¶.¶Bits®¶ ProcTypes.¶WBResult_$WB_ALU¶ 37; + +struct (ProcTypes.PCStat :: *) = { + ProcTypes.qpc :: ProcTypes.Addr; + ProcTypes.qnxtpc :: ProcTypes.Addr; + ProcTypes.qepoch :: ProcTypes.Epoch +}; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.PCStat; + +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.PCStat; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.PCStat; + +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.PCStat; + +instance ProcTypes ¶Prelude®¶.¶Bits®¶ ProcTypes.PCStat 72; + +data (ProcTypes.Instr :: *) = + ProcTypes.LW ProcTypes.¶Instr_$LW¶ | + ProcTypes.SW ProcTypes.¶Instr_$SW¶ | + ProcTypes.ADDIU ProcTypes.¶Instr_$ADDIU¶ | + ProcTypes.SLTI ProcTypes.¶Instr_$SLTI¶ | + ProcTypes.SLTIU ProcTypes.¶Instr_$SLTIU¶ | + ProcTypes.ANDI ProcTypes.¶Instr_$ANDI¶ | + ProcTypes.ORI ProcTypes.¶Instr_$ORI¶ | + ProcTypes.XORI ProcTypes.¶Instr_$XORI¶ | + ProcTypes.LUI ProcTypes.¶Instr_$LUI¶ | + ProcTypes.SLL ProcTypes.¶Instr_$SLL¶ | + ProcTypes.SRL ProcTypes.¶Instr_$SRL¶ | + ProcTypes.SRA ProcTypes.¶Instr_$SRA¶ | + ProcTypes.SLLV ProcTypes.¶Instr_$SLLV¶ | + ProcTypes.SRLV ProcTypes.¶Instr_$SRLV¶ | + ProcTypes.SRAV ProcTypes.¶Instr_$SRAV¶ | + ProcTypes.ADDU ProcTypes.¶Instr_$ADDU¶ | + ProcTypes.SUBU ProcTypes.¶Instr_$SUBU¶ | + ProcTypes.AND ProcTypes.¶Instr_$AND¶ | + ProcTypes.OR ProcTypes.¶Instr_$OR¶ | + ProcTypes.XOR ProcTypes.¶Instr_$XOR¶ | + ProcTypes.NOR ProcTypes.¶Instr_$NOR¶ | + ProcTypes.SLT ProcTypes.¶Instr_$SLT¶ | + ProcTypes.SLTU ProcTypes.¶Instr_$SLTU¶ | + ProcTypes.J ProcTypes.¶Instr_$J¶ | + ProcTypes.JAL ProcTypes.¶Instr_$JAL¶ | + ProcTypes.JR ProcTypes.¶Instr_$JR¶ | + ProcTypes.JALR ProcTypes.¶Instr_$JALR¶ | + ProcTypes.BEQ ProcTypes.¶Instr_$BEQ¶ | + ProcTypes.BNE ProcTypes.¶Instr_$BNE¶ | + ProcTypes.BLEZ ProcTypes.¶Instr_$BLEZ¶ | + ProcTypes.BGTZ ProcTypes.¶Instr_$BGTZ¶ | + ProcTypes.BLTZ ProcTypes.¶Instr_$BLTZ¶ | + ProcTypes.BGEZ ProcTypes.¶Instr_$BGEZ¶ | + ProcTypes.MFC0 ProcTypes.¶Instr_$MFC0¶ | + ProcTypes.MTC0 ProcTypes.¶Instr_$MTC0¶ | + ProcTypes.ILLEGAL (); + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.Instr; + +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.Instr; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.Instr; + +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.Instr; + +struct (ProcTypes.¶Instr_$LW¶ :: *) = { + ProcTypes.rbase :: ProcTypes.Rindx; + ProcTypes.rdst :: ProcTypes.Rindx; + ProcTypes.offset :: ProcTypes.Simm +}; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$LW¶; + +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$LW¶; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$LW¶; + +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$LW¶; + +struct (ProcTypes.¶Instr_$SW¶ :: *) = { + ProcTypes.rbase :: ProcTypes.Rindx; + ProcTypes.rsrc :: ProcTypes.Rindx; + ProcTypes.offset :: ProcTypes.Simm +}; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$SW¶; + +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$SW¶; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$SW¶; + +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$SW¶; + +struct (ProcTypes.¶Instr_$ADDIU¶ :: *) = { + ProcTypes.rsrc :: ProcTypes.Rindx; + ProcTypes.rdst :: ProcTypes.Rindx; + ProcTypes.imm :: ProcTypes.Simm +}; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$ADDIU¶; + +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$ADDIU¶; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$ADDIU¶; + +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$ADDIU¶; + +struct (ProcTypes.¶Instr_$SLTI¶ :: *) = { + ProcTypes.rsrc :: ProcTypes.Rindx; + ProcTypes.rdst :: ProcTypes.Rindx; + ProcTypes.imm :: ProcTypes.Simm +}; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$SLTI¶; + +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$SLTI¶; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$SLTI¶; + +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$SLTI¶; + +struct (ProcTypes.¶Instr_$SLTIU¶ :: *) = { + ProcTypes.rsrc :: ProcTypes.Rindx; + ProcTypes.rdst :: ProcTypes.Rindx; + ProcTypes.imm :: ProcTypes.Simm +}; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$SLTIU¶; + +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$SLTIU¶; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$SLTIU¶; + +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$SLTIU¶; + +struct (ProcTypes.¶Instr_$ANDI¶ :: *) = { + ProcTypes.rsrc :: ProcTypes.Rindx; + ProcTypes.rdst :: ProcTypes.Rindx; + ProcTypes.imm :: ProcTypes.Zimm +}; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$ANDI¶; + +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$ANDI¶; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$ANDI¶; + +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$ANDI¶; + +struct (ProcTypes.¶Instr_$ORI¶ :: *) = { + ProcTypes.rsrc :: ProcTypes.Rindx; + ProcTypes.rdst :: ProcTypes.Rindx; + ProcTypes.imm :: ProcTypes.Zimm +}; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$ORI¶; + +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$ORI¶; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$ORI¶; + +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$ORI¶; + +struct (ProcTypes.¶Instr_$XORI¶ :: *) = { + ProcTypes.rsrc :: ProcTypes.Rindx; + ProcTypes.rdst :: ProcTypes.Rindx; + ProcTypes.imm :: ProcTypes.Zimm +}; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$XORI¶; + +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$XORI¶; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$XORI¶; + +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$XORI¶; + +struct (ProcTypes.¶Instr_$LUI¶ :: *) = { + ProcTypes.rdst :: ProcTypes.Rindx; + ProcTypes.imm :: ProcTypes.Zimm +}; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$LUI¶; + +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$LUI¶; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$LUI¶; + +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$LUI¶; + +struct (ProcTypes.¶Instr_$SLL¶ :: *) = { + ProcTypes.rsrc :: ProcTypes.Rindx; + ProcTypes.rdst :: ProcTypes.Rindx; + ProcTypes.shamt :: ProcTypes.Shamt +}; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$SLL¶; + +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$SLL¶; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$SLL¶; + +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$SLL¶; + +struct (ProcTypes.¶Instr_$SRL¶ :: *) = { + ProcTypes.rsrc :: ProcTypes.Rindx; + ProcTypes.rdst :: ProcTypes.Rindx; + ProcTypes.shamt :: ProcTypes.Shamt +}; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$SRL¶; + +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$SRL¶; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$SRL¶; + +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$SRL¶; + +struct (ProcTypes.¶Instr_$SRA¶ :: *) = { + ProcTypes.rsrc :: ProcTypes.Rindx; + ProcTypes.rdst :: ProcTypes.Rindx; + ProcTypes.shamt :: ProcTypes.Shamt +}; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$SRA¶; + +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$SRA¶; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$SRA¶; + +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$SRA¶; + +struct (ProcTypes.¶Instr_$SLLV¶ :: *) = { + ProcTypes.rsrc :: ProcTypes.Rindx; + ProcTypes.rdst :: ProcTypes.Rindx; + ProcTypes.rshamt :: ProcTypes.Rindx +}; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$SLLV¶; + +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$SLLV¶; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$SLLV¶; + +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$SLLV¶; + +struct (ProcTypes.¶Instr_$SRLV¶ :: *) = { + ProcTypes.rsrc :: ProcTypes.Rindx; + ProcTypes.rdst :: ProcTypes.Rindx; + ProcTypes.rshamt :: ProcTypes.Rindx +}; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$SRLV¶; + +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$SRLV¶; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$SRLV¶; + +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$SRLV¶; + +struct (ProcTypes.¶Instr_$SRAV¶ :: *) = { + ProcTypes.rsrc :: ProcTypes.Rindx; + ProcTypes.rdst :: ProcTypes.Rindx; + ProcTypes.rshamt :: ProcTypes.Rindx +}; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$SRAV¶; + +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$SRAV¶; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$SRAV¶; + +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$SRAV¶; + +struct (ProcTypes.¶Instr_$ADDU¶ :: *) = { + ProcTypes.rsrc1 :: ProcTypes.Rindx; + ProcTypes.rsrc2 :: ProcTypes.Rindx; + ProcTypes.rdst :: ProcTypes.Rindx +}; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$ADDU¶; + +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$ADDU¶; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$ADDU¶; + +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$ADDU¶; + +struct (ProcTypes.¶Instr_$SUBU¶ :: *) = { + ProcTypes.rsrc1 :: ProcTypes.Rindx; + ProcTypes.rsrc2 :: ProcTypes.Rindx; + ProcTypes.rdst :: ProcTypes.Rindx +}; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$SUBU¶; + +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$SUBU¶; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$SUBU¶; + +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$SUBU¶; + +struct (ProcTypes.¶Instr_$AND¶ :: *) = { + ProcTypes.rsrc1 :: ProcTypes.Rindx; + ProcTypes.rsrc2 :: ProcTypes.Rindx; + ProcTypes.rdst :: ProcTypes.Rindx +}; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$AND¶; + +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$AND¶; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$AND¶; + +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$AND¶; + +struct (ProcTypes.¶Instr_$OR¶ :: *) = { + ProcTypes.rsrc1 :: ProcTypes.Rindx; + ProcTypes.rsrc2 :: ProcTypes.Rindx; + ProcTypes.rdst :: ProcTypes.Rindx +}; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$OR¶; + +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$OR¶; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$OR¶; + +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$OR¶; + +struct (ProcTypes.¶Instr_$XOR¶ :: *) = { + ProcTypes.rsrc1 :: ProcTypes.Rindx; + ProcTypes.rsrc2 :: ProcTypes.Rindx; + ProcTypes.rdst :: ProcTypes.Rindx +}; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$XOR¶; + +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$XOR¶; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$XOR¶; + +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$XOR¶; + +struct (ProcTypes.¶Instr_$NOR¶ :: *) = { + ProcTypes.rsrc1 :: ProcTypes.Rindx; + ProcTypes.rsrc2 :: ProcTypes.Rindx; + ProcTypes.rdst :: ProcTypes.Rindx +}; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$NOR¶; + +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$NOR¶; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$NOR¶; + +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$NOR¶; + +struct (ProcTypes.¶Instr_$SLT¶ :: *) = { + ProcTypes.rsrc1 :: ProcTypes.Rindx; + ProcTypes.rsrc2 :: ProcTypes.Rindx; + ProcTypes.rdst :: ProcTypes.Rindx +}; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$SLT¶; + +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$SLT¶; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$SLT¶; + +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$SLT¶; + +struct (ProcTypes.¶Instr_$SLTU¶ :: *) = { + ProcTypes.rsrc1 :: ProcTypes.Rindx; + ProcTypes.rsrc2 :: ProcTypes.Rindx; + ProcTypes.rdst :: ProcTypes.Rindx +}; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$SLTU¶; + +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$SLTU¶; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$SLTU¶; + +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$SLTU¶; + +struct (ProcTypes.¶Instr_$J¶ :: *) = { + ProcTypes.target :: ProcTypes.Target +}; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$J¶; + +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$J¶; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$J¶; + +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$J¶; + +struct (ProcTypes.¶Instr_$JAL¶ :: *) = { + ProcTypes.target :: ProcTypes.Target +}; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$JAL¶; + +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$JAL¶; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$JAL¶; + +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$JAL¶; + +struct (ProcTypes.¶Instr_$JR¶ :: *) = { + ProcTypes.rsrc :: ProcTypes.Rindx +}; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$JR¶; + +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$JR¶; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$JR¶; + +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$JR¶; + +struct (ProcTypes.¶Instr_$JALR¶ :: *) = { + ProcTypes.rsrc :: ProcTypes.Rindx; + ProcTypes.rdst :: ProcTypes.Rindx +}; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$JALR¶; + +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$JALR¶; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$JALR¶; + +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$JALR¶; + +struct (ProcTypes.¶Instr_$BEQ¶ :: *) = { + ProcTypes.rsrc1 :: ProcTypes.Rindx; + ProcTypes.rsrc2 :: ProcTypes.Rindx; + ProcTypes.offset :: ProcTypes.Simm +}; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$BEQ¶; + +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$BEQ¶; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$BEQ¶; + +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$BEQ¶; + +struct (ProcTypes.¶Instr_$BNE¶ :: *) = { + ProcTypes.rsrc1 :: ProcTypes.Rindx; + ProcTypes.rsrc2 :: ProcTypes.Rindx; + ProcTypes.offset :: ProcTypes.Simm +}; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$BNE¶; + +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$BNE¶; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$BNE¶; + +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$BNE¶; + +struct (ProcTypes.¶Instr_$BLEZ¶ :: *) = { + ProcTypes.rsrc :: ProcTypes.Rindx; + ProcTypes.offset :: ProcTypes.Simm +}; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$BLEZ¶; + +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$BLEZ¶; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$BLEZ¶; + +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$BLEZ¶; + +struct (ProcTypes.¶Instr_$BGTZ¶ :: *) = { + ProcTypes.rsrc :: ProcTypes.Rindx; + ProcTypes.offset :: ProcTypes.Simm +}; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$BGTZ¶; + +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$BGTZ¶; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$BGTZ¶; + +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$BGTZ¶; + +struct (ProcTypes.¶Instr_$BLTZ¶ :: *) = { + ProcTypes.rsrc :: ProcTypes.Rindx; + ProcTypes.offset :: ProcTypes.Simm +}; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$BLTZ¶; + +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$BLTZ¶; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$BLTZ¶; + +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$BLTZ¶; + +struct (ProcTypes.¶Instr_$BGEZ¶ :: *) = { + ProcTypes.rsrc :: ProcTypes.Rindx; + ProcTypes.offset :: ProcTypes.Simm +}; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$BGEZ¶; + +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$BGEZ¶; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$BGEZ¶; + +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$BGEZ¶; + +struct (ProcTypes.¶Instr_$MFC0¶ :: *) = { + ProcTypes.rdst :: ProcTypes.Rindx; + ProcTypes.cop0src :: ProcTypes.CP0indx +}; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$MFC0¶; + +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$MFC0¶; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$MFC0¶; + +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$MFC0¶; + +struct (ProcTypes.¶Instr_$MTC0¶ :: *) = { + ProcTypes.rsrc :: ProcTypes.Rindx; + ProcTypes.cop0dst :: ProcTypes.CP0indx +}; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUndefined®¶ ProcTypes.¶Instr_$MTC0¶; + +instance ProcTypes ¶Prelude®¶.¶PrimDeepSeqCond®¶ ProcTypes.¶Instr_$MTC0¶; + +instance ProcTypes ¶Prelude®¶.¶PrimMakeUninitialized®¶ ProcTypes.¶Instr_$MTC0¶; + +instance ProcTypes ¶Prelude®¶.¶Eq®¶ ProcTypes.¶Instr_$MTC0¶; + +ProcTypes.opFUNC :: ¶Prelude®¶.¶Bit®¶ 6; + +ProcTypes.fcSLL :: ¶Prelude®¶.¶Bit®¶ 6; + +ProcTypes.opRT :: ¶Prelude®¶.¶Bit®¶ 6; + +ProcTypes.fcSRL :: ¶Prelude®¶.¶Bit®¶ 6; + +ProcTypes.opRS :: ¶Prelude®¶.¶Bit®¶ 6; + +ProcTypes.fcSRA :: ¶Prelude®¶.¶Bit®¶ 6; + +ProcTypes.fcSLLV :: ¶Prelude®¶.¶Bit®¶ 6; + +ProcTypes.opLW :: ¶Prelude®¶.¶Bit®¶ 6; + +ProcTypes.fcSRLV :: ¶Prelude®¶.¶Bit®¶ 6; + +ProcTypes.opSW :: ¶Prelude®¶.¶Bit®¶ 6; + +ProcTypes.fcSRAV :: ¶Prelude®¶.¶Bit®¶ 6; + +ProcTypes.fcADDU :: ¶Prelude®¶.¶Bit®¶ 6; + +ProcTypes.opADDIU :: ¶Prelude®¶.¶Bit®¶ 6; + +ProcTypes.fcSUBU :: ¶Prelude®¶.¶Bit®¶ 6; + +ProcTypes.opSLTI :: ¶Prelude®¶.¶Bit®¶ 6; + +ProcTypes.fcAND :: ¶Prelude®¶.¶Bit®¶ 6; + +ProcTypes.opSLTIU :: ¶Prelude®¶.¶Bit®¶ 6; + +ProcTypes.fcOR :: ¶Prelude®¶.¶Bit®¶ 6; + +ProcTypes.opANDI :: ¶Prelude®¶.¶Bit®¶ 6; + +ProcTypes.fcXOR :: ¶Prelude®¶.¶Bit®¶ 6; + +ProcTypes.opORI :: ¶Prelude®¶.¶Bit®¶ 6; + +ProcTypes.fcNOR :: ¶Prelude®¶.¶Bit®¶ 6; + +ProcTypes.opXORI :: ¶Prelude®¶.¶Bit®¶ 6; + +ProcTypes.fcSLT :: ¶Prelude®¶.¶Bit®¶ 6; + +ProcTypes.opLUI :: ¶Prelude®¶.¶Bit®¶ 6; + +ProcTypes.fcSLTU :: ¶Prelude®¶.¶Bit®¶ 6; + +ProcTypes.opJ :: ¶Prelude®¶.¶Bit®¶ 6; + +ProcTypes.opJAL :: ¶Prelude®¶.¶Bit®¶ 6; + +ProcTypes.fcJR :: ¶Prelude®¶.¶Bit®¶ 6; + +ProcTypes.fcJALR :: ¶Prelude®¶.¶Bit®¶ 6; + +ProcTypes.opBEQ :: ¶Prelude®¶.¶Bit®¶ 6; + +ProcTypes.opBNE :: ¶Prelude®¶.¶Bit®¶ 6; + +ProcTypes.opBLEZ :: ¶Prelude®¶.¶Bit®¶ 6; + +ProcTypes.opBGTZ :: ¶Prelude®¶.¶Bit®¶ 6; + +ProcTypes.rtBLTZ :: ¶Prelude®¶.¶Bit®¶ 5; + +ProcTypes.rtBGEZ :: ¶Prelude®¶.¶Bit®¶ 5; + +ProcTypes.rsMFC0 :: ¶Prelude®¶.¶Bit®¶ 5; + +ProcTypes.rsMTC0 :: ¶Prelude®¶.¶Bit®¶ 5; + +instance ProcTypes ¶Prelude®¶.¶Bits®¶ ProcTypes.Instr 32; + +instance ProcTypes Trace.Traceable ProcTypes.Instr +} diff -r 6d1ff93e3afa -r 91a1f76ddd62 core/sim/bdir_dut/ProcTypes.bo Binary file core/sim/bdir_dut/ProcTypes.bo has changed diff -r 6d1ff93e3afa -r 91a1f76ddd62 core/sim/bdir_dut/Processor.bi --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/core/sim/bdir_dut/Processor.bi Tue Apr 13 17:34:33 2010 -0400 @@ -0,0 +1,126 @@ +signature Processor where { +import ¶Assert®¶; + +import ¶ConfigReg®¶; + +import ¶Counter®¶; + +import ¶FIFOF_®¶; + +import ¶FIFOF®¶; + +import ¶FIFO®¶; + +import ¶Inout®¶; + +import ¶List®¶; + +import BFIFO; + +import ¶Clocks®¶; + +import ¶ListN®¶; + +import ¶Monad®¶; + +import ¶PrimArray®¶; + +import ¶RWire®¶; + +import ¶RegFile®¶; + +import SFIFO; + +import ¶Vector®¶; + +import ¶Connectable®¶; + +import ¶GetPut®¶; + +import ¶ClientServer®¶; + +import Trace; + +import MemTypes; + +import ProcTypes; + +import BRegFile; + +import BranchPred; + +interface (Processor.ProcStats :: *) = { + Processor.num_cycles :: ¶GetPut®¶.¶Get®¶ ProcTypes.Stat; + Processor.num_inst :: ¶GetPut®¶.¶Get®¶ ProcTypes.Stat +}; + +instance Processor ¶Prelude®¶.¶PrimMakeUndefined®¶ Processor.ProcStats; + +instance Processor ¶Prelude®¶.¶PrimDeepSeqCond®¶ Processor.ProcStats; + +instance Processor ¶Prelude®¶.¶PrimMakeUninitialized®¶ Processor.ProcStats; + +interface (Processor.CPUToHost :: *) = { + Processor.cpuToHost :: ¶Prelude®¶.¶Int®¶ 32 -> ¶Prelude®¶.¶Bit®¶ 32 {-# arg_names = [req] #-} +}; + +instance Processor ¶Prelude®¶.¶PrimMakeUndefined®¶ Processor.CPUToHost; + +instance Processor ¶Prelude®¶.¶PrimDeepSeqCond®¶ Processor.CPUToHost; + +instance Processor ¶Prelude®¶.¶PrimMakeUninitialized®¶ Processor.CPUToHost; + +interface (Processor.Proc :: *) = { + Processor.dmem_client :: ¶ClientServer®¶.¶Client®¶ MemTypes.DataReq MemTypes.DataResp; + Processor.imem_client :: ¶ClientServer®¶.¶Client®¶ MemTypes.InstReq MemTypes.InstResp; + Processor.statsEn_get :: ¶GetPut®¶.¶Get®¶ ¶Prelude®¶.¶Bool®¶; + Processor.stats :: Processor.ProcStats; + Processor.tohost :: Processor.CPUToHost +}; + +instance Processor ¶Prelude®¶.¶PrimMakeUndefined®¶ Processor.Proc; + +instance Processor ¶Prelude®¶.¶PrimDeepSeqCond®¶ Processor.Proc; + +instance Processor ¶Prelude®¶.¶PrimMakeUninitialized®¶ Processor.Proc; + +data (Processor.Stage :: *) = Processor.PCgen () | Processor.Exec () | Processor.Writeback (); + +instance Processor ¶Prelude®¶.¶PrimMakeUndefined®¶ Processor.Stage; + +instance Processor ¶Prelude®¶.¶PrimDeepSeqCond®¶ Processor.Stage; + +instance Processor ¶Prelude®¶.¶PrimMakeUninitialized®¶ Processor.Stage; + +instance Processor ¶Prelude®¶.¶Eq®¶ Processor.Stage; + +instance Processor ¶Prelude®¶.¶Bits®¶ Processor.Stage 2; + +interface (Processor.BRFile :: *) = { + Processor.wr :: ProcTypes.Rindx -> + ¶Prelude®¶.¶Bit®¶ 32 -> ¶Prelude®¶.¶Action®¶ {-# arg_names = [rindx, ¡data¡] #-}; + Processor.rd1 :: ProcTypes.Rindx -> ¶Prelude®¶.¶Bit®¶ 32 {-# arg_names = [rindx] #-}; + Processor.rd2 :: ProcTypes.Rindx -> ¶Prelude®¶.¶Bit®¶ 32 {-# arg_names = [rindx] #-} +}; + +instance Processor ¶Prelude®¶.¶PrimMakeUndefined®¶ Processor.BRFile; + +instance Processor ¶Prelude®¶.¶PrimDeepSeqCond®¶ Processor.BRFile; + +instance Processor ¶Prelude®¶.¶PrimMakeUninitialized®¶ Processor.BRFile; + +Processor.mkBRFile :: (¶Prelude®¶.¶IsModule®¶ _m__ _c__) => _m__ Processor.BRFile; + +Processor.slt :: ¶Prelude®¶.¶Bit®¶ 32 -> ¶Prelude®¶.¶Bit®¶ 32 -> ¶Prelude®¶.¶Bit®¶ 32; + +Processor.sltu :: ¶Prelude®¶.¶Bit®¶ 32 -> ¶Prelude®¶.¶Bit®¶ 32 -> ¶Prelude®¶.¶Bit®¶ 32; + +Processor.rshft :: ¶Prelude®¶.¶Bit®¶ 32 -> ¶Prelude®¶.¶Bit®¶ 32; + +Processor.findwbf :: ProcTypes.Rindx -> ProcTypes.WBResult -> ¶Prelude®¶.¶Bool®¶; + +Processor.stall :: ProcTypes.Instr -> + SFIFO.SFIFO ProcTypes.WBResult ProcTypes.Rindx -> ¶Prelude®¶.¶Bool®¶; + +Processor.mkProc :: (¶Prelude®¶.¶IsModule®¶ _m__ _c__) => _m__ Processor.Proc +} diff -r 6d1ff93e3afa -r 91a1f76ddd62 core/sim/bdir_dut/Processor.bo Binary file core/sim/bdir_dut/Processor.bo has changed diff -r 6d1ff93e3afa -r 91a1f76ddd62 core/sim/bdir_dut/SFIFO.bi --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/core/sim/bdir_dut/SFIFO.bi Tue Apr 13 17:34:33 2010 -0400 @@ -0,0 +1,51 @@ +signature SFIFO where { +import ¶ConfigReg®¶; + +import ¶FIFOF_®¶; + +import ¶FIFOF®¶; + +import ¶FIFO®¶; + +import ¶List®¶; + +import ¶Monad®¶; + +import ¶RWire®¶; + +interface (SFIFO.SFIFO :: * -> * -> *) alpha_T search_T = { + SFIFO.enq :: alpha_T -> ¶Prelude®¶.¶Action®¶ {-# arg_names = [x] #-}; + SFIFO.deq :: ¶Prelude®¶.¶Action®¶ {-# arg_names = [] #-}; + SFIFO.first :: alpha_T {-# arg_names = [] #-}; + SFIFO.clear :: ¶Prelude®¶.¶Action®¶ {-# arg_names = [] #-}; + SFIFO.find :: search_T -> ¶Prelude®¶.¶Bool®¶ {-# arg_names = [x] #-}; + SFIFO.find2 :: search_T -> ¶Prelude®¶.¶Bool®¶ {-# arg_names = [x] #-} +}; + +instance SFIFO (¶Prelude®¶.¶PrimMakeUndefined®¶ alpha_T) => + ¶Prelude®¶.¶PrimMakeUndefined®¶ (SFIFO.SFIFO alpha_T search_T); + +instance SFIFO (¶Prelude®¶.¶PrimDeepSeqCond®¶ alpha_T) => + ¶Prelude®¶.¶PrimDeepSeqCond®¶ (SFIFO.SFIFO alpha_T search_T); + +instance SFIFO (¶Prelude®¶.¶PrimMakeUninitialized®¶ alpha_T) => + ¶Prelude®¶.¶PrimMakeUninitialized®¶ (SFIFO.SFIFO alpha_T search_T); + +SFIFO.mkSFIFO :: (¶Prelude®¶.¶Bits®¶ alpha_T asz, ¶Prelude®¶.¶IsModule®¶ _m__ _c__) => + (search_T -> alpha_T -> ¶Prelude®¶.¶Bool®¶) -> _m__ (SFIFO.SFIFO alpha_T search_T); + +SFIFO.mkSFIFO1 :: (¶Prelude®¶.¶Eq®¶ alpha_T, + ¶Prelude®¶.¶Bits®¶ alpha_T asz, + ¶Prelude®¶.¶IsModule®¶ _m__ _c__) => + (search_T -> alpha_T -> ¶Prelude®¶.¶Bool®¶) -> _m__ (SFIFO.SFIFO alpha_T search_T); + +SFIFO.mkSizedSFIFOInternal :: (¶Prelude®¶.¶Bits®¶ alpha_T alpha_SZ, + ¶Prelude®¶.¶IsModule®¶ _m__ _c__) => + ¶Prelude®¶.¶Integer®¶ -> + (search_T -> alpha_T -> ¶Prelude®¶.¶Bool®¶) -> + (search_T -> alpha_T -> ¶Prelude®¶.¶Bool®¶) -> _m__ (SFIFO.SFIFO alpha_T search_T); + +SFIFO.mkSizedSFIFO :: (¶Prelude®¶.¶Bits®¶ alpha_T asz, ¶Prelude®¶.¶IsModule®¶ _m__ _c__) => + ¶Prelude®¶.¶Integer®¶ -> + (search_T -> alpha_T -> ¶Prelude®¶.¶Bool®¶) -> _m__ (SFIFO.SFIFO alpha_T search_T) +} diff -r 6d1ff93e3afa -r 91a1f76ddd62 core/sim/bdir_dut/SFIFO.bo Binary file core/sim/bdir_dut/SFIFO.bo has changed diff -r 6d1ff93e3afa -r 91a1f76ddd62 core/sim/bdir_dut/SceMiLayer.bi --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/core/sim/bdir_dut/SceMiLayer.bi Tue Apr 13 17:34:33 2010 -0400 @@ -0,0 +1,174 @@ +signature SceMiLayer where { +import ¶Assert®¶; + +import ¶ConfigReg®¶; + +import ¶Counter®¶; + +import ¶DReg®¶; + +import ¶EdgeDetect®¶; + +import ¶FIFOF_®¶; + +import ¶FIFOF®¶; + +import ¶FIFO®¶; + +import ¶HList®¶; + +import ¶Inout®¶; + +import ¶List®¶; + +import BFIFO; + +import ¶Clocks®¶; + +import ¶DiniPCIE®¶; + +import ¶ListN®¶; + +import ¶ModuleContextCore®¶; + +import ¶ModuleContext®¶; + +import ¶Monad®¶; + +import ¶PrimArray®¶; + +import ¶RWire®¶; + +import ¶RegFile®¶; + +import ¶Real®¶; + +import ¶RevertingVirtualReg®¶; + +import ¶Reserved®¶; + +import SFIFO; + +import ¶Vector®¶; + +import ¶BRAMCore®¶; + +import ¶BUtils®¶; + +import ¶Connectable®¶; + +import ¶DefaultValue®¶; + +import ¶Gearbox®¶; + +import ¶GetPut®¶; + +import ¶AlignedFIFOs®¶; + +import ¶ClientServer®¶; + +import ¶FIFOLevel®¶; + +import ¶SceMiDefines®¶; + +import ¶SceMiProxies®¶; + +import ¶SpecialFIFOs®¶; + +import ¶SceMiInternals®¶; + +import ¶SceMiAldecMacros®¶; + +import ¶SceMiEveMacros®¶; + +import ¶SceMiMacros®¶; + +import ¶TieOff®¶; + +import Trace; + +import MemTypes; + +import MemArb; + +import ProcTypes; + +import BRegFile; + +import BranchPred; + +import DataCacheBlocking; + +import InstCacheBlocking; + +import Processor; + +import Core; + +import ¶UnitAppendList®¶; + +import ¶XilinxCells®¶; + +import ¶SceMiClocks®¶; + +import ¶SceMiDiniPCIE®¶; + +import ¶SceMiTCP®¶; + +import ¶XilinxPCIE®¶; + +import ¶SceMiVirtex5PCIE®¶; + +import ¶SceMiPCIE®¶; + +import ¶SceMiCore®¶; + +import ¶SceMiXactors®¶; + +import ¶SceMiSerialProbe®¶; + +import ¶SceMi®¶; + +interface (SceMiLayer.DutWrapper :: *) = { + SceMiLayer.core :: Core.Core; + SceMiLayer.doreset :: ¶GetPut®¶.¶Put®¶ (¶Prelude®¶.¶Bit®¶ 1) +}; + +instance SceMiLayer ¶Prelude®¶.¶PrimMakeUndefined®¶ SceMiLayer.DutWrapper; + +instance SceMiLayer ¶Prelude®¶.¶PrimDeepSeqCond®¶ SceMiLayer.DutWrapper; + +instance SceMiLayer ¶Prelude®¶.¶PrimMakeUninitialized®¶ SceMiLayer.DutWrapper; + +SceMiLayer.mkDutWrapper :: ¶Prelude®¶.¶Module®¶ SceMiLayer.DutWrapper; + +SceMiLayer.mkSceMiLayer :: ¶SceMiInternals®¶.¶SceMiModule®¶ ¶Prelude®¶.¶Empty®¶; + +SceMiLayer.mkCPUToHostXactor :: Processor.CPUToHost -> + ¶SceMiDefines®¶.¶SceMiClockPortIfc®¶ -> + ¶SceMiInternals®¶.¶SceMiModule®¶ ¶Prelude®¶.¶Empty®¶; + +data (SceMiLayer.StatID :: *) = + SceMiLayer.DCACHE_ACCESSES () | + SceMiLayer.DCACHE_MISSES () | + SceMiLayer.DCACHE_WRITEBACKS () | + SceMiLayer.ICACHE_ACCESSES () | + SceMiLayer.ICACHE_MISSES () | + SceMiLayer.ICACHE_EVICTIONS () | + SceMiLayer.PROC_INST () | + SceMiLayer.PROC_CYCLES (); + +instance SceMiLayer ¶Prelude®¶.¶PrimMakeUndefined®¶ SceMiLayer.StatID; + +instance SceMiLayer ¶Prelude®¶.¶PrimDeepSeqCond®¶ SceMiLayer.StatID; + +instance SceMiLayer ¶Prelude®¶.¶PrimMakeUninitialized®¶ SceMiLayer.StatID; + +instance SceMiLayer ¶Prelude®¶.¶Bits®¶ SceMiLayer.StatID 3; + +instance SceMiLayer ¶Prelude®¶.¶Eq®¶ SceMiLayer.StatID; + +SceMiLayer.mkCoreStatsXactor :: Core.CoreStats -> + ¶SceMiDefines®¶.¶SceMiClockPortIfc®¶ -> + ¶SceMiInternals®¶.¶SceMiModule®¶ ¶Prelude®¶.¶Empty®¶ +} diff -r 6d1ff93e3afa -r 91a1f76ddd62 core/sim/bdir_dut/SceMiLayer.bo Binary file core/sim/bdir_dut/SceMiLayer.bo has changed diff -r 6d1ff93e3afa -r 91a1f76ddd62 core/sim/bdir_dut/Trace.bi --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/core/sim/bdir_dut/Trace.bi Tue Apr 13 17:34:33 2010 -0400 @@ -0,0 +1,56 @@ +signature Trace where { +import ¶Counter®¶; + +import ¶FIFOF_®¶; + +import ¶FIFOF®¶; + +import ¶FIFO®¶; + +import ¶Inout®¶; + +import ¶List®¶; + +import ¶Clocks®¶; + +import ¶ListN®¶; + +import ¶PrimArray®¶; + +import ¶Vector®¶; + +import ¶Connectable®¶; + +import ¶GetPut®¶; + +import ¶ClientServer®¶; + +class (Trace.Traceable :: * -> *) item_t where { + Trace.traceTiny :: ¶Prelude®¶.¶String®¶ -> + ¶Prelude®¶.¶String®¶ -> item_t -> ¶Prelude®¶.¶Action®¶ {-# arg_names = [loc, traceTag, item] #-}; + Trace.traceFull :: ¶Prelude®¶.¶String®¶ -> + ¶Prelude®¶.¶String®¶ -> item_t -> ¶Prelude®¶.¶Action®¶ {-# arg_names = [loc, traceTag, item] #-} +}; + +instance Trace Trace.Traceable ¶Prelude®¶.¶String®¶; + +instance Trace Trace.Traceable (¶Prelude®¶.¶Bit®¶ n); + +Trace.traceGet :: (Trace.Traceable item_t) => + ¶Prelude®¶.¶String®¶ -> ¶Prelude®¶.¶String®¶ -> ¶GetPut®¶.¶Get®¶ item_t -> ¶GetPut®¶.¶Get®¶ item_t; + +Trace.tracePut :: (Trace.Traceable item_t) => + ¶Prelude®¶.¶String®¶ -> ¶Prelude®¶.¶String®¶ -> ¶GetPut®¶.¶Put®¶ item_t -> ¶GetPut®¶.¶Put®¶ item_t; + +Trace.traceClient :: (Trace.Traceable resp_t, Trace.Traceable req_t) => + ¶Prelude®¶.¶String®¶ -> + ¶Prelude®¶.¶String®¶ -> + ¶Prelude®¶.¶String®¶ -> + ¶ClientServer®¶.¶Client®¶ req_t resp_t -> ¶ClientServer®¶.¶Client®¶ req_t resp_t; + +Trace.traceServer :: (Trace.Traceable resp_t, Trace.Traceable req_t) => + ¶Prelude®¶.¶String®¶ -> + ¶Prelude®¶.¶String®¶ -> + ¶Prelude®¶.¶String®¶ -> + ¶ClientServer®¶.¶Server®¶ req_t resp_t -> ¶ClientServer®¶.¶Server®¶ req_t resp_t +} diff -r 6d1ff93e3afa -r 91a1f76ddd62 core/sim/bdir_dut/Trace.bo Binary file core/sim/bdir_dut/Trace.bo has changed diff -r 6d1ff93e3afa -r 91a1f76ddd62 core/sim/bdir_dut/mkBFIFO_16.ba Binary file core/sim/bdir_dut/mkBFIFO_16.ba has changed diff -r 6d1ff93e3afa -r 91a1f76ddd62 core/sim/bdir_dut/mkBridge.ba Binary file core/sim/bdir_dut/mkBridge.ba has changed diff -r 6d1ff93e3afa -r 91a1f76ddd62 core/sim/bdir_dut/mkCore.ba Binary file core/sim/bdir_dut/mkCore.ba has changed diff -r 6d1ff93e3afa -r 91a1f76ddd62 core/sim/bdir_dut/mkDataCache.ba Binary file core/sim/bdir_dut/mkDataCache.ba has changed diff -r 6d1ff93e3afa -r 91a1f76ddd62 core/sim/bdir_dut/mkDutWrapper.ba Binary file core/sim/bdir_dut/mkDutWrapper.ba has changed diff -r 6d1ff93e3afa -r 91a1f76ddd62 core/sim/bdir_dut/mkInstCache.ba Binary file core/sim/bdir_dut/mkInstCache.ba has changed diff -r 6d1ff93e3afa -r 91a1f76ddd62 core/sim/bdir_dut/mkMemArb.ba Binary file core/sim/bdir_dut/mkMemArb.ba has changed diff -r 6d1ff93e3afa -r 91a1f76ddd62 core/sim/bdir_dut/mkProc.ba Binary file core/sim/bdir_dut/mkProc.ba has changed diff -r 6d1ff93e3afa -r 91a1f76ddd62 core/sim/scemi.params --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/core/sim/scemi.params Tue Apr 13 17:34:33 2010 -0400 @@ -0,0 +1,70 @@ +// Sce-Mi parameters file generated on: Mon Apr 12 09:58:28 EDT 2010 +// By: Bluespec scemilink utility, version 2010.02.beta4 (build 19725, 2010-02-26) + +// ObjectKind Index AttributeName Value + +Clock 0 ClockName "scemi_clk_port" +Clock 0 RatioNumerator 1 +Clock 0 RatioDenominator 1 +Clock 0 DutyHi 0 +Clock 0 DutyLo 100 +Clock 0 Phase 0 +Clock 0 ResetCycles 8 + +MessageOutPort 3 TransactorName "" +MessageOutPort 3 PortName "scemi_tohost_response_outport" +MessageOutPort 3 PortWidth 32 +MessageOutPort 3 ChannelId 9 +MessageOutPort 3 Type "Bit#(32)" + +MessageOutPort 2 TransactorName "" +MessageOutPort 2 PortName "scemi_stats_xx_resp_outport" +MessageOutPort 2 PortWidth 18 +MessageOutPort 2 ChannelId 8 +MessageOutPort 2 Type "Int#(18)" + +MessageOutPort 1 TransactorName "" +MessageOutPort 1 PortName "scemi_shutdown_ctrl_out" +MessageOutPort 1 PortWidth 1 +MessageOutPort 1 ChannelId 7 +MessageOutPort 1 Type "Bool" + +MessageOutPort 0 TransactorName "" +MessageOutPort 0 PortName "scemi_mmem_req_outport" +MessageOutPort 0 PortWidth 73 +MessageOutPort 0 ChannelId 6 +MessageOutPort 0 Type "MemTypes::MemReq#(32,8,32)" + +MessageInPort 4 TransactorName "" +MessageInPort 4 PortName "scemi_tohost_request_inport" +MessageInPort 4 PortWidth 32 +MessageInPort 4 ChannelId 5 +MessageInPort 4 Type "Int#(32)" + +MessageInPort 3 TransactorName "" +MessageInPort 3 PortName "scemi_stats_xx_req_inport" +MessageInPort 3 PortWidth 3 +MessageInPort 3 ChannelId 4 +MessageInPort 3 Type "SceMiLayer::StatID" + +MessageInPort 2 TransactorName "" +MessageInPort 2 PortName "scemi_shutdown_ctrl_in" +MessageInPort 2 PortWidth 1 +MessageInPort 2 ChannelId 3 +MessageInPort 2 Type "Bool" + +MessageInPort 1 TransactorName "" +MessageInPort 1 PortName "scemi_mmem_resp_inport" +MessageInPort 1 PortWidth 41 +MessageInPort 1 ChannelId 2 +MessageInPort 1 Type "MemTypes::MemResp#(8,32)" + +MessageInPort 0 TransactorName "" +MessageInPort 0 PortName "scemi_doreset_inport" +MessageInPort 0 PortWidth 1 +MessageInPort 0 ChannelId 1 +MessageInPort 0 Type "Bit#(1)" + +Link 0 LinkType "TCP" +Link 0 TCPAddress "127.0.0.1" +Link 0 TCPPort 4321 diff -r 6d1ff93e3afa -r 91a1f76ddd62 core/sim/sim.bspec --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/core/sim/sim.bspec Tue Apr 13 17:34:33 2010 -0400 @@ -0,0 +1,86 @@ +### Bluespec project file. +### Generated by Bluespec Workstation on Fri Mar 19 21:06:20 EDT 2010 + +global PROJECT + +set PROJECT(COMP_BDIR) "bdir_dut" +set PROJECT(COMP_BSC_OPTIONS) "-keep-fires -aggressive-conditions -D SCEMI_TCP" +set PROJECT(COMP_BSC_TYPE) "bluesim" +set PROJECT(COMP_INFO_DIR) "info_dut" +set PROJECT(COMP_RTS_OPTIONS) "" +set PROJECT(COMP_SIMDIR) "simdir_dut" +set PROJECT(COMP_TYPE) "bsc" +set PROJECT(TB_COMP_TYPE) "ccd" +set PROJECT(COMP_VDIR) "vlog_dut" +set PROJECT(CURRENT_DIR) "" +set PROJECT(EDITOR_NAME) "other" +set PROJECT(EXCLUDED_FILES) "" +set PROJECT(INCLUDED_FILES) "*.bsv" +set PROJECT(GEN_FILES) "" +set PROJECT(LINK_BSC_OPTIONS) "-keep-fires" +set PROJECT(LINK_COMMAND) "build -f link_for_bluesim -t link_for_bluesim" +set PROJECT(LINK_MAKEFILE) "Makefile" +set PROJECT(LINK_MAKE_OPTIONS) "" +set PROJECT(LINK_OUTDIR) "." +set PROJECT(LINK_OUTNAME) "out" +set PROJECT(LINK_SIM_TARGET) "" +set PROJECT(LINK_CLEAN_TARGET) "" +set PROJECT(LINK_FULL_CLEAN_TARGET) "" +set PROJECT(LINK_TARGET) "" +set PROJECT(LINK_TYPE) "custom_command" +set PROJECT(MAIN_PLACEMENT) "700x350+0+0" +set PROJECT(MAKE_CLEAN) "clean" +set PROJECT(MAKE_FILE) "Makefile" +set PROJECT(MAKE_FULLCLEAN) "clean" +set PROJECT(MAKE_OPTIONS) "" +set PROJECT(MAKE_TARGET) "" +set PROJECT(MODULE_PLACEMENT) "500x350+50+500" +set PROJECT(PATHS) "bdir_dut . %/Prelude %/Libraries %/board_support/bridges ./../scemi ./../src" +set PROJECT(PACKAGE_PLACEMENT) "770x420+475+150" +set PROJECT(PROJECT_PLACEMENT) "250x460+0+385" +set PROJECT(RUN_OPTIONS) "" +set PROJECT(SCHEDULE_PLACEMENT) "650x650+500+225" +set PROJECT(SCEMI_ENABLE) "1" +set PROJECT(SCEMI_LINK_OPTIONS) "--sim --params=scemi.params" +set PROJECT(SCEMI_COMP_MAKEFILE) "" +set PROJECT(SCEMI_BSVTB) "0" +set PROJECT(SCEMI_TB_FILE) "" +set PROJECT(SCEMI_TB_MOD) "" +set PROJECT(SCEMI_COMPBSC) "off" +set PROJECT(SCEMI_COMPOPT) "" +set PROJECT(SCEMI_BSC_LINK_NAME) "" +set PROJECT(SCEMI_BSC_LINK_ODIR) "" +set PROJECT(SCEMI_BSC_LINK_OPTS) "" +set PROJECT(SCEMI_BSC_LINK_RUNOPTS) "" +set PROJECT(SCEMI_COMP_TARGET) "" +set PROJECT(SCEMI_BSC_LINKMK_TARGET) "" +set PROJECT(SCEMI_BSC_LINKMK_RUN) "" +set PROJECT(SCEMI_TB_CC_CC) "build tb" +set PROJECT(SCEMI_TB_CC_LINK) "echo linked" +set PROJECT(SCEMI_TB_CC_RUN) "./tb" +set PROJECT(SIM_CUSTOM_COMMAND) "./bsim_dut 2> err.txt" +set PROJECT(SIM_EXE) "" +set PROJECT(SIM_NAME) "cvc" +set PROJECT(SIM_OPTIONS) "" +set PROJECT(SOURCE) "" +set PROJECT(STATUS) "" +set PROJECT(TOP_FILE) "../scemi/Bridge.bsv" +set PROJECT(TOP_MODULE) "mkBridge" +set PROJECT(TYPE_PLACEMENT) "770x420+475+540" +set PROJECT(VIEWER_CLOSE) "close" +set PROJECT(WIZARD_PLACEMENT) "1024x700+50+50" +set PROJECT(EDITOR_GVIM) "gvim" +set PROJECT(EDITOR_EMACS) "emacs" +set PROJECT(EDITOR_OTHER) "/usr/bin/vim %f" +::Waves::set_options {Mentor,Command} {Not supported} +::Waves::set_options {GtkWave,Options} {-W} +::Waves::set_options {viewer} {Novas} +::Waves::set_options {Novas,Command} {nWave} +::Waves::set_options {Mentor,Options} {Not supported} +::Waves::set_options {ExtendNameMode} {noextend} +::Waves::set_options {Novas,Options} {-nologo} +::Waves::set_options {BoolDisplayMode} {nobenum} +::Waves::set_options {nonbsv_hierarchy} {/main/top} +::Waves::set_options {GtkWave,Command} {gtkx} +::Waves::set_options {StartTimeout} {20} +::Waves::set_options {DumpExtensions} {vcd fsdb wlf} diff -r 6d1ff93e3afa -r 91a1f76ddd62 core/src/BFIFO.bsv --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/core/src/BFIFO.bsv Tue Apr 13 17:34:33 2010 -0400 @@ -0,0 +1,222 @@ +import FIFO::*; +import FIFOF::*; +import List::*; +import Assert::*; + +module mkBFIFO1( FIFO#(item_t) ) provisos ( Bits#(item_t,item_sz) ); + + RWire#(item_t) inputWire <- mkRWire(); + PulseWire deqEnabled <- mkPulseWire(); + PulseWire clearEnabled <- mkPulseWire(); + + Reg#(item_t) register <- mkRegU(); + Reg#(Bool) valid <- mkReg(False); + + // If there is an input item on the inputWire wire and dequeue did not + // execute this cycle then we need to store the item in the register + + (*fire_when_enabled*) + rule update ( True ); + case (inputWire.wget()) matches + tagged Invalid: + if (deqEnabled || clearEnabled) + valid <= False; + tagged Valid .x: + begin + register <= x; + valid <= !(deqEnabled || clearEnabled); + end + endcase + endrule + + // On enqueue we write the input item to the inputWire wire + + method Action enq( item_t item ) if ( !valid ); + inputWire.wset(item); + endmethod + + // On dequeue we always invalidate the storage register regardless + // of whether or not the item was actually bypassed or not. We also + // set a combinational signal so that we know not to move the item + // into the register this cycle. + + method Action deq() if ( valid || isValid(inputWire.wget()) ); + deqEnabled.send(); + endmethod + + // We get the item either from the register (if register is valid) or + // from the combinational bypasss (if the rwire is valid). + + method item_t first() if ( valid || isValid(inputWire.wget()) ); + if ( valid ) + return register; + else + return unJust(inputWire.wget()); + endmethod + + method Action clear(); + clearEnabled.send(); + endmethod + +endmodule + +module mkSizedBFIFO#(Integer n) ( FIFO#(item_t) ) provisos ( Bits#(item_t,item_sz) ); + + RWire#(item_t) inputWire <- mkRWire(); + PulseWire deqEnabled <- mkPulseWire(); + PulseWire clearEnabled <- mkPulseWire(); + + List#(Reg#(item_t)) registers <- replicateM(n, mkRegU); + List#(Reg#(Bool)) valids <- replicateM(n, mkReg(False)); + + function Nat getNextFree (List#(Reg#(Bool)) vs); + + Nat res = fromInteger(n - 1); + + for (Integer x = n - 1; x > -1; x = x - 1) + res = !vs[x]._read() ? fromInteger(x) : res; + + return res; + + endfunction + + function Bool notFull(); + + Bool full = True; + + for (Integer x = 0; x < length(valids); x = x + 1) + full = full && valids[x]._read(); + + return !full; + + endfunction + // If there is an input item on the inputWire wire and dequeue did not + // execute this cycle then we need to store the item in the register + + rule update ( True ); + Nat next = getNextFree(valids); + + next = (deqEnabled) ? next - 1 : next; + + (valids[next]) <= isValid(inputWire.wget()); + (registers[next]) <= validValue(inputWire.wget()); + + if (deqEnabled && !clearEnabled) + begin + + for (Nat x = 0; x < (next - 1); x = x + 1) + begin + (valids[x]) <= valids[x+1]._read(); + (registers[x]) <= registers[x+1]._read(); + end + + end + else if (clearEnabled) + begin + + for (Integer x = 0; x < n; x = x + 1) + (valids[x]) <= False; + + end + endrule + + // On enqueue we write the input item to the inputWire wire + + method Action enq( item_t item ) if ( notFull ); + inputWire.wset(item); + endmethod + + // On dequeue we always invalidate the storage register regardless + // of whether or not the item was actually bypassed or not. We also + // set a combinational signal so that we know not to move the item + // into the register this cycle. + + method Action deq() if ( valids[0]._read() || isValid(inputWire.wget()) ); + deqEnabled.send(); + endmethod + + // We get the item either from the register (if register is valid) or + // from the combinational bypasss (if the rwire is valid). + + method item_t first() if ( valids[0]._read() || isValid(inputWire.wget()) ); + if ( valids[0]._read() ) + return registers[0]._read(); + else + return unJust(inputWire.wget()); + endmethod + + + method Action clear(); + clearEnabled.send(); + endmethod + +endmodule + + +module mkBFIFOF1( FIFOF#(item_t) ) provisos ( Bits#(item_t,item_sz) ); + + RWire#(item_t) inputWire <- mkRWire(); + RWire#(Bool) deqEnabled <- mkRWire(); + + Reg#(Maybe#(item_t)) register <- mkReg(Invalid); + + // If there is an input item on the inputWire wire and dequeue did not + // execute this cycle then we need to store the item in the register + + rule noDeq ( isValid(inputWire.wget()) && !isValid(deqEnabled.wget()) ); + register <= inputWire.wget(); + endrule + + // On enqueue we write the input item to the inputWire wire + + method Action enq( item_t item ) if ( !isValid(register) ); + inputWire.wset(item); + endmethod + + // On dequeue we always invalidate the storage register regardless + // of whether or not the item was actually bypassed or not. We also + // set a combinational signal so that we know not to move the item + // into the register this cycle. + + method Action deq() if ( isValid(register) || isValid(inputWire.wget()) ); + register <= Invalid; + deqEnabled.wset(True); + endmethod + + // We get the item either from the register (if register is valid) or + // from the combinational bypasss (if the rwire is valid). + + method item_t first() if ( isValid(register) || isValid(inputWire.wget()) ); + if ( isValid(register) ) + return unJust(register); + else + return unJust(inputWire.wget()); + endmethod + + // FIFOF adds the following two methods + + method Bool notFull(); + return !isValid(register); + endmethod + + method Bool notEmpty(); + return (isValid(register) || isValid(inputWire.wget())); + endmethod + + // Not sure about the clear method ... + + method Action clear(); + dynamicAssert( False, "BFIFO.clear() not implemented yet!" ); + endmethod + +endmodule + +(* synthesize *) +module mkBFIFO_16 (FIFO#(Bit#(16))); + + let f <- mkBFIFO1(); + + return f; + +endmodule + diff -r 6d1ff93e3afa -r 91a1f76ddd62 core/src/BRegFile.bsv --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/core/src/BRegFile.bsv Tue Apr 13 17:34:33 2010 -0400 @@ -0,0 +1,36 @@ +import RegFile::*; +import RWire::*; +import ProcTypes::*; + +//----------------------------------------------------------- +// Register file module +//----------------------------------------------------------- + +interface BRegFile #(type index_t, type data_t); + method Action upd(index_t addr, data_t data); + method data_t sub(index_t addr); +endinterface + +module mkBRegFile(RegFile#(index_t, data_t)) + provisos (Bits#(index_t, size_index), + Bits#(data_t, size_data), + Eq#(index_t), + Bounded#(index_t) ); + + RegFile#(index_t, data_t) rf <- mkRegFileWCF(minBound, maxBound); + RWire#(Tuple2#(index_t, data_t)) rw <-mkRWire(); + + method Action upd (index_t r, data_t d); + rf.upd(r,d); + rw.wset(tuple2(r,d)); + endmethod + + method data_t sub (index_t r); + case (rw.wget()) matches + tagged Valid {.wr, .d} : + return (wr == r) ? d : rf.sub(r); + tagged Invalid : return rf.sub(r); + endcase + endmethod + +endmodule diff -r 6d1ff93e3afa -r 91a1f76ddd62 core/src/BranchPred.bsv --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/core/src/BranchPred.bsv Tue Apr 13 17:34:33 2010 -0400 @@ -0,0 +1,41 @@ +import RegFile::*; +import ProcTypes::*; +import FIFO::*; + +typedef Maybe#(Addr) BrPred; +typedef Bit#(4) BPindx; + +typedef struct {Addr brpc; Addr nextpc;} BrPair deriving (Bits,Eq); + +typedef union tagged +{ + BrPair Valid; + void Invalid; +} CBranchPath deriving(Bits, Eq); // have the cache start out invalid and add valid values. + +interface BranchPred; + method BrPred get(Addr pres); //returns a maybe type that is invalid if no predition + method Action upd(Addr pres, Addr next); +endinterface + +module mkBranchPred(BranchPred); + + //state variables + RegFile#(BPindx, CBranchPath) bcache <- mkRegFileFull(); // cache to hold 16 (based on BPindx) + + method Action upd(Addr pres, Addr next); + BrPair brp; + brp = BrPair {brpc:pres, nextpc:next}; + bcache.upd(pres[5:2], tagged Valid brp); + endmethod + + method BrPred get(Addr prespc); + BPindx rd = prespc[5:2]; + let cbp = bcache.sub(rd); + if (cbp matches tagged Valid .bp &&& bp.brpc == prespc) //make sure that the read value was actually put there and the full address matches + return tagged Valid bp.nextpc; + else return Invalid; + endmethod + +endmodule + diff -r 6d1ff93e3afa -r 91a1f76ddd62 core/src/Core.bsv --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/core/src/Core.bsv Tue Apr 13 17:34:33 2010 -0400 @@ -0,0 +1,81 @@ +// The MIT License + +// Copyright (c) 2009 Massachusetts Institute of Technology + +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: + +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. + +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +// THE SOFTWARE. + +import Connectable::*; +import GetPut::*; +import ClientServer::*; + +import DataCacheBlocking::*; +import InstCacheBlocking::*; +import Processor::*; +import MemArb::*; +import MemTypes::*; + +interface CoreStats; + interface DCacheStats dcache; + interface ICacheStats icache; + interface ProcStats proc; +endinterface + +interface Core; + + // Interface from core to main memory + interface Client#(MainMemReq,MainMemResp) mmem_client; + + // Statistics + interface CoreStats stats; + + // CPU to Host + interface CPUToHost tohost; + +endinterface + +(* synthesize *) +module mkCore(Core); + + // Instantiate the modules + Proc proc <- mkProc(); + ICache#(InstReq,InstResp) icache <- mkInstCache(); + DCache#(DataReq,DataResp) dcache <- mkDataCache(); + MemArb marb <- mkMemArb(); + + // Internal connections + mkConnection( proc.statsEn_get, icache.statsEn_put ); + mkConnection( proc.statsEn_get, dcache.statsEn_put ); + mkConnection( proc.imem_client, icache.proc_server ); + mkConnection( proc.dmem_client, dcache.proc_server ); + mkConnection( icache.mmem_client, marb.cache0_server ); + mkConnection( dcache.mmem_client, marb.cache1_server ); + + // Methods + interface mmem_client = marb.mmem_client; + + interface CoreStats stats; + interface dcache = dcache.stats; + interface icache = icache.stats; + interface proc = proc.stats; + endinterface + + interface CPUToHost tohost = proc.tohost; + +endmodule + diff -r 6d1ff93e3afa -r 91a1f76ddd62 core/src/DataCacheBlocking.bsv --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/core/src/DataCacheBlocking.bsv Tue Apr 13 17:34:33 2010 -0400 @@ -0,0 +1,295 @@ +// The MIT License + +// Copyright (c) 2009 Massachusetts Institute of Technology + +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: + +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. + +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +// THE SOFTWARE. + +import Connectable::*; +import GetPut::*; +import ClientServer::*; +import RegFile::*; +import FIFO::*; +import FIFOF::*; + +import BFIFO::*; +import MemTypes::*; +import ProcTypes::*; +import Trace::*; + +interface DCacheStats; + interface Get#(Stat) num_accesses; + interface Get#(Stat) num_misses; + interface Get#(Stat) num_writebacks; +endinterface + +interface DCache#( type req_t, type resp_t ); + + // Interface from processor to cache + interface Server#(req_t,resp_t) proc_server; + + // Interface from cache to main memory + interface Client#(MainMemReq,MainMemResp) mmem_client; + + // Interface for enabling/disabling statistics + interface Put#(Bool) statsEn_put; + + // Interface for collecting statistics + interface DCacheStats stats; + +endinterface + + +//---------------------------------------------------------------------- +// Cache Types +//---------------------------------------------------------------------- + +typedef 10 CacheLineIndexSz; +typedef 20 CacheLineTagSz; +typedef 32 CacheLineSz; + +typedef Bit#(CacheLineIndexSz) CacheLineIndex; +typedef Bit#(CacheLineTagSz) CacheLineTag; +typedef Bit#(CacheLineSz) CacheLine; + +typedef enum +{ + Init, + Access, + RefillReq, + RefillResp +} +CacheStage +deriving (Eq,Bits); + +//---------------------------------------------------------------------- +// Helper functions +//---------------------------------------------------------------------- + +function Bit#(AddrSz) getAddr( DataReq req ); + + Bit#(AddrSz) addr = ?; + case ( req ) matches + tagged LoadReq .ld : addr = ld.addr; + tagged StoreReq .st : addr = st.addr; + endcase + + return addr; + +endfunction + +function CacheLineIndex getCacheLineIndex( DataReq req ); + Bit#(AddrSz) addr = getAddr(req); + Bit#(CacheLineIndexSz) index = truncate( addr >> 2 ); + return index; +endfunction + +function CacheLineTag getCacheLineTag( DataReq req ); + Bit#(AddrSz) addr = getAddr(req); + Bit#(CacheLineTagSz) tag = truncate( addr >> fromInteger(valueOf(CacheLineIndexSz)) >> 2 ); + return tag; +endfunction + +function Bit#(AddrSz) getCacheLineAddr( DataReq req ); + Bit#(AddrSz) addr = getAddr(req); + return ((addr >> 2) << 2); +endfunction + +//---------------------------------------------------------------------- +// Main module +//---------------------------------------------------------------------- + +(* doc = "synthesis attribute ram_style mkDataCache distributed;" *) +(* synthesize *) +module mkDataCache( DCache#(DataReq,DataResp) ); + + //----------------------------------------------------------- + // State + + Reg#(CacheStage) stage <- mkReg(Init); + + RegFile#(CacheLineIndex,Maybe#(CacheLineTag)) cacheTagRam <- mkRegFileFull(); + RegFile#(CacheLineIndex,CacheLine) cacheDataRam <- mkRegFileFull(); + + FIFO#(DataReq) reqQ <- mkFIFO(); + FIFOF#(DataResp) respQ <- mkBFIFOF1(); + + FIFO#(MainMemReq) mainMemReqQ <- mkBFIFO1(); + FIFO#(MainMemResp) mainMemRespQ <- mkFIFO(); + + Reg#(CacheLineIndex) initCounter <- mkReg(1); + + // Statistics state + + Reg#(Bool) statsEn <- mkReg(False); + + Reg#(Stat) num_accesses <- mkReg(0); + Reg#(Stat) num_misses <- mkReg(0); + Reg#(Stat) num_writebacks <- mkReg(0); + + //----------------------------------------------------------- + // Name some wires + + let req = reqQ.first(); + let reqIndex = getCacheLineIndex(req); + let reqTag = getCacheLineTag(req); + let reqCacheLineAddr = getCacheLineAddr(req); + + //----------------------------------------------------------- + // Initialize + + rule init ( stage == Init ); + traceTiny("mkDataCacheBlocking", "stage","i"); + initCounter <= initCounter + 1; + cacheTagRam.upd(initCounter,Invalid); + if ( initCounter == 0 ) + stage <= Access; + endrule + + //----------------------------------------------------------- + // Access cache rule + + rule access ( (stage == Access) && respQ.notFull() ); + + // Statistics + + if ( statsEn ) + num_accesses <= num_accesses + 1; + + + // Get the corresponding tag from the rams + + Maybe#(CacheLineTag) cacheLineTag = cacheTagRam.sub(reqIndex); + + // Handle cache hits ... + + if ( isValid(cacheLineTag) && ( unJust(cacheLineTag) == reqTag ) ) + begin + traceTiny("mkDataCacheBlocking", "hitMiss","h"); + reqQ.deq(); + + case ( req ) matches + + tagged LoadReq .ld : + respQ.enq( LoadResp { tag: ld.tag, data: cacheDataRam.sub(reqIndex) } ); + + tagged StoreReq .st : + begin + respQ.enq( StoreResp { tag : st.tag } ); + cacheDataRam.upd(reqIndex,st.data); + end + + endcase + + end + + // Handle cache misses ... + + else + begin + traceTiny("mkDataCacheBlocking", "hitMiss","m"); + if ( statsEn ) + num_misses <= num_misses + 1; + + // Currently we don't use dirty bits so we always writeback the data if it is valid + + if ( isValid(cacheLineTag) ) + begin + + if ( statsEn ) + num_writebacks <= num_writebacks + 1; + + MainMemReq wbReq + = StoreReq { tag : 0, + addr : { unJust(cacheLineTag), reqIndex, 2'b0 }, + data : cacheDataRam.sub(reqIndex) }; + + mainMemReqQ.enq(wbReq); + stage <= RefillReq; + end + + // Otherwise we can issue the refill request now + + else + begin + mainMemReqQ.enq( LoadReq { tag: 0, addr: reqCacheLineAddr } ); + stage <= RefillResp; + end + + end + + endrule + + //----------------------------------------------------------- + // Refill request rule + + rule refillReq ( stage == RefillReq ); + traceTiny("mkDataCacheBlocking", "stage","r"); + mainMemReqQ.enq( LoadReq { tag: 0, addr: reqCacheLineAddr } ); + stage <= RefillResp; + endrule + + //----------------------------------------------------------- + // Refill response rule + + rule refillResp ( stage == RefillResp ); + traceTiny("mkDataCacheBlocking", "stage","R"); + traceTiny("mkDataCacheBlocking", "refill",mainMemRespQ.first()); + + // Write the new data into the cache and update the tag + + mainMemRespQ.deq(); + case ( mainMemRespQ.first() ) matches + + tagged LoadResp .ld : + begin + cacheTagRam.upd(reqIndex,Valid(reqTag)); + cacheDataRam.upd(reqIndex,ld.data); + end + + tagged StoreResp .st : + noAction; + + endcase + + stage <= Access; + endrule + + //----------------------------------------------------------- + // Methods + + interface Client mmem_client; + interface Get request = toGet(mainMemReqQ); + interface Put response = toPut(mainMemRespQ); + endinterface + + interface Server proc_server; + interface Put request = tracePut("mkDataCacheBlocking", "reqTiny",toPut(reqQ)); + interface Get response = traceGet("mkDataCacheBlocking", "respTiny",toGet(respQ)); + endinterface + + interface Put statsEn_put = toPut(asReg(statsEn)); + + interface DCacheStats stats; + interface Get num_accesses = toGet(asReg(num_accesses)); + interface Get num_misses = toGet(asReg(num_misses)); + interface Get num_writebacks = toGet(asReg(num_writebacks)); + endinterface + +endmodule + diff -r 6d1ff93e3afa -r 91a1f76ddd62 core/src/InstCacheBlocking.bsv --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/core/src/InstCacheBlocking.bsv Tue Apr 13 17:34:33 2010 -0400 @@ -0,0 +1,269 @@ +// The MIT License + +// Copyright (c) 2009 Massachusetts Institute of Technology + +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: + +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. + +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +// THE SOFTWARE. + +import Connectable::*; +import GetPut::*; +import ClientServer::*; +import RegFile::*; +import FIFO::*; +import FIFOF::*; +import RWire::*; + +import BFIFO::*; +import MemTypes::*; +import ProcTypes::*; +import Trace::*; + +interface ICacheStats; + interface Get#(Stat) num_accesses; + interface Get#(Stat) num_misses; + interface Get#(Stat) num_evictions; +endinterface + +interface ICache#( type req_t, type resp_t ); + + // Interface from processor to cache + interface Server#(req_t,resp_t) proc_server; + + // Interface from cache to main memory + interface Client#(MainMemReq,MainMemResp) mmem_client; + + // Interface for enabling/disabling statistics + interface Put#(Bool) statsEn_put; + + // Interface for collecting statistics + interface ICacheStats stats; + +endinterface + +//---------------------------------------------------------------------- +// Cache Types +//---------------------------------------------------------------------- + +typedef 10 CacheLineIndexSz; +typedef 20 CacheLineTagSz; +typedef 32 CacheLineSz; + +typedef Bit#(CacheLineIndexSz) CacheLineIndex; +typedef Bit#(CacheLineTagSz) CacheLineTag; +typedef Bit#(CacheLineSz) CacheLine; + +typedef enum +{ + Init, + Access, + Evict, + RefillReq, + RefillResp +} +CacheStage +deriving (Eq,Bits); + +//---------------------------------------------------------------------- +// Helper functions +//---------------------------------------------------------------------- + +function Bit#(AddrSz) getAddr( InstReq req ); + + Bit#(AddrSz) addr = ?; + case ( req ) matches + tagged LoadReq .ld : addr = ld.addr; + tagged StoreReq .st : addr = st.addr; + endcase + + return addr; + +endfunction + +function CacheLineIndex getCacheLineIndex( InstReq req ); + Bit#(AddrSz) addr = getAddr(req); + Bit#(CacheLineIndexSz) index = truncate( addr >> 2 ); + return index; +endfunction + +function CacheLineTag getCacheLineTag( InstReq req ); + Bit#(AddrSz) addr = getAddr(req); + Bit#(CacheLineTagSz) tag = truncate( addr >> fromInteger(valueOf(CacheLineIndexSz)) >> 2 ); + return tag; +endfunction + +function Bit#(AddrSz) getCacheLineAddr( InstReq req ); + Bit#(AddrSz) addr = getAddr(req); + return ((addr >> 2) << 2); +endfunction + +//---------------------------------------------------------------------- +// Main module +//---------------------------------------------------------------------- + +(* doc = "synthesis attribute ram_style mkInstCache distributed;" *) +(* synthesize *) +module mkInstCache( ICache#(InstReq,InstResp) ); + + //----------------------------------------------------------- + // State + + Reg#(CacheStage) stage <- mkReg(Init); + + RegFile#(CacheLineIndex,Maybe#(CacheLineTag)) cacheTagRam <- mkRegFileFull(); + RegFile#(CacheLineIndex,CacheLine) cacheDataRam <- mkRegFileFull(); + + FIFO#(InstReq) reqQ <- mkFIFO(); + FIFOF#(InstResp) respQ <- mkBFIFOF1(); + + FIFO#(MainMemReq) mainMemReqQ <- mkBFIFO1(); + FIFO#(MainMemResp) mainMemRespQ <- mkFIFO(); + + Reg#(CacheLineIndex) initCounter <- mkReg(1); + + // Statistics state + + Reg#(Bool) statsEn <- mkReg(False); + + Reg#(Stat) numAccesses <- mkReg(0); + Reg#(Stat) numMisses <- mkReg(0); + Reg#(Stat) numEvictions <- mkReg(0); + + //----------------------------------------------------------- + // Name some wires + + let req = reqQ.first(); + let reqIndex = getCacheLineIndex(req); + let reqTag = getCacheLineTag(req); + let reqCacheLineAddr = getCacheLineAddr(req); + let refill = mainMemRespQ.first(); + + //----------------------------------------------------------- + // Initialize + + rule init ( stage == Init ); + traceTiny("mkInstCacheBlocking", "stage","i"); + initCounter <= initCounter + 1; + cacheTagRam.upd(initCounter,Invalid); + if ( initCounter == 0 ) + stage <= Access; + endrule + + //----------------------------------------------------------- + // Cache access rule + + rule access ( (stage == Access) && respQ.notFull() ); + + // Statistics + + if ( statsEn ) + numAccesses <= numAccesses + 1; + + // Check tag and valid bit to see if this is a hit or a miss + + Maybe#(CacheLineTag) cacheLineTag = cacheTagRam.sub(reqIndex); + + // Handle cache hits ... + + if ( isValid(cacheLineTag) && ( unJust(cacheLineTag) == reqTag ) ) + begin + traceTiny("mkInstCacheBlocking", "hitMiss","h"); + reqQ.deq(); + + case ( req ) matches + + tagged LoadReq .ld : + respQ.enq( LoadResp { tag : ld.tag, data : cacheDataRam.sub(reqIndex) } ); + + tagged StoreReq .st : + $display( " RTL-ERROR : %m : Stores are not allowed on the inst port!" ); + + endcase + + end + + // Handle cache misses - since lines in instruction cache are + // never dirty we can always immediately issue a refill request + + else + begin + traceTiny("mkInstCacheBlocking", "hitMiss","m"); + if ( statsEn ) + numMisses <= numMisses + 1; + if ( statsEn ) + if ( isJust(cacheLineTag) ) + numEvictions <= numEvictions + 1; + + MainMemReq rfReq + = LoadReq { tag : 0, + addr : reqCacheLineAddr }; + + mainMemReqQ.enq(rfReq); + stage <= RefillResp; + end + + endrule + + //----------------------------------------------------------- + // Refill response rule + + rule refillResp ( stage == RefillResp ); + traceTiny("mkInstCacheBlocking", "stage","R"); + traceTiny("mkInstCacheBlocking", "refill",refill); + + // Write the new data into the cache and update the tag + + mainMemRespQ.deq(); + case ( mainMemRespQ.first() ) matches + + tagged LoadResp .ld : + begin + cacheTagRam.upd(reqIndex,Valid(reqTag)); + cacheDataRam.upd(reqIndex,ld.data); + end + + tagged StoreResp .st : + noAction; + + endcase + + stage <= Access; + endrule + + //----------------------------------------------------------- + // Methods + + interface Client mmem_client; + interface Get request = fifoToGet(mainMemReqQ); + interface Put response = fifoToPut(mainMemRespQ); + endinterface + + interface Server proc_server; + interface Put request = tracePut("mkInstCacheBlocking", "reqTiny",toPut(reqQ)); + interface Get response = traceGet("mkInstCacheBlocking", "respTiny",toGet(respQ)); + endinterface + + interface Put statsEn_put = toPut(asReg(statsEn)); + + interface ICacheStats stats; + interface Get num_accesses = toGet(asReg(numAccesses)); + interface Get num_misses = toGet(asReg(numMisses)); + interface Get num_evictions = toGet(asReg(numEvictions)); + endinterface + +endmodule + diff -r 6d1ff93e3afa -r 91a1f76ddd62 core/src/MemArb.bsv --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/core/src/MemArb.bsv Tue Apr 13 17:34:33 2010 -0400 @@ -0,0 +1,141 @@ +// The MIT License + +// Copyright (c) 2009 Massachusetts Institute of Technology + +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: + +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. + +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +// THE SOFTWARE. + +import Connectable::*; +import GetPut::*; +import ClientServer::*; +import FIFOF::*; +import FIFO::*; + +import BFIFO::*; +import MemTypes::*; +import Trace::*; + +interface MemArb; + + interface Server#(MainMemReq,MainMemResp) cache0_server; + interface Server#(MainMemReq,MainMemResp) cache1_server; + interface Client#(MainMemReq,MainMemResp) mmem_client; + +endinterface + +typedef enum { REQ0, REQ1 } ReqPtr deriving(Eq,Bits); + +(* synthesize *) +module mkMemArb( MemArb ); + + //----------------------------------------------------------- + // State + + FIFOF#(MainMemReq) req0Q <- mkFIFOF1(); + FIFO#(MainMemResp) resp0Q <- mkFIFO1(); + + FIFOF#(MainMemReq) req1Q <- mkFIFOF1(); + FIFO#(MainMemResp) resp1Q <- mkFIFO1(); + + FIFO#(MainMemReq) mreqQ <- mkFIFO1(); + FIFO#(MainMemResp) mrespQ <- mkFIFO1(); + + Reg#(ReqPtr) nextReq <- mkReg(REQ0); + + //----------------------------------------------------------- + // Some wires + + let req0avail = req0Q.notEmpty(); + let req1avail = req1Q.notEmpty(); + + //----------------------------------------------------------- + // Rules + + rule chooseReq0 ( req0avail && (!req1avail || (nextReq == REQ0)) ); + traceTiny("mkMemArb", "memArb req0",req0Q.first()); + + // Rewrite tag field if this is a load ... + MainMemReq mreq + = case ( req0Q.first() ) matches + tagged LoadReq .ld : return LoadReq { tag:0, addr:ld.addr }; + tagged StoreReq .st : return req0Q.first(); + endcase; + + // Send out the request + mreqQ.enq(mreq); + nextReq <= REQ1; + req0Q.deq(); + + endrule + + rule chooseReq1 ( req1avail && (!req0avail || (nextReq == REQ1)) ); + traceTiny("mkMemArb", "memArb req1",req1Q.first); + + // Rewrite tag field if this is a load ... + MainMemReq mreq + = case ( req1Q.first() ) matches + tagged LoadReq .ld : return LoadReq { tag:1, addr:ld.addr }; + tagged StoreReq .st : return req1Q.first(); + endcase; + + // Send out the request + mreqQ.enq(mreq); + nextReq <= REQ0; + req1Q.deq(); + + endrule + + rule returnResp; + traceTiny("mkMemArb", "resp",mrespQ.first()); + + // Use tag to figure out where to send response + mrespQ.deq(); + let tag + = case ( mrespQ.first() ) matches + tagged LoadResp .ld : return ld.tag; + tagged StoreResp .st : return st.tag; + endcase; + + if ( tag == 0 ) + resp0Q.enq(mrespQ.first()); + else + resp1Q.enq(mrespQ.first()); + + endrule + + //----------------------------------------------------------- + // Methods + + interface Server cache0_server; + interface Put request = toPut(req0Q); + interface Get response = toGet(resp0Q); + endinterface + + interface Server cache1_server; + interface Put request = toPut(req1Q); + interface Get response = toGet(resp1Q); + endinterface + + interface Client mmem_client; + interface Get request = toGet(mreqQ); + interface Put response = toPut(mrespQ); + endinterface + +endmodule + + diff -r 6d1ff93e3afa -r 91a1f76ddd62 core/src/MemTypes.bsv --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/core/src/MemTypes.bsv Tue Apr 13 17:34:33 2010 -0400 @@ -0,0 +1,93 @@ + +import Trace::*; + +//---------------------------------------------------------------------- +// Basic memory requests and responses +//---------------------------------------------------------------------- + +typedef union tagged +{ + struct { Bit#(addrSz) addr; Bit#(tagSz) tag; } LoadReq; + struct { Bit#(addrSz) addr; Bit#(tagSz) tag; Bit#(dataSz) data; } StoreReq; +} +MemReq#( type addrSz, type tagSz, type dataSz ) +deriving(Eq,Bits); + +typedef union tagged +{ + struct { Bit#(tagSz) tag; Bit#(dataSz) data; } LoadResp; + struct { Bit#(tagSz) tag; } StoreResp; +} +MemResp#( type tagSz, type dataSz ) +deriving(Eq,Bits); + +//---------------------------------------------------------------------- +// Specialized req/resp for inst/data/host +//---------------------------------------------------------------------- + +typedef 32 AddrSz; +typedef 08 TagSz; +typedef 32 DataSz; +typedef 32 InstSz; +typedef 32 HostDataSz; + +typedef MemReq#(AddrSz,TagSz,0) InstReq; +typedef MemResp#(TagSz,InstSz) InstResp; + +typedef MemReq#(AddrSz,TagSz,DataSz) DataReq; +typedef MemResp#(TagSz,DataSz) DataResp; + +typedef MemReq#(AddrSz,TagSz,HostDataSz) HostReq; +typedef MemResp#(TagSz,HostDataSz) HostResp; + +//---------------------------------------------------------------------- +// Specialized req/resp for main memory +//---------------------------------------------------------------------- + +typedef 32 MainMemAddrSz; +typedef 08 MainMemTagSz; +typedef 32 MainMemDataSz; + +typedef MemReq#(MainMemAddrSz,MainMemTagSz,MainMemDataSz) MainMemReq; +typedef MemResp#(MainMemTagSz,MainMemDataSz) MainMemResp; + +//---------------------------------------------------------------------- +// Tracing Functions +//---------------------------------------------------------------------- + +instance Traceable#(MemReq#(a,b,c)); + + function Action traceTiny( String loc, String ttag, MemReq#(a,b,c) req ); + case ( req ) matches + tagged LoadReq .ld : $fdisplay(stderr, " => %s:%s l%2x", loc, ttag, ld.tag ); + tagged StoreReq .st : $fdisplay(stderr, " => %s:%s s%2x", loc, ttag, st.tag ); + endcase + endfunction + + function Action traceFull( String loc, String ttag, MemReq#(a,b,c) req ); + case ( req ) matches + tagged LoadReq .ld : $fdisplay(stderr, " => %s:%s Ld { addr=%x, tag=%x }", loc, ttag, ld.addr, ld.tag ); + tagged StoreReq .st : $fdisplay(stderr, " => %s:%s St { addr=%x, tag=%x, data=%x }", loc, ttag, st.addr, st.tag, st.data ); + endcase + endfunction + +endinstance + +instance Traceable#(MemResp#(a,b)); + + function Action traceTiny( String loc, String ttag, MemResp#(a,b) resp ); + case ( resp ) matches + tagged LoadResp .ld : $fdisplay(stderr, " => %s:%s l%2x", loc, ttag, ld.tag ); + tagged StoreResp .st : $fdisplay(stderr, " => %s:%s s%2x", loc, ttag, st.tag ); + endcase + endfunction + + function Action traceFull( String loc, String ttag, MemResp#(a,b) resp ); + case ( resp ) matches + tagged LoadResp .ld : $fdisplay(stderr, " => %s:%s Ld { tag=%x, data=%x }", loc, ttag, ld.tag, ld.data ); + tagged StoreResp .st : $fdisplay(stderr, " => %s:%s St { tag=%x }", loc, ttag, st.tag ); + endcase + endfunction + +endinstance + diff -r 6d1ff93e3afa -r 91a1f76ddd62 core/src/PathTypes.bsv --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/core/src/PathTypes.bsv Tue Apr 13 17:34:33 2010 -0400 @@ -0,0 +1,31 @@ +import Trace::*; +import Vector::*; + +`define MAX_VOICES 4 +`define MAX_CORES 16 +`define MAX_PATH_IDS 18 +`define MAX_PATH_LENGTH 8 + +// The path is hardwired and so should never be stored in a register. Therefore int type rather than Bit type + +typedef Bit#(32) MemAddr; +typedef Int#(TLog#(`MAX_PATH_IDS)) PathId; + +//The mixer is identified as PathId 0, path end is max +PathId mixerId = 0; +PathId endId = `MAX_CORES+1; + +// Path is array of path ids +typedef Vector#(`MAX_PATH_LENGTH, PathId) CorePath; +typedef struct +{ + MemAddr startAddr; + CorePath route; + } FullPath deriving(Eq, Bits); + +vector#(`MAX_VOICES, FullPath) routeTable; +CorePath aroute = {1, 2}; +routeTable = {{12, aroute},{1, aroute}}; + + + diff -r 6d1ff93e3afa -r 91a1f76ddd62 core/src/ProcTypes.bsv --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/core/src/ProcTypes.bsv Tue Apr 13 17:34:33 2010 -0400 @@ -0,0 +1,375 @@ + +import Trace::*; + +//---------------------------------------------------------------------- +// Other typedefs +//---------------------------------------------------------------------- + +typedef Bit#(32) Addr; +typedef Int#(18) Stat; + +//---------------------------------------------------------------------- +// Basic instruction type +//---------------------------------------------------------------------- + +typedef Bit#(5) Rindx; +typedef Bit#(16) Simm; +typedef Bit#(16) Zimm; +typedef Bit#(8) Epoch; +typedef Bit#(5) Shamt; +typedef Bit#(26) Target; +typedef Bit#(5) CP0indx; +typedef Bit#(32) Data; + +typedef enum +{ + Taken, + NotTaken +} + Direction + deriving(Bits,Eq); + + +//---------------------------------------------------------------------- +// Pipeline typedefs +//---------------------------------------------------------------------- + +typedef union tagged +{ + Tuple2#(Rindx,Data) ALUWB; + Rindx MemWB; + Tuple2#(Rindx,Data) CoWB; +} + WritebackType + deriving(Bits,Eq); + +//////////////////////// +// I Add Writeback queue type +//////////// +typedef union tagged +{ + struct {Bit#(32) data; Rindx dest; } WB_ALU; + Bit#(32) WB_Host; + Rindx WB_Load; + void WB_Store; +} +WBResult deriving(Eq, Bits); + +typedef struct{Addr qpc; Addr qnxtpc; Epoch qepoch;} PCStat deriving(Eq, Bits); +//typedef struct{Addr qpc; Epoch qepoch;} PCStat deriving(Eq, Bits); + +typedef union tagged +{ + + struct { Rindx rbase; Rindx rdst; Simm offset; } LW; + struct { Rindx rbase; Rindx rsrc; Simm offset; } SW; + + struct { Rindx rsrc; Rindx rdst; Simm imm; } ADDIU; + struct { Rindx rsrc; Rindx rdst; Simm imm; } SLTI; + struct { Rindx rsrc; Rindx rdst; Simm imm; } SLTIU; + struct { Rindx rsrc; Rindx rdst; Zimm imm; } ANDI; + struct { Rindx rsrc; Rindx rdst; Zimm imm; } ORI; + struct { Rindx rsrc; Rindx rdst; Zimm imm; } XORI; + struct { Rindx rdst; Zimm imm; } LUI; + + struct { Rindx rsrc; Rindx rdst; Shamt shamt; } SLL; + struct { Rindx rsrc; Rindx rdst; Shamt shamt; } SRL; + struct { Rindx rsrc; Rindx rdst; Shamt shamt; } SRA; + struct { Rindx rsrc; Rindx rdst; Rindx rshamt; } SLLV; + struct { Rindx rsrc; Rindx rdst; Rindx rshamt; } SRLV; + struct { Rindx rsrc; Rindx rdst; Rindx rshamt; } SRAV; + struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } ADDU; + struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } SUBU; + struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } AND; + struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } OR; + struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } XOR; + struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } NOR; + struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } SLT; + struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } SLTU; + + struct { Target target; } J; + struct { Target target; } JAL; + struct { Rindx rsrc; } JR; + struct { Rindx rsrc; Rindx rdst; } JALR; + struct { Rindx rsrc1; Rindx rsrc2; Simm offset; } BEQ; + struct { Rindx rsrc1; Rindx rsrc2; Simm offset; } BNE; + struct { Rindx rsrc; Simm offset; } BLEZ; + struct { Rindx rsrc; Simm offset; } BGTZ; + struct { Rindx rsrc; Simm offset; } BLTZ; + struct { Rindx rsrc; Simm offset; } BGEZ; + + struct { Rindx rdst; CP0indx cop0src; } MFC0; + struct { Rindx rsrc; CP0indx cop0dst; } MTC0; + + void ILLEGAL; + +} +Instr deriving(Eq); + +//---------------------------------------------------------------------- +// Pack and Unpack +//---------------------------------------------------------------------- + +Bit#(6) opFUNC = 6'b000000; Bit#(6) fcSLL = 6'b000000; +Bit#(6) opRT = 6'b000001; Bit#(6) fcSRL = 6'b000010; +Bit#(6) opRS = 6'b010000; Bit#(6) fcSRA = 6'b000011; + Bit#(6) fcSLLV = 6'b000100; +Bit#(6) opLW = 6'b100011; Bit#(6) fcSRLV = 6'b000110; +Bit#(6) opSW = 6'b101011; Bit#(6) fcSRAV = 6'b000111; + Bit#(6) fcADDU = 6'b100001; +Bit#(6) opADDIU = 6'b001001; Bit#(6) fcSUBU = 6'b100011; +Bit#(6) opSLTI = 6'b001010; Bit#(6) fcAND = 6'b100100; +Bit#(6) opSLTIU = 6'b001011; Bit#(6) fcOR = 6'b100101; +Bit#(6) opANDI = 6'b001100; Bit#(6) fcXOR = 6'b100110; +Bit#(6) opORI = 6'b001101; Bit#(6) fcNOR = 6'b100111; +Bit#(6) opXORI = 6'b001110; Bit#(6) fcSLT = 6'b101010; +Bit#(6) opLUI = 6'b001111; Bit#(6) fcSLTU = 6'b101011; + +Bit#(6) opJ = 6'b000010; +Bit#(6) opJAL = 6'b000011; +Bit#(6) fcJR = 6'b001000; +Bit#(6) fcJALR = 6'b001001; +Bit#(6) opBEQ = 6'b000100; +Bit#(6) opBNE = 6'b000101; +Bit#(6) opBLEZ = 6'b000110; +Bit#(6) opBGTZ = 6'b000111; +Bit#(5) rtBLTZ = 5'b00000; +Bit#(5) rtBGEZ = 5'b00001; + +Bit#(5) rsMFC0 = 5'b00000; +Bit#(5) rsMTC0 = 5'b00100; + +instance Bits#(Instr,32); + + // Pack Function + + function Bit#(32) pack( Instr instr ); + + case ( instr ) matches + + tagged LW .it : return { opLW, it.rbase, it.rdst, it.offset }; + tagged SW .it : return { opSW, it.rbase, it.rsrc, it.offset }; + + tagged ADDIU .it : return { opADDIU, it.rsrc, it.rdst, it.imm }; + tagged SLTI .it : return { opSLTI, it.rsrc, it.rdst, it.imm }; + tagged SLTIU .it : return { opSLTIU, it.rsrc, it.rdst, it.imm }; + tagged ANDI .it : return { opANDI, it.rsrc, it.rdst, it.imm }; + tagged ORI .it : return { opORI, it.rsrc, it.rdst, it.imm }; + tagged XORI .it : return { opXORI, it.rsrc, it.rdst, it.imm }; + tagged LUI .it : return { opLUI, 5'b0, it.rdst, it.imm }; + + tagged SLL .it : return { opFUNC, 5'b0, it.rsrc, it.rdst, it.shamt, fcSLL }; + tagged SRL .it : return { opFUNC, 5'b0, it.rsrc, it.rdst, it.shamt, fcSRL }; + tagged SRA .it : return { opFUNC, 5'b0, it.rsrc, it.rdst, it.shamt, fcSRA }; + + tagged SLLV .it : return { opFUNC, it.rshamt, it.rsrc, it.rdst, 5'b0, fcSLLV }; + tagged SRLV .it : return { opFUNC, it.rshamt, it.rsrc, it.rdst, 5'b0, fcSRLV }; + tagged SRAV .it : return { opFUNC, it.rshamt, it.rsrc, it.rdst, 5'b0, fcSRAV }; + + tagged ADDU .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcADDU }; + tagged SUBU .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcSUBU }; + tagged AND .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcAND }; + tagged OR .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcOR }; + tagged XOR .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcXOR }; + tagged NOR .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcNOR }; + tagged SLT .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcSLT }; + tagged SLTU .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcSLTU }; + + tagged J .it : return { opJ, it.target }; + tagged JAL .it : return { opJAL, it.target }; + tagged JR .it : return { opFUNC, it.rsrc, 5'b0, 5'b0, 5'b0, fcJR }; + tagged JALR .it : return { opFUNC, it.rsrc, 5'b0, it.rdst, 5'b0, fcJALR }; + tagged BEQ .it : return { opBEQ, it.rsrc1, it.rsrc2, it.offset }; + tagged BNE .it : return { opBNE, it.rsrc1, it.rsrc2, it.offset }; + tagged BLEZ .it : return { opBLEZ, it.rsrc, 5'b0, it.offset }; + tagged BGTZ .it : return { opBGTZ, it.rsrc, 5'b0, it.offset }; + tagged BLTZ .it : return { opRT, it.rsrc, rtBLTZ, it.offset }; + tagged BGEZ .it : return { opRT, it.rsrc, rtBGEZ, it.offset }; + + tagged MFC0 .it : return { opRS, rsMFC0, it.rdst, it.cop0src, 11'b0 }; + tagged MTC0 .it : return { opRS, rsMTC0, it.rsrc, it.cop0dst, 11'b0 }; + + endcase + + endfunction + + // Unpack Function + + function Instr unpack( Bit#(32) instrBits ); + + let opcode = instrBits[ 31 : 26 ]; + let rs = instrBits[ 25 : 21 ]; + let rt = instrBits[ 20 : 16 ]; + let rd = instrBits[ 15 : 11 ]; + let shamt = instrBits[ 10 : 6 ]; + let funct = instrBits[ 5 : 0 ]; + let imm = instrBits[ 15 : 0 ]; + let target = instrBits[ 25 : 0 ]; + + case ( opcode ) + + opLW : return LW { rbase:rs, rdst:rt, offset:imm }; + opSW : return SW { rbase:rs, rsrc:rt, offset:imm }; + opADDIU : return ADDIU { rsrc:rs, rdst:rt, imm:imm }; + opSLTI : return SLTI { rsrc:rs, rdst:rt, imm:imm }; + opSLTIU : return SLTIU { rsrc:rs, rdst:rt, imm:imm }; + opANDI : return ANDI { rsrc:rs, rdst:rt, imm:imm }; + opORI : return ORI { rsrc:rs, rdst:rt, imm:imm }; + opXORI : return XORI { rsrc:rs, rdst:rt, imm:imm }; + opLUI : return LUI { rdst:rt, imm:imm }; + opJ : return J { target:target }; + opJAL : return JAL { target:target }; + opBEQ : return BEQ { rsrc1:rs, rsrc2:rt, offset:imm }; + opBNE : return BNE { rsrc1:rs, rsrc2:rt, offset:imm }; + opBLEZ : return BLEZ { rsrc:rs, offset:imm }; + opBGTZ : return BGTZ { rsrc:rs, offset:imm }; + + opFUNC : + case ( funct ) + fcSLL : return SLL { rsrc:rt, rdst:rd, shamt:shamt }; + fcSRL : return SRL { rsrc:rt, rdst:rd, shamt:shamt }; + fcSRA : return SRA { rsrc:rt, rdst:rd, shamt:shamt }; + fcSLLV : return SLLV { rsrc:rt, rdst:rd, rshamt:rs }; + fcSRLV : return SRLV { rsrc:rt, rdst:rd, rshamt:rs }; + fcSRAV : return SRAV { rsrc:rt, rdst:rd, rshamt:rs }; + fcADDU : return ADDU { rsrc1:rs, rsrc2:rt, rdst:rd }; + fcSUBU : return SUBU { rsrc1:rs, rsrc2:rt, rdst:rd }; + fcAND : return AND { rsrc1:rs, rsrc2:rt, rdst:rd }; + fcOR : return OR { rsrc1:rs, rsrc2:rt, rdst:rd }; + fcXOR : return XOR { rsrc1:rs, rsrc2:rt, rdst:rd }; + fcNOR : return NOR { rsrc1:rs, rsrc2:rt, rdst:rd }; + fcSLT : return SLT { rsrc1:rs, rsrc2:rt, rdst:rd }; + fcSLTU : return SLTU { rsrc1:rs, rsrc2:rt, rdst:rd }; + fcJR : return JR { rsrc:rs }; + fcJALR : return JALR { rsrc:rs, rdst:rd }; + default : return ILLEGAL; + endcase + + opRT : + case ( rt ) + rtBLTZ : return BLTZ { rsrc:rs, offset:imm }; + rtBGEZ : return BGEZ { rsrc:rs, offset:imm }; + default : return ILLEGAL; + endcase + + opRS : + case ( rs ) + rsMFC0 : return MFC0 { rdst:rt, cop0src:rd }; + rsMTC0 : return MTC0 { rsrc:rt, cop0dst:rd }; + default : return ILLEGAL; + endcase + + default : return ILLEGAL; + + endcase + + endfunction + +endinstance + +//---------------------------------------------------------------------- +// Trace +//---------------------------------------------------------------------- + +instance Traceable#(Instr); + + function Action traceTiny( String loc, String ttag, Instr inst ); + case ( inst ) matches + + tagged LW .it : $fdisplay(stderr, " => %s:%s lw", loc, ttag ); + tagged SW .it : $fdisplay(stderr, " => %s:%s sw", loc, ttag ); + + tagged ADDIU .it : $fdisplay(stderr, " => %s:%s addi", loc, ttag ); + tagged SLTI .it : $fdisplay(stderr, " => %s:%s sli", loc, ttag ); + tagged SLTIU .it : $fdisplay(stderr, " => %s:%s sliu", loc, ttag ); + tagged ANDI .it : $fdisplay(stderr, " => %s:%s andi", loc, ttag ); + tagged ORI .it : $fdisplay(stderr, " => %s:%s ori", loc, ttag ); + tagged XORI .it : $fdisplay(stderr, " => %s:%s xori", loc, ttag ); + tagged LUI .it : $fdisplay(stderr, " => %s:%s lui", loc, ttag ); + + tagged SLL .it : $fdisplay(stderr, " => %s:%s sll", loc, ttag ); + tagged SRL .it : $fdisplay(stderr, " => %s:%s srl", loc, ttag ); + tagged SRA .it : $fdisplay(stderr, " => %s:%s sra", loc, ttag ); + tagged SLLV .it : $fdisplay(stderr, " => %s:%s sllv", loc, ttag ); + tagged SRLV .it : $fdisplay(stderr, " => %s:%s srlv", loc, ttag ); + tagged SRAV .it : $fdisplay(stderr, " => %s:%s srav", loc, ttag ); + + tagged ADDU .it : $fdisplay(stderr, " => %s:%s addu", loc, ttag ); + tagged SUBU .it : $fdisplay(stderr, " => %s:%s subu", loc, ttag ); + tagged AND .it : $fdisplay(stderr, " => %s:%s and", loc, ttag ); + tagged OR .it : $fdisplay(stderr, " => %s:%s or", loc, ttag ); + tagged XOR .it : $fdisplay(stderr, " => %s:%s xor", loc, ttag ); + tagged NOR .it : $fdisplay(stderr, " => %s:%s nor", loc, ttag ); + tagged SLT .it : $fdisplay(stderr, " => %s:%s slt", loc, ttag ); + tagged SLTU .it : $fdisplay(stderr, " => %s:%s sltu", loc, ttag ); + + tagged J .it : $fdisplay(stderr, " => %s:%s j", loc, ttag ); + tagged JAL .it : $fdisplay(stderr, " => %s:%s jal", loc, ttag ); + tagged JR .it : $fdisplay(stderr, " => %s:%s jr", loc, ttag ); + tagged JALR .it : $fdisplay(stderr, " => %s:%s jalr", loc, ttag ); + tagged BEQ .it : $fdisplay(stderr, " => %s:%s beq", loc, ttag ); + tagged BNE .it : $fdisplay(stderr, " => %s:%s bne", loc, ttag ); + tagged BLEZ .it : $fdisplay(stderr, " => %s:%s blez", loc, ttag ); + tagged BGTZ .it : $fdisplay(stderr, " => %s:%s bgtz", loc, ttag ); + tagged BLTZ .it : $fdisplay(stderr, " => %s:%s bltz", loc, ttag ); + tagged BGEZ .it : $fdisplay(stderr, " => %s:%s bgez", loc, ttag ); + + tagged MFC0 .it : $fdisplay(stderr, " => %s:%s mfc0", loc, ttag ); + tagged MTC0 .it : $fdisplay(stderr, " => %s:%s mtc0", loc, ttag ); + + tagged ILLEGAL : $fdisplay(stderr, " => %s:%s ill", loc, ttag ); + + endcase + endfunction + + function Action traceFull( String loc, String ttag, Instr inst ); + case ( inst ) matches + + tagged LW .it : $fdisplay(stderr, " => %s:%s lw r%0d, 0x%x(r%0d)", loc, ttag, it.rdst, it.offset, it.rbase ); + tagged SW .it : $fdisplay(stderr, " => %s:%s sw r%0d, 0x%x(r%0d)", loc, ttag, it.rsrc, it.offset, it.rbase ); + + tagged ADDIU .it : $fdisplay(stderr, " => %s:%s addiu r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); + tagged SLTI .it : $fdisplay(stderr, " => %s:%s slti r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); + tagged SLTIU .it : $fdisplay(stderr, " => %s:%s sltiu r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); + tagged ANDI .it : $fdisplay(stderr, " => %s:%s andi r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); + tagged ORI .it : $fdisplay(stderr, " => %s:%s ori r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); + tagged XORI .it : $fdisplay(stderr, " => %s:%s xori r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); + tagged LUI .it : $fdisplay(stderr, " => %s:%s lui r%0d, 0x%x", loc, ttag, it.rdst, it.imm ); + + tagged SLL .it : $fdisplay(stderr, " => %s:%s sll r%0d, r%0d, %0d", loc, ttag, it.rdst, it.rsrc, it.shamt ); + tagged SRL .it : $fdisplay(stderr, " => %s:%s srl r%0d, r%0d, %0d", loc, ttag, it.rdst, it.rsrc, it.shamt ); + tagged SRA .it : $fdisplay(stderr, " => %s:%s sra r%0d, r%0d, %0d", loc, ttag, it.rdst, it.rsrc, it.shamt ); + tagged SLLV .it : $fdisplay(stderr, " => %s:%s sllv r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc, it.rshamt ); + tagged SRLV .it : $fdisplay(stderr, " => %s:%s srlv r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc, it.rshamt ); + tagged SRAV .it : $fdisplay(stderr, " => %s:%s srav r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc, it.rshamt ); + + tagged ADDU .it : $fdisplay(stderr, " => %s:%s addu r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); + tagged SUBU .it : $fdisplay(stderr, " => %s:%s subu r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); + tagged AND .it : $fdisplay(stderr, " => %s:%s and r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); + tagged OR .it : $fdisplay(stderr, " => %s:%s or r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); + tagged XOR .it : $fdisplay(stderr, " => %s:%s xor r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); + tagged NOR .it : $fdisplay(stderr, " => %s:%s nor r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); + tagged SLT .it : $fdisplay(stderr, " => %s:%s slt r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); + tagged SLTU .it : $fdisplay(stderr, " => %s:%s sltu r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); + + tagged J .it : $fdisplay(stderr, " => %s:%s j 0x%x", loc, ttag, it.target ); + tagged JAL .it : $fdisplay(stderr, " => %s:%s jal 0x%x", loc, ttag, it.target ); + tagged JR .it : $fdisplay(stderr, " => %s:%s jr r%0d", loc, ttag, it.rsrc ); + tagged JALR .it : $fdisplay(stderr, " => %s:%s jalr r%0d", loc, ttag, it.rsrc ); + tagged BEQ .it : $fdisplay(stderr, " => %s:%s beq r%0d, r%0d, 0x%x", loc, ttag, it.rsrc1, it.rsrc2, it.offset ); + tagged BNE .it : $fdisplay(stderr, " => %s:%s bne r%0d, r%0d, 0x%x", loc, ttag, it.rsrc1, it.rsrc2, it.offset ); + tagged BLEZ .it : $fdisplay(stderr, " => %s:%s blez r%0d, 0x%x", loc, ttag, it.rsrc, it.offset ); + tagged BGTZ .it : $fdisplay(stderr, " => %s:%s bgtz r%0d, 0x%x", loc, ttag, it.rsrc, it.offset ); + tagged BLTZ .it : $fdisplay(stderr, " => %s:%s bltz r%0d, 0x%x", loc, ttag, it.rsrc, it.offset ); + tagged BGEZ .it : $fdisplay(stderr, " => %s:%s bgez r%0d, 0x%x", loc, ttag, it.rsrc, it.offset ); + + tagged MFC0 .it : $fdisplay(stderr, " => %s:%s mfc0 r%0d, cpr%0d", loc, ttag, it.rdst, it.cop0src ); + tagged MTC0 .it : $fdisplay(stderr, " => %s:%s mtc0 r%0d, cpr%0d", loc, ttag, it.rsrc, it.cop0dst ); + + tagged ILLEGAL : $fdisplay(stderr, " => %s:%s illegal instruction", loc, ttag ); + + endcase + endfunction + +endinstance + diff -r 6d1ff93e3afa -r 91a1f76ddd62 core/src/Processor.bsv --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/core/src/Processor.bsv Tue Apr 13 17:34:33 2010 -0400 @@ -0,0 +1,559 @@ +/// The MIT License + +// Copyright (c) 2009 Massachusetts Institute of Technology + +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: + +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. + +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +// THE SOFTWARE. + +import Connectable::*; +import GetPut::*; +import ClientServer::*; +import RegFile::*; +import BRegFile::*; +import FIFO::*; +import FIFOF::*; +import SFIFO::*; +import RWire::*; + +import BFIFO::*; +import MemTypes::*; +import ProcTypes::*; +import BranchPred::*; +import PathTypes::*; + +import Trace::*; + +interface ProcStats; + interface Get#(Stat) num_cycles; + interface Get#(Stat) num_inst; +endinterface + +interface CPUToHost; + method Bit#(32) cpuToHost(int req); +endinterface + +interface Proc; + + // Interface from processor to caches + interface Client#(DataReq,DataResp) dmem_client; + interface Client#(InstReq,InstResp) imem_client; + + // Interface for enabling/disabling statistics on the rest of the core + interface Get#(Bool) statsEn_get; + + // Interface for collecting statistics. + interface ProcStats stats; + + // Interface to host + interface CPUToHost tohost; + +endinterface + + +typedef enum { PCgen, Exec, Writeback } Stage deriving(Eq,Bits); + +//----------------------------------------------------------- +// Register file module +//----------------------------------------------------------- + +interface BRFile; + method Action wr( Rindx rindx, Bit#(32) data ); + method Bit#(32) rd1( Rindx rindx ); + method Bit#(32) rd2( Rindx rindx ); +endinterface + +module mkBRFile( BRFile ); + + RegFile#(Rindx,Bit#(32)) rfile <- mkBRegFile(); + + method Action wr( Rindx rindx, Bit#(32) data ); + rfile.upd( rindx, data ); + endmethod + + method Bit#(32) rd1( Rindx rindx ); + return ( rindx == 0 ) ? 0 : rfile.sub(rindx); + endmethod + + method Bit#(32) rd2( Rindx rindx ); + return ( rindx == 0 ) ? 0 : rfile.sub(rindx); + endmethod + +endmodule + +//----------------------------------------------------------- +// Helper functions +//----------------------------------------------------------- + +function Bit#(32) slt( Bit#(32) val1, Bit#(32) val2 ); + return zeroExtend( pack( signedLT(val1,val2) ) ); +endfunction + +function Bit#(32) sltu( Bit#(32) val1, Bit#(32) val2 ); + return zeroExtend( pack( val1 < val2 ) ); +endfunction + +function Bit#(32) rshft( Bit#(32) val ); + return zeroExtend(val[4:0]); +endfunction + + +//----------------------------------------------------------- +// Find funct for wbQ +//----------------------------------------------------------- +function Bool findwbf(Rindx fVal, WBResult cmpVal); + case (cmpVal) matches + tagged WB_ALU {data:.res, dest:.rd} : + return (fVal == rd); + tagged WB_Load .rd : + return (fVal == rd); + tagged WB_Store .st : + return False; + tagged WB_Host .x : + return False; + endcase +endfunction + + +//----------------------------------------------------------- +// Stall funct for wbQ +//----------------------------------------------------------- +function Bool stall(Instr inst, SFIFO#(WBResult, Rindx) f); + case (inst) matches + // -- Memory Ops ------------------------------------------------ + tagged LW .it : + return f.find(it.rbase); + tagged SW {rsrc:.dreg, rbase:.addr, offset:.o} : + return (f.find(addr) || f.find2(dreg)); + + // -- Simple Ops ------------------------------------------------ + tagged ADDIU .it : return f.find(it.rsrc); + tagged SLTI .it : return f.find(it.rsrc); + tagged SLTIU .it : return f.find(it.rsrc); + tagged ANDI .it : return f.find(it.rsrc); + tagged ORI .it : return f.find(it.rsrc); + tagged XORI .it : return f.find(it.rsrc); + + tagged LUI .it : return f.find(it.rdst); //this rds/wrs itself + tagged SLL .it : return f.find(it.rsrc); + tagged SRL .it : return f.find(it.rsrc); + tagged SRA .it : return f.find(it.rsrc); + tagged SLLV .it : return (f.find(it.rsrc) || f.find(it.rshamt)); + tagged SRLV .it : return (f.find(it.rsrc) || f.find(it.rshamt)); + tagged SRAV .it : return (f.find(it.rsrc) || f.find(it.rshamt)); + tagged ADDU .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); + tagged SUBU .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); + tagged AND .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); + tagged OR .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); + tagged XOR .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); + tagged NOR .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); + tagged SLT .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); + tagged SLTU .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); + + + // -- Branches -------------------------------------------------- + + tagged BLEZ .it : return (f.find(it.rsrc)); + tagged BGTZ .it : return (f.find(it.rsrc)); + tagged BLTZ .it : return (f.find(it.rsrc)); + tagged BGEZ .it : return (f.find(it.rsrc)); + tagged BEQ .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); + tagged BNE .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); + + // -- Jumps ----------------------------------------------------- + + tagged J .it : return False; + tagged JR .it : return f.find(it.rsrc); + tagged JALR .it : return f.find(it.rsrc); + tagged JAL .it : return False; + + // -- Cop0 ------------------------------------------------------ + + tagged MTC0 .it : return f.find(it.rsrc); + tagged MFC0 .it : return False; + + // -- Illegal --------------------------------------------------- + + default : return False; + + endcase +endfunction +//----------------------------------------------------------- +// Reference processor +//----------------------------------------------------------- + + +(* doc = "synthesis attribute ram_style mkProc distributed;" *) +(* synthesize *) +module mkProc( Proc ); + + //----------------------------------------------------------- + // State + + // Standard processor state + + Reg#(Addr) pc <- mkReg(32'h00001000); + Reg#(Epoch) epoch <- mkReg(0); + Reg#(Stage) stage <- mkReg(PCgen); + BRFile rf <- mkBRFile; + + // Branch Prediction + BranchPred bp <- mkBranchPred(); + FIFO#(PCStat) execpc <- mkLFIFO(); + + // Pipelines + FIFO#(PCStat) pcQ <-mkSizedFIFO(3); + SFIFO#(WBResult, Rindx) wbQ <-mkSFIFO(findwbf); + + Reg#(Bit#(32)) cp0_tohost <- mkReg(0); + Reg#(Bit#(32)) cp0_fromhost <- mkReg(0); + Reg#(Bool) cp0_statsEn <- mkReg(False); + + // Memory request/response state + + FIFO#(InstReq) instReqQ <- mkBFIFO1(); + FIFO#(InstResp) instRespQ <- mkFIFO(); + + FIFO#(DataReq) dataReqQ <- mkBFIFO1(); + FIFO#(DataResp) dataRespQ <- mkFIFO(); + + // Statistics state + Reg#(Stat) num_cycles <- mkReg(0); + Reg#(Stat) num_inst <- mkReg(0); + + //----------------------------------------------------------- + // Rules + + (* descending_urgency = "exec, pcgen" *) + rule pcgen; //( stage == PCgen ); + let pc_plus4 = pc + 4; + + traceTiny("mkProc", "pc",pc); + traceTiny("mkProc", "pcgen","P"); + instReqQ.enq( LoadReq{ addr:pc, tag:epoch} ); + + let next_pc = bp.get(pc); + if (next_pc matches tagged Valid .npc) + begin + pcQ.enq(PCStat {qpc:pc, qnxtpc:npc, qepoch:epoch}); + pc <= npc; + end + else + begin + pcQ.enq(PCStat {qpc:pc, qnxtpc:pc_plus4, qepoch:epoch}); + pc <= pc_plus4; + end + + endrule + + rule discard (instRespQ.first() matches tagged LoadResp .ld + &&& ld.tag != epoch); + traceTiny("mkProc", "stage", "D"); + instRespQ.deq(); + endrule + + (* conflict_free = "exec, writeback" *) + rule exec (instRespQ.first() matches tagged LoadResp.ld + &&& (ld.tag == epoch) + &&& unpack(ld.data) matches .inst + &&& !stall(inst, wbQ)); + + // Some abbreviations + let sext = signExtend; + let zext = zeroExtend; + let sra = signedShiftRight; + + // Get the instruction + + instRespQ.deq(); + Instr inst + = case ( instRespQ.first() ) matches + tagged LoadResp .ld : return unpack(ld.data); + tagged StoreResp .st : return ?; + endcase; + + // Get the PC info + let instrpc = pcQ.first().qpc; + let pc_plus4 = instrpc + 4; + + Bool branchTaken = False; + Addr newPC = pc_plus4; + + // Tracing + traceTiny("mkProc", "exec","X"); + traceTiny("mkProc", "exInstTiny",inst); + traceFull("mkProc", "exInstFull",inst); + + case ( inst ) matches + + // -- Memory Ops ------------------------------------------------ + + tagged LW .it : + begin + Addr addr = rf.rd1(it.rbase) + sext(it.offset); + dataReqQ.enq( LoadReq{ addr:addr, tag:zeroExtend(it.rdst) } ); + wbQ.enq(tagged WB_Load it.rdst); + end + + tagged SW .it : + begin + Addr addr = rf.rd1(it.rbase) + sext(it.offset); + dataReqQ.enq( StoreReq{ tag:0, addr:addr, data:rf.rd2(it.rsrc) } ); + wbQ.enq(tagged WB_Store); + end + + // -- Simple Ops ------------------------------------------------ + + tagged ADDIU .it : + begin + Bit#(32) result = rf.rd1(it.rsrc) + sext(it.imm); + wbQ.enq(tagged WB_ALU {data:result, dest:it.rdst}); + end + tagged SLTI .it : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:slt( rf.rd1(it.rsrc), sext(it.imm) )}); + tagged SLTIU .it : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:sltu( rf.rd1(it.rsrc), sext(it.imm) ) }); + tagged ANDI .it : + begin + Bit#(32) zext_it_imm = zext(it.imm); + wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(rf.rd1(it.rsrc) & zext_it_imm)} ); + end + tagged ORI .it : + begin + Bit#(32) zext_it_imm = zext(it.imm); + wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(rf.rd1(it.rsrc) | zext_it_imm)} ); + end + tagged XORI .it : + begin + Bit#(32) zext_it_imm = zext(it.imm); + wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) ^ zext_it_imm )}); + end + tagged LUI .it : + begin + Bit#(32) zext_it_imm = zext(it.imm); + wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(zext_it_imm << 32'd16) }); + end + + tagged SLL .it : + begin + Bit#(32) zext_it_shamt = zext(it.shamt); + wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) << zext_it_shamt )} ); + end + tagged SRL .it : + begin + Bit#(32) zext_it_shamt = zext(it.shamt); + wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) >> zext_it_shamt )}); + end + tagged SRA .it : + begin + Bit#(32) zext_it_shamt = zext(it.shamt); + wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( rf.rd1(it.rsrc), zext_it_shamt )}); + end + tagged SLLV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) << rshft(rf.rd2(it.rshamt)) )}); + tagged SRLV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) >> rshft(rf.rd2(it.rshamt)) )} ); + tagged SRAV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( rf.rd1(it.rsrc), rshft(rf.rd2(it.rshamt)) ) }); + tagged ADDU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) + rf.rd2(it.rsrc2) )} ); + tagged SUBU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) - rf.rd2(it.rsrc2) )} ); + tagged AND .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) & rf.rd2(it.rsrc2) )} ); + tagged OR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) | rf.rd2(it.rsrc2) )} ); + tagged XOR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) ^ rf.rd2(it.rsrc2) )} ); + tagged NOR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(~(rf.rd1(it.rsrc1) | rf.rd2(it.rsrc2)) )} ); + tagged SLT .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:slt( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) }); + tagged SLTU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sltu( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) }); + + // -- Branches -------------------------------------------------- + + tagged BLEZ .it : + if ( signedLE( rf.rd1(it.rsrc), 0 ) ) + begin + newPC = pc_plus4 + (sext(it.offset) << 2); + branchTaken = True; + end + + tagged BGTZ .it : + if ( signedGT( rf.rd1(it.rsrc), 0 ) ) + begin + newPC = pc_plus4 + (sext(it.offset) << 2); + branchTaken = True; + end + + tagged BLTZ .it : + if ( signedLT( rf.rd1(it.rsrc), 0 ) ) + begin + newPC = pc_plus4 + (sext(it.offset) << 2); + branchTaken = True; + end + + tagged BGEZ .it : + if ( signedGE( rf.rd1(it.rsrc), 0 ) ) + begin + newPC = pc_plus4 + (sext(it.offset) << 2); + branchTaken = True; + end + + tagged BEQ .it : + if ( rf.rd1(it.rsrc1) == rf.rd2(it.rsrc2) ) + begin + newPC = pc_plus4 + (sext(it.offset) << 2); + branchTaken = True; + end + + tagged BNE .it : + if ( rf.rd1(it.rsrc1) != rf.rd2(it.rsrc2) ) + begin + newPC = pc_plus4 + (sext(it.offset) << 2); + branchTaken = True; + end + + // -- Jumps ----------------------------------------------------- + + tagged J .it : + begin + newPC = { pc_plus4[31:28], it.target, 2'b0 }; + branchTaken = True; + end + + tagged JR .it : + begin + newPC = rf.rd1(it.rsrc); + branchTaken = True; + end + + tagged JAL .it : + begin + wbQ.enq(tagged WB_ALU {dest:31, data:pc_plus4 }); + newPC = { pc_plus4[31:28], it.target, 2'b0 }; + branchTaken = True; + end + + tagged JALR .it : + begin + wbQ.enq(tagged WB_ALU {dest:it.rdst, data:pc_plus4 }); + newPC = rf.rd1(it.rsrc); + branchTaken = True; + end + + // -- Cop0 ------------------------------------------------------ + + tagged MTC0 .it : + begin + case ( it.cop0dst ) + 5'd10 : cp0_statsEn <= unpack(truncate(rf.rd1(it.rsrc))); + 5'd21 : cp0_tohost <= truncate(rf.rd1(it.rsrc)); + default : + $display( " RTL-ERROR : %m : Illegal MTC0 cop0dst register!" ); + endcase + wbQ.enq(tagged WB_Host 0); //no idea wwhat this actually should be. + end + +//this is host stuff? + tagged MFC0 .it : + begin + case ( it.cop0src ) + // not actually an ALU instruction but don't have the format otherwise + 5'd10 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(cp0_statsEn)) }); + 5'd20 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_fromhost }); + 5'd21 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_tohost }); + default : + $display( " RTL-ERROR : %m : Illegal MFC0 cop0src register!" ); + endcase + end + + // -- Illegal --------------------------------------------------- + + default : + $display( " RTL-ERROR : %m : Illegal instruction !" ); + + endcase + +//evaluate branch prediction + Addr ppc = pcQ.first().qnxtpc; //predicted branch + if (ppc != newPC) //prediction wrong + begin + epoch <= pcQ.first().qepoch + 1; + bp.upd(instrpc, newPC); //update branch predictor + pcQ.clear(); + pc <= newPC; + end + else + pcQ.deq(); + + if ( cp0_statsEn ) + num_inst <= num_inst+1; + + endrule + + rule writeback; // ( stage == Writeback ); + traceTiny("mkProc", "writeback","W"); + + + // get what to do off the writeback queue + wbQ.deq(); + case (wbQ.first()) matches + tagged WB_ALU {data:.res, dest:.rdst} : rf.wr(rdst, res); + tagged WB_Load .regWr : + begin + dataRespQ.deq(); + if (dataRespQ.first() matches tagged LoadResp .ld) + rf.wr(truncate(ld.tag), ld.data); // no need to use Rindx from queue? Duplicate? + end + tagged WB_Store : dataRespQ.deq(); + tagged WB_Host .dat : noAction; + endcase + + endrule + + rule inc_num_cycles; + if ( cp0_statsEn ) + num_cycles <= num_cycles+1; + endrule + + +//----------------------------------------------------------- +// My Adds +//----------------------------------------------------------- + + //----------------------------------------------------------- + // Methods + + interface Client imem_client; + interface Get request = toGet(instReqQ); + interface Put response = toPut(instRespQ); + endinterface + + interface Client dmem_client; + interface Get request = toGet(dataReqQ); + interface Put response = toPut(dataRespQ); + endinterface + + interface Get statsEn_get = toGet(asReg(cp0_statsEn)); + + interface ProcStats stats; + interface Get num_cycles = toGet(asReg(num_cycles)); + interface Get num_inst = toGet(asReg(num_inst)); + endinterface + + interface CPUToHost tohost; + method Bit#(32) cpuToHost(int req); + return (case (req) + 0: cp0_tohost; + 1: pc; + 2: zeroExtend(pack(stage)); + endcase); + endmethod + endinterface + +endmodule + diff -r 6d1ff93e3afa -r 91a1f76ddd62 core/src/SFIFO.bsv --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/core/src/SFIFO.bsv Tue Apr 13 17:34:33 2010 -0400 @@ -0,0 +1,213 @@ + +import FIFO::*; +import ConfigReg::*; +import RWire::*; + +import List::*; +import Monad::*; + +interface SFIFO#(type alpha_T, type search_T); + method Action enq(alpha_T x); + method Action deq(); + method alpha_T first(); + method Action clear(); + method Bool find(search_T x); + method Bool find2(search_T x); + +endinterface + +module mkSFIFO#(function Bool searchfunc(search_T s, alpha_T x)) (SFIFO#(alpha_T, search_T)) + provisos + (Bits#(alpha_T,asz)); + + Reg#(alpha_T) f0 <- mkConfigRegU(); + Reg#(alpha_T) f1 <- mkConfigRegU(); + + Reg#(Bool) vf0 <- mkConfigReg(False); + Reg#(Bool) vf1 <- mkConfigReg(False); + + PulseWire edge1 <- mkPulseWire(); + + method Action enq(alpha_T x) if (!(vf0 && vf1)); + if (edge1 || !vf0)//empty or we're dequeueing + begin + vf0 <= True; //True + vf1 <= False; + f0 <= x; + end + else // !vf1 + begin + vf1 <= True; + f1 <= x; + end + endmethod + + method Action deq() if (vf0); + edge1.send(); + vf0 <= vf1; + f0 <= f1; + vf1 <= False; + endmethod + + method alpha_T first() if(vf0); + return (f0); + endmethod + + method Action clear(); + vf0 <= False; + vf1 <= False; + endmethod + + method Bool find(search_T sv); + Bool nvf0 = edge1 ? False: vf0; + Bool nvf1 = vf1; + + return (nvf0 && searchfunc(sv, f0) || + nvf1 && searchfunc(sv, f1)); + endmethod + + method Bool find2(search_T sv); + Bool nvf0 = edge1 ? False: vf0; + Bool nvf1 = vf1; + + return (nvf0 && searchfunc(sv, f0) || + nvf1 && searchfunc(sv, f1)); + endmethod + +endmodule + +module mkSFIFO1#(function Bool searchfunc(search_T s, alpha_T x)) (SFIFO#(alpha_T, search_T)) + provisos + (Bits#(alpha_T,asz), Eq#(alpha_T)); + + Reg#(alpha_T) f0 <- mkConfigRegU; + + Reg#(Bool) vf0 <- mkConfigReg(False); + + PulseWire edge1 <- mkPulseWire(); + + method Action enq(alpha_T x) if (!vf0); + vf0 <= True; //True + f0 <= x; + endmethod + + method Action deq() if (vf0); + edge1.send(); + vf0 <= False; + endmethod + + method alpha_T first() if(vf0); + return (f0); + endmethod + + method Action clear(); + vf0 <= False; + endmethod + + method Bool find(search_T sv); + Bool nvf0 = edge1 ? False: vf0; + + return (nvf0 && searchfunc(sv, f0)); + endmethod + + method Bool find2(search_T sv); + Bool nvf0 = edge1 ? False: vf0; + return (nvf0 && searchfunc(sv, f0)); + endmethod + +endmodule + +module mkSizedSFIFOInternal#(Integer n, + function Bool searchfunc1(search_T s, alpha_T x), + function Bool searchfunc2(search_T s, alpha_T x)) (SFIFO#(alpha_T, search_T)) + + provisos ( Bits#(alpha_T,alpha_SZ) ); + + List#(Reg#(alpha_T)) registers <- replicateM(n, mkRegU); + List#(Reg#(Bool)) valids <- replicateM(n, mkReg(False)); + + function Nat getNextFree (List#(Reg#(Bool)) vs); + + Nat res = fromInteger(n - 1); + + for (Integer x = n - 1; x > -1; x = x - 1) + res = !vs[x]._read() ? fromInteger(x) : res; + + return res; + + endfunction + + function Bool notFull(); + + Bool full = True; + + for (Integer x = 0; x < n; x = x + 1) + full = full && valids[x]._read(); + + return !full; + + endfunction + + method Action enq( alpha_T item ) if ( notFull() ); + + Nat k = getNextFree(valids); + select(valids, k)._write(True); + select(registers, k)._write(item); + + endmethod + + method Action deq() if ( valids[0]._read() ); + + for (Integer x = 0; x < (n-1); x = x + 1) + begin + + (registers[x]) <= registers[x + 1]._read(); + (valids[x]) <= valids[x + 1]._read(); + + end + (valids[n-1]) <= False; + endmethod + + method alpha_T first() if ( valids[0]._read() ); + return registers[0]._read(); + endmethod + + method Bool find(search_T sv); + Bool res = False; + + for (Integer x = 0; x < n; x = x + 1) + if ( valids[x]._read() && searchfunc1(sv, registers[x]._read()) ) + res = True; + + return res; + + endmethod + + method Bool find2(search_T sv); + Bool res = False; + + for (Integer x = 0; x < n; x = x + 1) + if ( valids[x]._read() && searchfunc2(sv, registers[x]._read()) ) + res = True; + + return res; + + endmethod + + method Action clear(); + + for (Integer x = 0; x < n; x = x + 1) + (valids[x]) <= False; + + endmethod + +endmodule + +module mkSizedSFIFO#(Integer n, function Bool searchfunc(search_T s, alpha_T x)) (SFIFO#(alpha_T, search_T)) + provisos + (Bits#(alpha_T,asz)); + + let foo <- mkSizedSFIFOInternal(n, searchfunc, searchfunc); + return foo; + +endmodule diff -r 6d1ff93e3afa -r 91a1f76ddd62 core/src/Trace.bsv --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/core/src/Trace.bsv Tue Apr 13 17:34:33 2010 -0400 @@ -0,0 +1,92 @@ + +import ClientServer::*; +import GetPut::*; + +//---------------------------------------------------------------------- +// ToString typeclass +//---------------------------------------------------------------------- + +typeclass Traceable#( type item_t ); + function Action traceTiny( String loc, String traceTag, item_t item ); + function Action traceFull( String loc, String traceTag, item_t item ); +endtypeclass + +instance Traceable#(String); + + function Action traceTiny( String loc, String ttag, String str ); + $fdisplay(stderr, " => %s:%s %s", loc, ttag, str ); + endfunction + + function Action traceFull( String loc, String ttag, String str ); + $fdisplay(stderr, " => %s:%s %s", loc, ttag, str ); + endfunction + +endinstance + +instance Traceable#(Bit#(n)); + + function Action traceTiny( String loc, String ttag, Bit#(n) b ); + $fdisplay(stderr, " => %s:%s %x", loc, ttag, b ); + endfunction + + function Action traceFull( String loc, String ttag, Bit#(n) b ); + $fdisplay(stderr, " => %s:%s %x", loc, ttag, b ); + endfunction + +endinstance + +//---------------------------------------------------------------------- +// Tracing interface wrappers +//---------------------------------------------------------------------- + +function Get#(item_t) traceGet( String locStr, String tagStr, Get#(item_t) g ) + provisos ( Traceable#(item_t) ); + return + ( + interface Get + method ActionValue#(item_t) get(); + item_t item <- g.get(); + traceTiny(locStr, tagStr,item); + return item; + endmethod + endinterface + ); +endfunction + +function Put#(item_t) tracePut( String locStr, String tagStr, Put#(item_t) p ) + provisos ( Traceable#(item_t) ); + return + ( + interface Put + method Action put( item_t item ); + traceTiny(locStr, tagStr,item); + p.put(item); + endmethod + endinterface + ); +endfunction + +function Client#(req_t,resp_t) traceClient( String locStr, String reqTagStr, String respTagStr, + Client#(req_t,resp_t) c ) + provisos ( Traceable#(req_t), Traceable#(resp_t) ); + return + ( + interface Client + interface Get request = traceGet(locStr, reqTagStr,c.request); + interface Put response = tracePut(locStr, respTagStr,c.response); + endinterface + ); +endfunction + +function Server#(req_t,resp_t) traceServer( String locStr, String reqTagStr, String respTagStr, + Server#(req_t,resp_t) c ) + provisos ( Traceable#(req_t), Traceable#(resp_t) ); + return + ( + interface Server + interface Put request = tracePut(locStr, reqTagStr,c.request); + interface Get response = traceGet(locStr, respTagStr,c.response); + endinterface + ); +endfunction +