changeset 63:1d5cbb5343d2 pygar svn.64

[svn r64] mods to compile correctly for FPGA
author punk
date Mon, 10 May 2010 22:54:54 -0400
parents 90fa9b289aab
children bf08daea854e
files modules/bluespec/Pygar/core/Processor.bsv modules/bluespec/Pygar/core/processor.awb modules/bluespec/Pygar/lab4/BRegFile.bsv modules/bluespec/Pygar/lab4/DataCacheBlocking.bsv modules/bluespec/Pygar/lab4/InstCacheBlocking.bsv modules/bluespec/Pygar/lab4/audio_processor_library.awb modules/bluespec/Pygar/lab4/data_cache.awb modules/bluespec/Pygar/lab4/instruction_cache.awb modules/bluespec/Pygar/lab4/processor_library.awb
diffstat 9 files changed, 159 insertions(+), 89 deletions(-) [+]
line wrap: on
line diff
     1.1 --- a/modules/bluespec/Pygar/core/Processor.bsv	Mon May 10 21:00:49 2010 -0400
     1.2 +++ b/modules/bluespec/Pygar/core/Processor.bsv	Mon May 10 22:54:54 2010 -0400
     1.3 @@ -83,34 +83,6 @@
     1.4  typedef enum { PCgen, Exec, Writeback } Stage deriving(Eq,Bits);
     1.5  
     1.6  //-----------------------------------------------------------
     1.7 -// Register file module
     1.8 -//-----------------------------------------------------------
     1.9 -
    1.10 -interface BRFile;
    1.11 -   method Action   wr( Rindx rindx, Bit#(32) data );
    1.12 -   method Bit#(32) rd1( Rindx rindx );
    1.13 -   method Bit#(32) rd2( Rindx rindx );
    1.14 -endinterface
    1.15 -
    1.16 -module mkBRFile( BRFile );
    1.17 -   
    1.18 -   RegFile#(Rindx,Bit#(32)) rfile <- mkBRegFile();
    1.19 -   
    1.20 -   method Action wr( Rindx rindx, Bit#(32) data );
    1.21 -      rfile.upd( rindx, data );
    1.22 -   endmethod
    1.23 -   
    1.24 -   method Bit#(32) rd1( Rindx rindx );
    1.25 -      return ( rindx == 0 ) ? 0 : rfile.sub(rindx);
    1.26 -   endmethod
    1.27 -   
    1.28 -   method Bit#(32) rd2( Rindx rindx );
    1.29 -      return ( rindx == 0 ) ? 0 : rfile.sub(rindx);
    1.30 -   endmethod
    1.31 -
    1.32 -endmodule
    1.33 -
    1.34 -//-----------------------------------------------------------
    1.35  // Helper functions
    1.36  //-----------------------------------------------------------
    1.37  
    1.38 @@ -225,7 +197,7 @@
    1.39     Reg#(Addr)  pc    <- mkReg(32'h00001000);
    1.40     Reg#(Epoch) epoch <- mkReg(0);
    1.41     Reg#(Stage) stage <- mkReg(PCgen);
    1.42 -   BRFile      rf    <- mkBRFile;
    1.43 +   BRegFile      rf  <- mkBRegFile;
    1.44  
    1.45     // Branch Prediction
    1.46     BranchPred               bp <- mkBranchPred();
    1.47 @@ -335,15 +307,18 @@
    1.48  
    1.49  	 tagged LW .it : 
    1.50  	    begin
    1.51 -               Addr addr = rf.rd1(it.rbase) + sext(it.offset);
    1.52 +	       let val_rbase <- rf.rd1(it.rbase);
    1.53 +               Addr addr = val_rbase + sext(it.offset);
    1.54                 dataReqQ.enq( LoadReq{ addr:addr, tag:zeroExtend(it.rdst) } );
    1.55                 wbQ.enq(tagged WB_Load it.rdst);
    1.56  	    end
    1.57  
    1.58  	 tagged SW .it : 
    1.59  	    begin
    1.60 -               Addr addr = rf.rd1(it.rbase) + sext(it.offset);
    1.61 -               dataReqQ.enq( StoreReq{ tag:0, addr:addr, data:rf.rd2(it.rsrc) } );
    1.62 +	       let val_rbase <- rf.rd1(it.rbase);
    1.63 +	       let val_rsrc2 <- rf.rd2(it.rsrc);
    1.64 +               Addr addr = val_rbase + sext(it.offset);
    1.65 +               dataReqQ.enq( StoreReq{ tag:0, addr:addr, data:val_rsrc2 } );
    1.66                 wbQ.enq(tagged WB_Store);
    1.67  	    end
    1.68  
    1.69 @@ -351,25 +326,37 @@
    1.70  
    1.71  	 tagged ADDIU .it : 
    1.72  	    begin
    1.73 -	       Bit#(32) result = rf.rd1(it.rsrc) + sext(it.imm);
    1.74 +	       let val_rsrc1 <- rf.rd1(it.rsrc); 
    1.75 +	       Bit#(32) result = val_rsrc1 + sext(it.imm);
    1.76  	       wbQ.enq(tagged WB_ALU {data:result, dest:it.rdst});
    1.77  	    end
    1.78 -	 tagged SLTI  .it : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:slt( rf.rd1(it.rsrc), sext(it.imm) )});
    1.79 -	 tagged SLTIU .it : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:sltu( rf.rd1(it.rsrc), sext(it.imm) ) });
    1.80 +	 tagged SLTI  .it : 
    1.81 +	    begin
    1.82 +	       let val_rsrc1 <- rf.rd1(it.rsrc); 
    1.83 +	       wbQ.enq(tagged WB_ALU {dest:it.rdst, data:slt( val_rsrc1, sext(it.imm) )});
    1.84 +	    end
    1.85 +	 tagged SLTIU .it : 
    1.86 +	    begin
    1.87 +	       let val_rsrc1 <- rf.rd1(it.rsrc); 
    1.88 +	       wbQ.enq(tagged WB_ALU {dest:it.rdst, data:sltu( val_rsrc1, sext(it.imm) ) });
    1.89 +	    end
    1.90  	 tagged ANDI  .it : 
    1.91  	    begin
    1.92 +	       let val_rsrc1 <- rf.rd1(it.rsrc); 
    1.93  	       Bit#(32) zext_it_imm = zext(it.imm);
    1.94 -	       wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(rf.rd1(it.rsrc) & zext_it_imm)} );
    1.95 +	       wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(val_rsrc1 & zext_it_imm)} );
    1.96  	    end
    1.97  	 tagged ORI   .it : 
    1.98  	    begin
    1.99 +	       let val_rsrc1 <- rf.rd1(it.rsrc); 
   1.100  	       Bit#(32) zext_it_imm = zext(it.imm);
   1.101 -	       wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(rf.rd1(it.rsrc) | zext_it_imm)} );
   1.102 +	       wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(val_rsrc1 | zext_it_imm)} );
   1.103  	    end
   1.104  	 tagged XORI  .it : 
   1.105  	    begin
   1.106 +	       let val_rsrc1 <- rf.rd1(it.rsrc); 
   1.107  	       Bit#(32) zext_it_imm = zext(it.imm);
   1.108 -	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) ^ zext_it_imm )});
   1.109 +	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc1 ^ zext_it_imm )});
   1.110  	    end
   1.111  	 tagged LUI   .it : 
   1.112  	    begin
   1.113 @@ -379,86 +366,165 @@
   1.114  	 
   1.115  	 tagged SLL   .it : 
   1.116  	    begin
   1.117 +	       let val_rsrc1 <- rf.rd1(it.rsrc); 
   1.118  	       Bit#(32) zext_it_shamt = zext(it.shamt);
   1.119 -	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) << zext_it_shamt )} );
   1.120 +	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc1 << zext_it_shamt )} );
   1.121  	    end
   1.122  	 tagged SRL   .it : 
   1.123  	    begin
   1.124 +	       let val_rsrc1 <- rf.rd1(it.rsrc); 
   1.125  	       Bit#(32) zext_it_shamt = zext(it.shamt);
   1.126 -	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) >> zext_it_shamt )});
   1.127 +	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc1 >> zext_it_shamt )});
   1.128  	    end
   1.129  	 tagged SRA   .it : 
   1.130  	    begin
   1.131 +	       let val_rsrc1 <- rf.rd1(it.rsrc); 
   1.132  	       Bit#(32) zext_it_shamt = zext(it.shamt);
   1.133 -	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( rf.rd1(it.rsrc), zext_it_shamt )});
   1.134 +	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( val_rsrc1, zext_it_shamt )});
   1.135  	    end
   1.136 -	 tagged SLLV  .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) << rshft(rf.rd2(it.rshamt)) )});
   1.137 -	 tagged SRLV  .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) >> rshft(rf.rd2(it.rshamt)) )} );
   1.138 -	 tagged SRAV  .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( rf.rd1(it.rsrc), rshft(rf.rd2(it.rshamt)) ) });
   1.139 -	 tagged ADDU  .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) + rf.rd2(it.rsrc2) )} );
   1.140 -	 tagged SUBU  .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) - rf.rd2(it.rsrc2) )} );
   1.141 -	 tagged AND   .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) & rf.rd2(it.rsrc2) )} );
   1.142 -	 tagged OR    .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) | rf.rd2(it.rsrc2) )} );
   1.143 -	 tagged XOR   .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) ^ rf.rd2(it.rsrc2) )} );
   1.144 -	 tagged NOR   .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(~(rf.rd1(it.rsrc1) | rf.rd2(it.rsrc2)) )} );
   1.145 -	 tagged SLT   .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:slt( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) });
   1.146 -	 tagged SLTU  .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sltu( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) });
   1.147 +	 tagged SLLV  .it : 
   1.148 +	    begin
   1.149 +	       let val_rsrc1 <- rf.rd1(it.rsrc);
   1.150 +	       let val_rshamt <- rf.rd2(it.rshamt); 
   1.151 +	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc1 << rshft(val_rshamt) )});
   1.152 +	    end	       
   1.153 +	 tagged SRLV  .it : 
   1.154 +	    begin
   1.155 +	       let val_rsrc1 <- rf.rd1(it.rsrc); 
   1.156 +	       let val_rshamt <- rf.rd2(it.rshamt); 
   1.157 +	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc1 >> rshft(val_rshamt) )} );
   1.158 +	    end	       
   1.159 +	 tagged SRAV  .it : 
   1.160 +	    begin
   1.161 +	       let val_rsrc1 <- rf.rd1(it.rsrc); 
   1.162 +	       let val_rshamt <- rf.rd2(it.rshamt); 
   1.163 +	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( val_rsrc1, rshft(val_rshamt) ) });
   1.164 +	    end	       
   1.165 +	 tagged ADDU  .it : 
   1.166 +	    begin
   1.167 +	       let val_rsrc11 <- rf.rd1(it.rsrc1); 
   1.168 +	       let val_rsrc22 <- rf.rd2(it.rsrc2); 
   1.169 +	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc11 + val_rsrc22 )} );
   1.170 +	    end
   1.171 +	 tagged SUBU  .it : 
   1.172 +	    begin
   1.173 +	       let val_rsrc11 <- rf.rd1(it.rsrc1); 
   1.174 +	       let val_rsrc22 <- rf.rd2(it.rsrc2); 
   1.175 +	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc11 - val_rsrc22 )} );
   1.176 +	    end
   1.177 +	 tagged AND   .it : 
   1.178 +	    begin
   1.179 +	       let val_rsrc11 <- rf.rd1(it.rsrc1); 
   1.180 +	       let val_rsrc22 <- rf.rd2(it.rsrc2); 
   1.181 +	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc11 & val_rsrc22 )} );
   1.182 +	    end
   1.183 +	 tagged OR    .it : 
   1.184 +	    begin
   1.185 +	       let val_rsrc11 <- rf.rd1(it.rsrc1); 
   1.186 +	       let val_rsrc22 <- rf.rd2(it.rsrc2); 
   1.187 +	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc11 | val_rsrc22 )} );
   1.188 +	    end
   1.189 +	 tagged XOR   .it : 
   1.190 +	    begin
   1.191 +	       let val_rsrc11 <- rf.rd1(it.rsrc1); 
   1.192 +	       let val_rsrc22 <- rf.rd2(it.rsrc2); 
   1.193 +	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc11 ^ val_rsrc22 )} );
   1.194 +	    end
   1.195 +	 tagged NOR   .it : 
   1.196 +	    begin
   1.197 +	       let val_rsrc11 <- rf.rd1(it.rsrc1); 
   1.198 +	       let val_rsrc22 <- rf.rd2(it.rsrc2); 
   1.199 +	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(~(val_rsrc11 | val_rsrc22) )} );
   1.200 +	    end
   1.201 +	 tagged SLT   .it : 
   1.202 +	    begin
   1.203 +	       let val_rsrc11 <- rf.rd1(it.rsrc1); 
   1.204 +	       let val_rsrc22 <- rf.rd2(it.rsrc2); 
   1.205 +	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:slt( val_rsrc11, val_rsrc22 ) });
   1.206 +	    end
   1.207 +	 tagged SLTU  .it : 
   1.208 +	    begin
   1.209 +	       let val_rsrc11 <- rf.rd1(it.rsrc1); 
   1.210 +	       let val_rsrc22 <- rf.rd2(it.rsrc2); 
   1.211 +	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sltu( val_rsrc11, val_rsrc22 ) });
   1.212 +	    end
   1.213  
   1.214  	 // -- Branches --------------------------------------------------
   1.215  
   1.216  	 tagged BLEZ  .it : 
   1.217 -            if ( signedLE( rf.rd1(it.rsrc), 0 ) )
   1.218 -	       begin
   1.219 +	    begin
   1.220 +	       let val_rsrc1 <- rf.rd1(it.rsrc); 
   1.221 +	         if ( signedLE( val_rsrc1, 0 ) )
   1.222 +	       	 begin
   1.223  		  newPC = pc_plus4 + (sext(it.offset) << 2);
   1.224  		  branchTaken = True;
   1.225 -	       end
   1.226 +	       	 end
   1.227 +	    end
   1.228  
   1.229  	 tagged BGTZ  .it : 
   1.230 -            if ( signedGT( rf.rd1(it.rsrc), 0 ) ) 
   1.231 +	    begin
   1.232 +	       let val_rsrc1 <- rf.rd1(it.rsrc); 
   1.233 +               if ( signedGT( val_rsrc1, 0 ) ) 
   1.234                 begin 
   1.235  		  newPC = pc_plus4 + (sext(it.offset) << 2);
   1.236  		  branchTaken = True;
   1.237  	       end
   1.238 +	    end
   1.239  
   1.240  	 tagged BLTZ  .it : 
   1.241 -            if ( signedLT( rf.rd1(it.rsrc), 0 ) )
   1.242 +	    begin
   1.243 +	       let val_rsrc1 <- rf.rd1(it.rsrc); 
   1.244 +               if ( signedLT( val_rsrc1, 0 ) )
   1.245                 begin 
   1.246  		  newPC = pc_plus4 + (sext(it.offset) << 2);
   1.247  		  branchTaken = True;
   1.248  	       end
   1.249 +	    end
   1.250  		  
   1.251 -	 tagged BGEZ  .it : 
   1.252 -            if ( signedGE( rf.rd1(it.rsrc), 0 ) )
   1.253 -               begin 
   1.254 -		  newPC = pc_plus4 + (sext(it.offset) << 2);		  
   1.255 -		  branchTaken = True;
   1.256 -	       end
   1.257 +	 tagged BGEZ  .it :
   1.258 +	    begin
   1.259 +	       let val_rsrc1 <- rf.rd1(it.rsrc); 
   1.260 +                 if ( signedGE( val_rsrc1, 0 ) )
   1.261 +               	 begin 
   1.262 +		        newPC = pc_plus4 + (sext(it.offset) << 2);		  
   1.263 +		  	branchTaken = True;
   1.264 +	         end
   1.265 +	    end
   1.266  
   1.267        tagged BEQ   .it : 
   1.268 -        if ( rf.rd1(it.rsrc1) == rf.rd2(it.rsrc2) )
   1.269 +        begin
   1.270 +	  let val_rsrc11 <- rf.rd1(it.rsrc1); 
   1.271 +	  let val_rsrc22 <- rf.rd2(it.rsrc2); 
   1.272 +          if ( val_rsrc11 == val_rsrc22 )
   1.273            begin 
   1.274  	     newPC = pc_plus4 + (sext(it.offset) << 2);
   1.275  	     branchTaken = True;
   1.276  	  end
   1.277 +	end
   1.278  
   1.279        tagged BNE   .it : 
   1.280 -        if ( rf.rd1(it.rsrc1) != rf.rd2(it.rsrc2) )
   1.281 +        begin
   1.282 +	  let val_rsrc11 <- rf.rd1(it.rsrc1); 
   1.283 +	  let val_rsrc22 <- rf.rd2(it.rsrc2); 
   1.284 +          if ( val_rsrc11 != val_rsrc22 )
   1.285            begin 
   1.286  	     newPC = pc_plus4 + (sext(it.offset) << 2);
   1.287  	     branchTaken = True;
   1.288  	  end
   1.289 +	end
   1.290  
   1.291        // -- Jumps -----------------------------------------------------
   1.292        
   1.293        tagged J     .it : 
   1.294 -        begin 
   1.295 +        begin
   1.296  	   newPC = { pc_plus4[31:28], it.target, 2'b0 };
   1.297  	   branchTaken = True;
   1.298  	end
   1.299        
   1.300        tagged JR    .it : 
   1.301          begin
   1.302 -	   newPC = rf.rd1(it.rsrc);
   1.303 +	   let val_rsrc1 <- rf.rd1(it.rsrc); 
   1.304 +	   newPC = val_rsrc1;
   1.305  	   branchTaken = True;
   1.306  	end
   1.307  
   1.308 @@ -471,8 +537,9 @@
   1.309  
   1.310        tagged JALR  .it : 
   1.311         begin
   1.312 +	  let val_rsrc1 <- rf.rd1(it.rsrc); 
   1.313            wbQ.enq(tagged WB_ALU {dest:it.rdst, data:pc_plus4 });
   1.314 -          newPC = rf.rd1(it.rsrc);
   1.315 +          newPC = val_rsrc1;
   1.316  	  branchTaken = True;
   1.317         end
   1.318  
   1.319 @@ -480,12 +547,13 @@
   1.320        
   1.321        tagged MTC0  .it : //Recieve things from host computer
   1.322  	 begin
   1.323 + 	  let val_rsrc1 <- rf.rd1(it.rsrc); 
   1.324  //	    $display( " PROCESSOR MTC0 call\n");
   1.325              case ( it.cop0dst )
   1.326 -	       5'd10 : cp0_statsEn <= unpack(truncate(rf.rd1(it.rsrc)));
   1.327 -	       5'd21 : cp0_tohost  <= truncate(rf.rd1(it.rsrc));
   1.328 -	       5'd26 : cp0_progComp <= unpack(truncate(rf.rd1(it.rsrc))); //states audio program completed and termination okay
   1.329 - 	       5'd27 : outAudioFifo.enq(tagged Sample unpack(truncate(rf.rd1(it.rsrc))));  //Bit size is 16 not 32 
   1.330 +	       5'd10 : cp0_statsEn <= unpack(truncate(val_rsrc1));
   1.331 +	       5'd21 : cp0_tohost  <= truncate(val_rsrc1);
   1.332 +	       5'd26 : cp0_progComp <= unpack(truncate(val_rsrc1)); //states audio program completed and termination okay
   1.333 + 	       5'd27 : outAudioFifo.enq(tagged Sample unpack(truncate(val_rsrc1)));  //Bit size is 16 not 32 
   1.334  	       default :
   1.335  	       $display( " RTL-ERROR : %m : Illegal MTC0 cop0dst register!" );
   1.336  	    endcase
     2.1 --- a/modules/bluespec/Pygar/core/processor.awb	Mon May 10 21:00:49 2010 -0400
     2.2 +++ b/modules/bluespec/Pygar/core/processor.awb	Mon May 10 22:54:54 2010 -0400
     2.3 @@ -11,3 +11,4 @@
     2.4  
     2.5  
     2.6  
     2.7 +
     3.1 --- a/modules/bluespec/Pygar/lab4/BRegFile.bsv	Mon May 10 21:00:49 2010 -0400
     3.2 +++ b/modules/bluespec/Pygar/lab4/BRegFile.bsv	Mon May 10 22:54:54 2010 -0400
     3.3 @@ -11,29 +11,25 @@
     3.4  // Register file module
     3.5  //-----------------------------------------------------------
     3.6  
     3.7 -interface BRFile;
     3.8 +interface BRegFile;
     3.9     method Action   wr( Rindx rindx, Bit#(32) data );
    3.10 -   method Action Value Bit#(32) rd1( Rindx rindx );
    3.11 -   method Action Value Bit#(32) rd2( Rindx rindx );
    3.12 +   method ActionValue#( Bit#(32)) rd1( Rindx rindx );
    3.13 +   method ActionValue#( Bit#(32)) rd2( Rindx rindx );
    3.14  endinterface
    3.15  
    3.16  (* doc = "synthesis attribute ram_style mkBRegFile distributed;" *)
    3.17  (* synthesize *)
    3.18 -module mkBRegFile(BRFile) 
    3.19 -   provisos (Bits#(index_t, size_index),
    3.20 -	     Bits#(data_t, size_data),
    3.21 -	     Eq#(index_t),
    3.22 -	     Bounded#(index_t) );
    3.23 +module mkBRegFile(BRegFile);
    3.24  
    3.25 -   LUTRAM#(index_t, data_t) rf <- mkLUTRAMU_RegFile();
    3.26 -   RWire#(Tuple2#(index_t, data_t)) rw <-mkRWire();
    3.27 +   LUTRAM#(Rindx, Bit#(32)) rf <- mkLUTRAMU_RegFile();
    3.28 +   RWire#(Tuple2#(Rindx, Bit#(32))) rw <-mkRWire();
    3.29  
    3.30     method Action wr( Rindx rindx, Bit#(32) data );
    3.31        rf.upd( rindx, data );
    3.32 -      rw.wset(tuple2(rindex,data));
    3.33 +      rw.wset(tuple2(rindx,data));
    3.34     endmethod
    3.35  
    3.36 -   method Bit#(32) rd1 (Rindx r);
    3.37 +   method ActionValue#(Bit#(32)) rd1 (Rindx r);
    3.38        if (r == 0) return 0;
    3.39        else begin
    3.40              case (rw.wget()) matches
    3.41 @@ -44,7 +40,7 @@
    3.42  	   end
    3.43     endmethod
    3.44  
    3.45 -   method Bit#(32) rd2 (Rindx r);
    3.46 +   method ActionValue#(Bit#(32)) rd2 (Rindx r);
    3.47        if (r == 0) return 0;
    3.48        else begin
    3.49              case (rw.wget()) matches
     4.1 --- a/modules/bluespec/Pygar/lab4/DataCacheBlocking.bsv	Mon May 10 21:00:49 2010 -0400
     4.2 +++ b/modules/bluespec/Pygar/lab4/DataCacheBlocking.bsv	Mon May 10 22:54:54 2010 -0400
     4.3 @@ -110,7 +110,7 @@
     4.4  
     4.5  (* doc = "synthesis attribute ram_style mkDataCache distributed;" *)
     4.6  (* synthesize *)
     4.7 -module [CONNECTED_MODULE] mkDataCache( DCache#(DataReq,DataResp) );
     4.8 +module mkDataCache( DCache#(DataReq,DataResp) );
     4.9  
    4.10    //-----------------------------------------------------------
    4.11    // State
     5.1 --- a/modules/bluespec/Pygar/lab4/InstCacheBlocking.bsv	Mon May 10 21:00:49 2010 -0400
     5.2 +++ b/modules/bluespec/Pygar/lab4/InstCacheBlocking.bsv	Mon May 10 22:54:54 2010 -0400
     5.3 @@ -111,7 +111,7 @@
     5.4  
     5.5  (* doc = "synthesis attribute ram_style mkInstCache distributed;" *)
     5.6  (* synthesize *)
     5.7 -module [CONNECTED_MODULE] mkInstCache( ICache#(InstReq,InstResp) );
     5.8 +module mkInstCache( ICache#(InstReq,InstResp) );
     5.9  
    5.10    //-----------------------------------------------------------
    5.11    // State
     6.1 --- a/modules/bluespec/Pygar/lab4/audio_processor_library.awb	Mon May 10 21:00:49 2010 -0400
     6.2 +++ b/modules/bluespec/Pygar/lab4/audio_processor_library.awb	Mon May 10 22:54:54 2010 -0400
     6.3 @@ -8,3 +8,7 @@
     6.4  %attributes PYGAR
     6.5  
     6.6  %public BFIFO.bsv MemTypes.bsv FIFOUtility.bsv GetPutExt.bsv SFIFO.bsv CBUFF.bsv BRegFile.bsv BranchPred.bsv
     6.7 +
     6.8 +%generated -t VERILOG mkBRegFile.v
     6.9 +%generated -t BA mkBRegFile.ba
    6.10 +
     7.1 --- a/modules/bluespec/Pygar/lab4/data_cache.awb	Mon May 10 21:00:49 2010 -0400
     7.2 +++ b/modules/bluespec/Pygar/lab4/data_cache.awb	Mon May 10 22:54:54 2010 -0400
     7.3 @@ -9,4 +9,4 @@
     7.4  %public DataCache.dic
     7.5  
     7.6  %generated -t VERILOG mkDataCache.v
     7.7 -%generated -t BA mkDataCache.ba
     7.8 \ No newline at end of file
     7.9 +%generated -t BA mkDataCache.ba
     8.1 --- a/modules/bluespec/Pygar/lab4/instruction_cache.awb	Mon May 10 21:00:49 2010 -0400
     8.2 +++ b/modules/bluespec/Pygar/lab4/instruction_cache.awb	Mon May 10 22:54:54 2010 -0400
     8.3 @@ -9,4 +9,4 @@
     8.4  %public InstCache.dic
     8.5  
     8.6  %generated -t VERILOG mkInstCache.v
     8.7 -%generated -t BA mkInstCache.ba
     8.8 \ No newline at end of file
     8.9 +%generated -t BA mkInstCache.ba
     9.1 --- a/modules/bluespec/Pygar/lab4/processor_library.awb	Mon May 10 21:00:49 2010 -0400
     9.2 +++ b/modules/bluespec/Pygar/lab4/processor_library.awb	Mon May 10 22:54:54 2010 -0400
     9.3 @@ -9,3 +9,4 @@
     9.4  
     9.5  %generated -t VERILOG mkBRegFile.v
     9.6  %generated -t BA mkBRegFile.ba
     9.7 +