# HG changeset patch # User punk # Date 1273546494 14400 # Node ID 1d5cbb5343d274e9ee4acd5d9e0131e1eb3f0534 # Parent 90fa9b289aab976dc08859e7b96ceaa5c6b004e5 [svn r64] mods to compile correctly for FPGA diff -r 90fa9b289aab -r 1d5cbb5343d2 modules/bluespec/Pygar/core/Processor.bsv --- a/modules/bluespec/Pygar/core/Processor.bsv Mon May 10 21:00:49 2010 -0400 +++ b/modules/bluespec/Pygar/core/Processor.bsv Mon May 10 22:54:54 2010 -0400 @@ -83,34 +83,6 @@ typedef enum { PCgen, Exec, Writeback } Stage deriving(Eq,Bits); //----------------------------------------------------------- -// Register file module -//----------------------------------------------------------- - -interface BRFile; - method Action wr( Rindx rindx, Bit#(32) data ); - method Bit#(32) rd1( Rindx rindx ); - method Bit#(32) rd2( Rindx rindx ); -endinterface - -module mkBRFile( BRFile ); - - RegFile#(Rindx,Bit#(32)) rfile <- mkBRegFile(); - - method Action wr( Rindx rindx, Bit#(32) data ); - rfile.upd( rindx, data ); - endmethod - - method Bit#(32) rd1( Rindx rindx ); - return ( rindx == 0 ) ? 0 : rfile.sub(rindx); - endmethod - - method Bit#(32) rd2( Rindx rindx ); - return ( rindx == 0 ) ? 0 : rfile.sub(rindx); - endmethod - -endmodule - -//----------------------------------------------------------- // Helper functions //----------------------------------------------------------- @@ -225,7 +197,7 @@ Reg#(Addr) pc <- mkReg(32'h00001000); Reg#(Epoch) epoch <- mkReg(0); Reg#(Stage) stage <- mkReg(PCgen); - BRFile rf <- mkBRFile; + BRegFile rf <- mkBRegFile; // Branch Prediction BranchPred bp <- mkBranchPred(); @@ -335,15 +307,18 @@ tagged LW .it : begin - Addr addr = rf.rd1(it.rbase) + sext(it.offset); + let val_rbase <- rf.rd1(it.rbase); + Addr addr = val_rbase + sext(it.offset); dataReqQ.enq( LoadReq{ addr:addr, tag:zeroExtend(it.rdst) } ); wbQ.enq(tagged WB_Load it.rdst); end tagged SW .it : begin - Addr addr = rf.rd1(it.rbase) + sext(it.offset); - dataReqQ.enq( StoreReq{ tag:0, addr:addr, data:rf.rd2(it.rsrc) } ); + let val_rbase <- rf.rd1(it.rbase); + let val_rsrc2 <- rf.rd2(it.rsrc); + Addr addr = val_rbase + sext(it.offset); + dataReqQ.enq( StoreReq{ tag:0, addr:addr, data:val_rsrc2 } ); wbQ.enq(tagged WB_Store); end @@ -351,25 +326,37 @@ tagged ADDIU .it : begin - Bit#(32) result = rf.rd1(it.rsrc) + sext(it.imm); + let val_rsrc1 <- rf.rd1(it.rsrc); + Bit#(32) result = val_rsrc1 + sext(it.imm); wbQ.enq(tagged WB_ALU {data:result, dest:it.rdst}); end - tagged SLTI .it : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:slt( rf.rd1(it.rsrc), sext(it.imm) )}); - tagged SLTIU .it : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:sltu( rf.rd1(it.rsrc), sext(it.imm) ) }); + tagged SLTI .it : + begin + let val_rsrc1 <- rf.rd1(it.rsrc); + wbQ.enq(tagged WB_ALU {dest:it.rdst, data:slt( val_rsrc1, sext(it.imm) )}); + end + tagged SLTIU .it : + begin + let val_rsrc1 <- rf.rd1(it.rsrc); + wbQ.enq(tagged WB_ALU {dest:it.rdst, data:sltu( val_rsrc1, sext(it.imm) ) }); + end tagged ANDI .it : begin + let val_rsrc1 <- rf.rd1(it.rsrc); Bit#(32) zext_it_imm = zext(it.imm); - wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(rf.rd1(it.rsrc) & zext_it_imm)} ); + wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(val_rsrc1 & zext_it_imm)} ); end tagged ORI .it : begin + let val_rsrc1 <- rf.rd1(it.rsrc); Bit#(32) zext_it_imm = zext(it.imm); - wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(rf.rd1(it.rsrc) | zext_it_imm)} ); + wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(val_rsrc1 | zext_it_imm)} ); end tagged XORI .it : begin + let val_rsrc1 <- rf.rd1(it.rsrc); Bit#(32) zext_it_imm = zext(it.imm); - wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) ^ zext_it_imm )}); + wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc1 ^ zext_it_imm )}); end tagged LUI .it : begin @@ -379,86 +366,165 @@ tagged SLL .it : begin + let val_rsrc1 <- rf.rd1(it.rsrc); Bit#(32) zext_it_shamt = zext(it.shamt); - wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) << zext_it_shamt )} ); + wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc1 << zext_it_shamt )} ); end tagged SRL .it : begin + let val_rsrc1 <- rf.rd1(it.rsrc); Bit#(32) zext_it_shamt = zext(it.shamt); - wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) >> zext_it_shamt )}); + wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc1 >> zext_it_shamt )}); end tagged SRA .it : begin + let val_rsrc1 <- rf.rd1(it.rsrc); Bit#(32) zext_it_shamt = zext(it.shamt); - wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( rf.rd1(it.rsrc), zext_it_shamt )}); + wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( val_rsrc1, zext_it_shamt )}); end - tagged SLLV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) << rshft(rf.rd2(it.rshamt)) )}); - tagged SRLV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) >> rshft(rf.rd2(it.rshamt)) )} ); - tagged SRAV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( rf.rd1(it.rsrc), rshft(rf.rd2(it.rshamt)) ) }); - tagged ADDU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) + rf.rd2(it.rsrc2) )} ); - tagged SUBU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) - rf.rd2(it.rsrc2) )} ); - tagged AND .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) & rf.rd2(it.rsrc2) )} ); - tagged OR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) | rf.rd2(it.rsrc2) )} ); - tagged XOR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) ^ rf.rd2(it.rsrc2) )} ); - tagged NOR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(~(rf.rd1(it.rsrc1) | rf.rd2(it.rsrc2)) )} ); - tagged SLT .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:slt( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) }); - tagged SLTU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sltu( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) }); + tagged SLLV .it : + begin + let val_rsrc1 <- rf.rd1(it.rsrc); + let val_rshamt <- rf.rd2(it.rshamt); + wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc1 << rshft(val_rshamt) )}); + end + tagged SRLV .it : + begin + let val_rsrc1 <- rf.rd1(it.rsrc); + let val_rshamt <- rf.rd2(it.rshamt); + wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc1 >> rshft(val_rshamt) )} ); + end + tagged SRAV .it : + begin + let val_rsrc1 <- rf.rd1(it.rsrc); + let val_rshamt <- rf.rd2(it.rshamt); + wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( val_rsrc1, rshft(val_rshamt) ) }); + end + tagged ADDU .it : + begin + let val_rsrc11 <- rf.rd1(it.rsrc1); + let val_rsrc22 <- rf.rd2(it.rsrc2); + wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc11 + val_rsrc22 )} ); + end + tagged SUBU .it : + begin + let val_rsrc11 <- rf.rd1(it.rsrc1); + let val_rsrc22 <- rf.rd2(it.rsrc2); + wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc11 - val_rsrc22 )} ); + end + tagged AND .it : + begin + let val_rsrc11 <- rf.rd1(it.rsrc1); + let val_rsrc22 <- rf.rd2(it.rsrc2); + wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc11 & val_rsrc22 )} ); + end + tagged OR .it : + begin + let val_rsrc11 <- rf.rd1(it.rsrc1); + let val_rsrc22 <- rf.rd2(it.rsrc2); + wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc11 | val_rsrc22 )} ); + end + tagged XOR .it : + begin + let val_rsrc11 <- rf.rd1(it.rsrc1); + let val_rsrc22 <- rf.rd2(it.rsrc2); + wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc11 ^ val_rsrc22 )} ); + end + tagged NOR .it : + begin + let val_rsrc11 <- rf.rd1(it.rsrc1); + let val_rsrc22 <- rf.rd2(it.rsrc2); + wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(~(val_rsrc11 | val_rsrc22) )} ); + end + tagged SLT .it : + begin + let val_rsrc11 <- rf.rd1(it.rsrc1); + let val_rsrc22 <- rf.rd2(it.rsrc2); + wbQ.enq(tagged WB_ALU {dest: it.rdst, data:slt( val_rsrc11, val_rsrc22 ) }); + end + tagged SLTU .it : + begin + let val_rsrc11 <- rf.rd1(it.rsrc1); + let val_rsrc22 <- rf.rd2(it.rsrc2); + wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sltu( val_rsrc11, val_rsrc22 ) }); + end // -- Branches -------------------------------------------------- tagged BLEZ .it : - if ( signedLE( rf.rd1(it.rsrc), 0 ) ) - begin + begin + let val_rsrc1 <- rf.rd1(it.rsrc); + if ( signedLE( val_rsrc1, 0 ) ) + begin newPC = pc_plus4 + (sext(it.offset) << 2); branchTaken = True; - end + end + end tagged BGTZ .it : - if ( signedGT( rf.rd1(it.rsrc), 0 ) ) + begin + let val_rsrc1 <- rf.rd1(it.rsrc); + if ( signedGT( val_rsrc1, 0 ) ) begin newPC = pc_plus4 + (sext(it.offset) << 2); branchTaken = True; end + end tagged BLTZ .it : - if ( signedLT( rf.rd1(it.rsrc), 0 ) ) + begin + let val_rsrc1 <- rf.rd1(it.rsrc); + if ( signedLT( val_rsrc1, 0 ) ) begin newPC = pc_plus4 + (sext(it.offset) << 2); branchTaken = True; end + end - tagged BGEZ .it : - if ( signedGE( rf.rd1(it.rsrc), 0 ) ) - begin - newPC = pc_plus4 + (sext(it.offset) << 2); - branchTaken = True; - end + tagged BGEZ .it : + begin + let val_rsrc1 <- rf.rd1(it.rsrc); + if ( signedGE( val_rsrc1, 0 ) ) + begin + newPC = pc_plus4 + (sext(it.offset) << 2); + branchTaken = True; + end + end tagged BEQ .it : - if ( rf.rd1(it.rsrc1) == rf.rd2(it.rsrc2) ) + begin + let val_rsrc11 <- rf.rd1(it.rsrc1); + let val_rsrc22 <- rf.rd2(it.rsrc2); + if ( val_rsrc11 == val_rsrc22 ) begin newPC = pc_plus4 + (sext(it.offset) << 2); branchTaken = True; end + end tagged BNE .it : - if ( rf.rd1(it.rsrc1) != rf.rd2(it.rsrc2) ) + begin + let val_rsrc11 <- rf.rd1(it.rsrc1); + let val_rsrc22 <- rf.rd2(it.rsrc2); + if ( val_rsrc11 != val_rsrc22 ) begin newPC = pc_plus4 + (sext(it.offset) << 2); branchTaken = True; end + end // -- Jumps ----------------------------------------------------- tagged J .it : - begin + begin newPC = { pc_plus4[31:28], it.target, 2'b0 }; branchTaken = True; end tagged JR .it : begin - newPC = rf.rd1(it.rsrc); + let val_rsrc1 <- rf.rd1(it.rsrc); + newPC = val_rsrc1; branchTaken = True; end @@ -471,8 +537,9 @@ tagged JALR .it : begin + let val_rsrc1 <- rf.rd1(it.rsrc); wbQ.enq(tagged WB_ALU {dest:it.rdst, data:pc_plus4 }); - newPC = rf.rd1(it.rsrc); + newPC = val_rsrc1; branchTaken = True; end @@ -480,12 +547,13 @@ tagged MTC0 .it : //Recieve things from host computer begin + let val_rsrc1 <- rf.rd1(it.rsrc); // $display( " PROCESSOR MTC0 call\n"); case ( it.cop0dst ) - 5'd10 : cp0_statsEn <= unpack(truncate(rf.rd1(it.rsrc))); - 5'd21 : cp0_tohost <= truncate(rf.rd1(it.rsrc)); - 5'd26 : cp0_progComp <= unpack(truncate(rf.rd1(it.rsrc))); //states audio program completed and termination okay - 5'd27 : outAudioFifo.enq(tagged Sample unpack(truncate(rf.rd1(it.rsrc)))); //Bit size is 16 not 32 + 5'd10 : cp0_statsEn <= unpack(truncate(val_rsrc1)); + 5'd21 : cp0_tohost <= truncate(val_rsrc1); + 5'd26 : cp0_progComp <= unpack(truncate(val_rsrc1)); //states audio program completed and termination okay + 5'd27 : outAudioFifo.enq(tagged Sample unpack(truncate(val_rsrc1))); //Bit size is 16 not 32 default : $display( " RTL-ERROR : %m : Illegal MTC0 cop0dst register!" ); endcase diff -r 90fa9b289aab -r 1d5cbb5343d2 modules/bluespec/Pygar/core/processor.awb --- a/modules/bluespec/Pygar/core/processor.awb Mon May 10 21:00:49 2010 -0400 +++ b/modules/bluespec/Pygar/core/processor.awb Mon May 10 22:54:54 2010 -0400 @@ -11,3 +11,4 @@ + diff -r 90fa9b289aab -r 1d5cbb5343d2 modules/bluespec/Pygar/lab4/BRegFile.bsv --- a/modules/bluespec/Pygar/lab4/BRegFile.bsv Mon May 10 21:00:49 2010 -0400 +++ b/modules/bluespec/Pygar/lab4/BRegFile.bsv Mon May 10 22:54:54 2010 -0400 @@ -11,29 +11,25 @@ // Register file module //----------------------------------------------------------- -interface BRFile; +interface BRegFile; method Action wr( Rindx rindx, Bit#(32) data ); - method Action Value Bit#(32) rd1( Rindx rindx ); - method Action Value Bit#(32) rd2( Rindx rindx ); + method ActionValue#( Bit#(32)) rd1( Rindx rindx ); + method ActionValue#( Bit#(32)) rd2( Rindx rindx ); endinterface (* doc = "synthesis attribute ram_style mkBRegFile distributed;" *) (* synthesize *) -module mkBRegFile(BRFile) - provisos (Bits#(index_t, size_index), - Bits#(data_t, size_data), - Eq#(index_t), - Bounded#(index_t) ); +module mkBRegFile(BRegFile); - LUTRAM#(index_t, data_t) rf <- mkLUTRAMU_RegFile(); - RWire#(Tuple2#(index_t, data_t)) rw <-mkRWire(); + LUTRAM#(Rindx, Bit#(32)) rf <- mkLUTRAMU_RegFile(); + RWire#(Tuple2#(Rindx, Bit#(32))) rw <-mkRWire(); method Action wr( Rindx rindx, Bit#(32) data ); rf.upd( rindx, data ); - rw.wset(tuple2(rindex,data)); + rw.wset(tuple2(rindx,data)); endmethod - method Bit#(32) rd1 (Rindx r); + method ActionValue#(Bit#(32)) rd1 (Rindx r); if (r == 0) return 0; else begin case (rw.wget()) matches @@ -44,7 +40,7 @@ end endmethod - method Bit#(32) rd2 (Rindx r); + method ActionValue#(Bit#(32)) rd2 (Rindx r); if (r == 0) return 0; else begin case (rw.wget()) matches diff -r 90fa9b289aab -r 1d5cbb5343d2 modules/bluespec/Pygar/lab4/DataCacheBlocking.bsv --- a/modules/bluespec/Pygar/lab4/DataCacheBlocking.bsv Mon May 10 21:00:49 2010 -0400 +++ b/modules/bluespec/Pygar/lab4/DataCacheBlocking.bsv Mon May 10 22:54:54 2010 -0400 @@ -110,7 +110,7 @@ (* doc = "synthesis attribute ram_style mkDataCache distributed;" *) (* synthesize *) -module [CONNECTED_MODULE] mkDataCache( DCache#(DataReq,DataResp) ); +module mkDataCache( DCache#(DataReq,DataResp) ); //----------------------------------------------------------- // State diff -r 90fa9b289aab -r 1d5cbb5343d2 modules/bluespec/Pygar/lab4/InstCacheBlocking.bsv --- a/modules/bluespec/Pygar/lab4/InstCacheBlocking.bsv Mon May 10 21:00:49 2010 -0400 +++ b/modules/bluespec/Pygar/lab4/InstCacheBlocking.bsv Mon May 10 22:54:54 2010 -0400 @@ -111,7 +111,7 @@ (* doc = "synthesis attribute ram_style mkInstCache distributed;" *) (* synthesize *) -module [CONNECTED_MODULE] mkInstCache( ICache#(InstReq,InstResp) ); +module mkInstCache( ICache#(InstReq,InstResp) ); //----------------------------------------------------------- // State diff -r 90fa9b289aab -r 1d5cbb5343d2 modules/bluespec/Pygar/lab4/audio_processor_library.awb --- a/modules/bluespec/Pygar/lab4/audio_processor_library.awb Mon May 10 21:00:49 2010 -0400 +++ b/modules/bluespec/Pygar/lab4/audio_processor_library.awb Mon May 10 22:54:54 2010 -0400 @@ -8,3 +8,7 @@ %attributes PYGAR %public BFIFO.bsv MemTypes.bsv FIFOUtility.bsv GetPutExt.bsv SFIFO.bsv CBUFF.bsv BRegFile.bsv BranchPred.bsv + +%generated -t VERILOG mkBRegFile.v +%generated -t BA mkBRegFile.ba + diff -r 90fa9b289aab -r 1d5cbb5343d2 modules/bluespec/Pygar/lab4/data_cache.awb --- a/modules/bluespec/Pygar/lab4/data_cache.awb Mon May 10 21:00:49 2010 -0400 +++ b/modules/bluespec/Pygar/lab4/data_cache.awb Mon May 10 22:54:54 2010 -0400 @@ -9,4 +9,4 @@ %public DataCache.dic %generated -t VERILOG mkDataCache.v -%generated -t BA mkDataCache.ba \ No newline at end of file +%generated -t BA mkDataCache.ba diff -r 90fa9b289aab -r 1d5cbb5343d2 modules/bluespec/Pygar/lab4/instruction_cache.awb --- a/modules/bluespec/Pygar/lab4/instruction_cache.awb Mon May 10 21:00:49 2010 -0400 +++ b/modules/bluespec/Pygar/lab4/instruction_cache.awb Mon May 10 22:54:54 2010 -0400 @@ -9,4 +9,4 @@ %public InstCache.dic %generated -t VERILOG mkInstCache.v -%generated -t BA mkInstCache.ba \ No newline at end of file +%generated -t BA mkInstCache.ba diff -r 90fa9b289aab -r 1d5cbb5343d2 modules/bluespec/Pygar/lab4/processor_library.awb --- a/modules/bluespec/Pygar/lab4/processor_library.awb Mon May 10 21:00:49 2010 -0400 +++ b/modules/bluespec/Pygar/lab4/processor_library.awb Mon May 10 22:54:54 2010 -0400 @@ -9,3 +9,4 @@ %generated -t VERILOG mkBRegFile.v %generated -t BA mkBRegFile.ba +