view modules/bluespec/Pygar/core/audioCorePipeline.bsv @ 46:adcfa79d2c67 pygar svn.47

[svn r47] thru.c vmh which forwards sample
author punk
date Wed, 05 May 2010 12:43:51 -0400
parents 4d87fa55a776
children 97d1959f7c5c
line wrap: on
line source
1 // The MIT License
3 // Copyright (c) 2009 Massachusetts Institute of Technology
5 // Permission is hereby granted, free of charge, to any person obtaining a copy
6 // of this software and associated documentation files (the "Software"), to deal
7 // in the Software without restriction, including without limitation the rights
8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 // copies of the Software, and to permit persons to whom the Software is
10 // furnished to do so, subject to the following conditions:
12 // The above copyright notice and this permission notice shall be included in
13 // all copies or substantial portions of the Software.
15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
21 // THE SOFTWARE.
23 // Author: Kermin Fleming kfleming@mit.edu
25 import Connectable::*;
26 import GetPut::*;
27 import ClientServer::*;
28 import FIFO::*;
29 import SpecialFIFOs::*;
31 //AWB includes
32 `include "asim/provides/low_level_platform_interface.bsh"
33 `include "asim/provides/soft_connections.bsh"
34 `include "asim/provides/common_services.bsh"
36 //Local includes
37 `include "asim/provides/audio_pipe_types.bsh" //provides Audio Pipeline interface
38 `include "asim/provides/path_types.bsh"
39 `include "asim/provides/core.bsh"
40 `include "asim/provides/mixer.bsh"
41 `include "asim/provides/processor_library.bsh"
42 `include "asim/provides/fpga_components.bsh"
43 `include "asim/provides/scratchpad_memory.bsh"
44 `include "asim/provides/mem_services.bsh"
45 `include "asim/dict/VDEV_SCRATCH.bsh"
47 `include "asim/rrr/remote_client_stub_AUDIOCORERRR.bsh"
48 `include "asim/rrr/remote_server_stub_AUDIOCORERRR.bsh"
50 module [CONNECTED_MODULE] mkConnectedApplication ();
51 Core core <- mkCore;
52 Reg#(int) cycle <- mkReg(0);
54 // Reg#(Bit#(32)) ac_fini <- mkReg(0);
56 //External memory
57 // I'm not comfortable assuming that the memory subsystem is in order
58 // So I'll insert a completion buffer here.
59 MEMORY_IFC#(Bit#(18), Bit#(32)) memory <- mkScratchpad(`VDEV_SCRATCH_MEMORY, SCRATCHPAD_CACHED); //Services Memory items
61 // Services Samples
62 ClientStub_AUDIOCORERRR client_stub <- mkClientStub_AUDIOCORERRR();
63 // Make this big enough so that several outstanding requests may be supported
64 FIFO#(Bit#(MainMemTagSz)) tags <- mkSizedFIFO(8);
66 //-----------------------------------------------------------
67 // Debug port
69 ServerStub_AUDIOCORERRR server_stub <- mkServerStub_AUDIOCORERRR();
72 // this is for the tracing
73 rule printCycles;
74 cycle <= cycle+1;
75 $fdisplay(stderr, " => Cycle = %d", cycle);
76 endrule
78 rule sendMemReq;
79 let coreReq <- core.mmem_client.request.get;
80 case (coreReq) matches
81 tagged LoadReq .load: begin
82 // $display("PIPE Load Addr Req %h", load.addr);
83 //Allocate ROB space
84 memory.readReq(truncate(load.addr>>2));
85 tags.enq(load.tag);
86 end
87 tagged StoreReq .store: begin
88 // $display("PIPE Write Addr Req %h", store.addr);
89 memory.write(truncate(store.addr>>2),store.data);
90 end
91 endcase
92 endrule
94 rule receiveMemResp;
95 let memResp <- memory.readRsp();
96 tags.deq;
97 core.mmem_client.response.put(tagged LoadResp {data:memResp,
98 tag: tags.first});
99 // $display("PIPE Receive MemReq %x", memResp);
100 endrule
102 rule feedOutput;
103 let pipelineData <- core.sampleOutput.get();
104 AudioProcessorControl endOfFileTag = EndOfFile;
105 AudioProcessorControl sampleTag = Data;
107 case (pipelineData) matches
108 tagged EndOfFile:
109 client_stub.makeRequest_SendProcessedStream(zeroExtend(pack(endOfFileTag)),?);
110 tagged Sample .sample:client_stub.makeRequest_SendProcessedStream(zeroExtend(pack(sampleTag)), zeroExtend(pack(sample)));
111 endcase
112 endrule
114 //***** SERVER Side *****
116 /* (* conservative_implicit_conditions *)
117 rule handleCPUToHost;
118 let req <- server_stub.acceptRequest_ReadCPUToHost();
119 case (req)
120 0: server_stub.sendResponse_ReadCPUToHost(cp0_tohost);
121 endcase
122 endrule
123 */
124 rule feedInput;
125 let command <- server_stub.acceptRequest_SendUnprocessedStream();
126 AudioProcessorControl ctrl = unpack(truncate(command.ctrl));
128 Bit#(32) test = unpack(truncate(command.channel));
129 $display("rlm: %x", test);
132 if(ctrl == EndOfFile)
133 begin
134 $display("lsp: PIPE received EOF ");
135 core.sampleInput.put(tagged EndOfFile);
136 end
137 else
138 begin
139 // $display("lsp: PIPE received Data ");
140 core.sampleInput.put(tagged Sample unpack(truncate(command.sample)));
141 end
142 endrule
143 endmodule