view modules/bluespec/Pygar/core/audioCorePipeline.bsv @ 51:9fe5ed4af92d pygar svn.52

[svn r52] tested having multiple cores
author punk
date Wed, 05 May 2010 17:01:04 -0400
parents a139cc07b773
children 49049f97312c
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1 // The MIT License
3 // Copyright (c) 2009 Massachusetts Institute of Technology
5 // Permission is hereby granted, free of charge, to any person obtaining a copy
6 // of this software and associated documentation files (the "Software"), to deal
7 // in the Software without restriction, including without limitation the rights
8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 // copies of the Software, and to permit persons to whom the Software is
10 // furnished to do so, subject to the following conditions:
12 // The above copyright notice and this permission notice shall be included in
13 // all copies or substantial portions of the Software.
15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
21 // THE SOFTWARE.
23 // Author: Kermin Fleming kfleming@mit.edu
25 import Connectable::*;
26 import GetPut::*;
27 import ClientServer::*;
28 import FIFO::*;
29 import SpecialFIFOs::*;
31 //AWB includes
32 `include "asim/provides/low_level_platform_interface.bsh"
33 `include "asim/provides/soft_connections.bsh"
34 `include "asim/provides/common_services.bsh"
36 //Local includes
37 `include "asim/provides/audio_pipe_types.bsh" //provides Audio Pipeline interface
38 `include "asim/provides/path_types.bsh"
39 `include "asim/provides/core.bsh"
40 `include "asim/provides/mixer.bsh"
41 `include "asim/provides/processor_library.bsh"
42 `include "asim/provides/fpga_components.bsh"
43 `include "asim/dict/VDEV_SCRATCH.bsh"
45 `include "asim/rrr/remote_client_stub_AUDIOCORERRR.bsh"
46 `include "asim/rrr/remote_server_stub_AUDIOCORERRR.bsh"
48 module [CONNECTED_MODULE] mkConnectedApplication ();
49 Core core <- mkCore(`VDEV_SCRATCH_MEMORYA);
50 Core anotherCore <- mkCore(`VDEV_SCRATCH_MEMORYB);
51 // RLM::
52 // the simple existance of this additional core causes the dreaded
53 // beast to emerge --- the ASSERTION FAILURE: sw/model/stats-device.cpp:317 Cycle:0
54 //stats device: Duplicate entry DATA_CACHE_NUM_WRITEBACKS, postion 0
55 //Core core1 <- mkCore;
56 Reg#(int) cycle <- mkReg(0);
58 // Reg#(Bit#(32)) ac_fini <- mkReg(0);
60 //External memory
61 // I'm not comfortable assuming that the memory subsystem is in order
62 // So I'll insert a completion buffer here.
64 // Services Samples
65 ClientStub_AUDIOCORERRR client_stub <- mkClientStub_AUDIOCORERRR();
68 //-----------------------------------------------------------
69 // Debug port
71 ServerStub_AUDIOCORERRR server_stub <- mkServerStub_AUDIOCORERRR();
74 // this is for the tracing
75 rule printCycles;
76 cycle <= cycle+1;
77 $fdisplay(stderr, " => Cycle = %d", cycle);
78 endrule
80 rule feedOutput;
81 let pipelineData <- core.sampleOutput.get();
82 AudioProcessorControl endOfFileTag = EndOfFile;
83 AudioProcessorControl sampleTag = Data;
85 case (pipelineData) matches
86 tagged EndOfFile:
87 client_stub.makeRequest_SendProcessedStream(zeroExtend(pack(endOfFileTag)),?);
88 tagged Sample .sample:client_stub.makeRequest_SendProcessedStream(zeroExtend(pack(sampleTag)), zeroExtend(pack(sample)));
89 endcase
90 endrule
92 //***** SERVER Side *****
94 /* (* conservative_implicit_conditions *)
95 rule handleCPUToHost;
96 let req <- server_stub.acceptRequest_ReadCPUToHost();
97 case (req)
98 0: server_stub.sendResponse_ReadCPUToHost(cp0_tohost);
99 endcase
100 endrule
101 */
102 rule feedInput;
103 let command <- server_stub.acceptRequest_SendUnprocessedStream();
104 AudioProcessorControl ctrl = unpack(truncate(command.ctrl));
106 Bit#(32) test = unpack(truncate(command.channel));
107 // $display("rlm: %x", test);
110 if(ctrl == EndOfFile)
111 begin
112 $display("lsp: PIPE received EOF ");
113 core.sampleInput.put(tagged EndOfFile);
114 end
115 else
116 begin
117 // $display("lsp: PIPE received Data ");
118 core.sampleInput.put(tagged Sample unpack(truncate(command.sample)));
119 end
120 endrule
121 endmodule