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diff modules/bluespec/Pygar/lab4/data_cache.awb @ 63:1d5cbb5343d2 pygar svn.64

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[svn r64] mods to compile correctly for FPGA
author punk
date Mon, 10 May 2010 22:54:54 -0400
parents 6179c07c21d7
children
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     1.1 --- a/modules/bluespec/Pygar/lab4/data_cache.awb	Mon May 10 21:00:49 2010 -0400
     1.2 +++ b/modules/bluespec/Pygar/lab4/data_cache.awb	Mon May 10 22:54:54 2010 -0400
     1.3 @@ -9,4 +9,4 @@
     1.4  %public DataCache.dic
     1.5  
     1.6  %generated -t VERILOG mkDataCache.v
     1.7 -%generated -t BA mkDataCache.ba
     1.8 \ No newline at end of file
     1.9 +%generated -t BA mkDataCache.ba