Mercurial > pygar
diff modules/bluespec/Pygar/lab4/BRegFile.bsv @ 63:1d5cbb5343d2 pygar svn.64
[svn r64] mods to compile correctly for FPGA
| author | punk |
|---|---|
| date | Mon, 10 May 2010 22:54:54 -0400 |
| parents | 90fa9b289aab |
| children |
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1.1 --- a/modules/bluespec/Pygar/lab4/BRegFile.bsv Mon May 10 21:00:49 2010 -0400 1.2 +++ b/modules/bluespec/Pygar/lab4/BRegFile.bsv Mon May 10 22:54:54 2010 -0400 1.3 @@ -11,29 +11,25 @@ 1.4 // Register file module 1.5 //----------------------------------------------------------- 1.6 1.7 -interface BRFile; 1.8 +interface BRegFile; 1.9 method Action wr( Rindx rindx, Bit#(32) data ); 1.10 - method Action Value Bit#(32) rd1( Rindx rindx ); 1.11 - method Action Value Bit#(32) rd2( Rindx rindx ); 1.12 + method ActionValue#( Bit#(32)) rd1( Rindx rindx ); 1.13 + method ActionValue#( Bit#(32)) rd2( Rindx rindx ); 1.14 endinterface 1.15 1.16 (* doc = "synthesis attribute ram_style mkBRegFile distributed;" *) 1.17 (* synthesize *) 1.18 -module mkBRegFile(BRFile) 1.19 - provisos (Bits#(index_t, size_index), 1.20 - Bits#(data_t, size_data), 1.21 - Eq#(index_t), 1.22 - Bounded#(index_t) ); 1.23 +module mkBRegFile(BRegFile); 1.24 1.25 - LUTRAM#(index_t, data_t) rf <- mkLUTRAMU_RegFile(); 1.26 - RWire#(Tuple2#(index_t, data_t)) rw <-mkRWire(); 1.27 + LUTRAM#(Rindx, Bit#(32)) rf <- mkLUTRAMU_RegFile(); 1.28 + RWire#(Tuple2#(Rindx, Bit#(32))) rw <-mkRWire(); 1.29 1.30 method Action wr( Rindx rindx, Bit#(32) data ); 1.31 rf.upd( rindx, data ); 1.32 - rw.wset(tuple2(rindex,data)); 1.33 + rw.wset(tuple2(rindx,data)); 1.34 endmethod 1.35 1.36 - method Bit#(32) rd1 (Rindx r); 1.37 + method ActionValue#(Bit#(32)) rd1 (Rindx r); 1.38 if (r == 0) return 0; 1.39 else begin 1.40 case (rw.wget()) matches 1.41 @@ -44,7 +40,7 @@ 1.42 end 1.43 endmethod 1.44 1.45 - method Bit#(32) rd2 (Rindx r); 1.46 + method ActionValue#(Bit#(32)) rd2 (Rindx r); 1.47 if (r == 0) return 0; 1.48 else begin 1.49 case (rw.wget()) matches