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comparison modules/bluespec/Pygar/lab4/BRegFile.bsv @ 63:1d5cbb5343d2 pygar svn.64

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[svn r64] mods to compile correctly for FPGA
author punk
date Mon, 10 May 2010 22:54:54 -0400
parents 90fa9b289aab
children
comparison
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62:90fa9b289aab 63:1d5cbb5343d2
9 9
10 //----------------------------------------------------------- 10 //-----------------------------------------------------------
11 // Register file module 11 // Register file module
12 //----------------------------------------------------------- 12 //-----------------------------------------------------------
13 13
14 interface BRFile; 14 interface BRegFile;
15 method Action wr( Rindx rindx, Bit#(32) data ); 15 method Action wr( Rindx rindx, Bit#(32) data );
16 method Action Value Bit#(32) rd1( Rindx rindx ); 16 method ActionValue#( Bit#(32)) rd1( Rindx rindx );
17 method Action Value Bit#(32) rd2( Rindx rindx ); 17 method ActionValue#( Bit#(32)) rd2( Rindx rindx );
18 endinterface 18 endinterface
19 19
20 (* doc = "synthesis attribute ram_style mkBRegFile distributed;" *) 20 (* doc = "synthesis attribute ram_style mkBRegFile distributed;" *)
21 (* synthesize *) 21 (* synthesize *)
22 module mkBRegFile(BRFile) 22 module mkBRegFile(BRegFile);
23 provisos (Bits#(index_t, size_index),
24 Bits#(data_t, size_data),
25 Eq#(index_t),
26 Bounded#(index_t) );
27 23
28 LUTRAM#(index_t, data_t) rf <- mkLUTRAMU_RegFile(); 24 LUTRAM#(Rindx, Bit#(32)) rf <- mkLUTRAMU_RegFile();
29 RWire#(Tuple2#(index_t, data_t)) rw <-mkRWire(); 25 RWire#(Tuple2#(Rindx, Bit#(32))) rw <-mkRWire();
30 26
31 method Action wr( Rindx rindx, Bit#(32) data ); 27 method Action wr( Rindx rindx, Bit#(32) data );
32 rf.upd( rindx, data ); 28 rf.upd( rindx, data );
33 rw.wset(tuple2(rindex,data)); 29 rw.wset(tuple2(rindx,data));
34 endmethod 30 endmethod
35 31
36 method Bit#(32) rd1 (Rindx r); 32 method ActionValue#(Bit#(32)) rd1 (Rindx r);
37 if (r == 0) return 0; 33 if (r == 0) return 0;
38 else begin 34 else begin
39 case (rw.wget()) matches 35 case (rw.wget()) matches
40 tagged Valid {.wr, .d} : 36 tagged Valid {.wr, .d} :
41 return (wr == r) ? d : rf.sub(r); 37 return (wr == r) ? d : rf.sub(r);
42 tagged Invalid : return rf.sub(r); 38 tagged Invalid : return rf.sub(r);
43 endcase 39 endcase
44 end 40 end
45 endmethod 41 endmethod
46 42
47 method Bit#(32) rd2 (Rindx r); 43 method ActionValue#(Bit#(32)) rd2 (Rindx r);
48 if (r == 0) return 0; 44 if (r == 0) return 0;
49 else begin 45 else begin
50 case (rw.wget()) matches 46 case (rw.wget()) matches
51 tagged Valid {.wr, .d} : 47 tagged Valid {.wr, .d} :
52 return (wr == r) ? d : rf.sub(r); 48 return (wr == r) ? d : rf.sub(r);