pygar: modules/bluespec/Pygar/core/Processor.bsv comparison

comparison modules/bluespec/Pygar/core/Processor.bsv @ 63:1d5cbb5343d2 pygar svn.64

[svn r64] mods to compile correctly for FPGA

author	punk
date	Mon, 10 May 2010 22:54:54 -0400
parents	2991344775f8
children	cf8bb3038cbd

comparison

equal deleted inserted replaced

-:90fa9b289aab
+:1d5cbb5343d2
 interface Put#(AudioProcessorUnit) sampleInput;
 endinterface
 typedef enum { PCgen, Exec, Writeback } Stage deriving(Eq,Bits);
-//-----------------------------------------------------------
-// Register file module
-//-----------------------------------------------------------
-interface BRFile;
-method Action   wr( Rindx rindx, Bit#(32) data );
-method Bit#(32) rd1( Rindx rindx );
-method Bit#(32) rd2( Rindx rindx );
-endinterface
-module mkBRFile( BRFile );
-RegFile#(Rindx,Bit#(32)) rfile <- mkBRegFile();
-method Action wr( Rindx rindx, Bit#(32) data );
-rfile.upd( rindx, data );
-endmethod
-method Bit#(32) rd1( Rindx rindx );
-return ( rindx == 0 ) ? 0 : rfile.sub(rindx);
-endmethod
-method Bit#(32) rd2( Rindx rindx );
-return ( rindx == 0 ) ? 0 : rfile.sub(rindx);
-endmethod
-endmodule
 //-----------------------------------------------------------
 // Helper functions
 //-----------------------------------------------------------
 // Standard processor state
 Reg#(Addr)  pc    <- mkReg(32'h00001000);
 Reg#(Epoch) epoch <- mkReg(0);
 Reg#(Stage) stage <- mkReg(PCgen);
-BRFile      rf    <- mkBRFile;
+BRegFile      rf  <- mkBRegFile;
 // Branch Prediction
 BranchPred               bp <- mkBranchPred();
 FIFO#(PCStat)        execpc <- mkLFIFO();
 	 // -- Memory Ops ------------------------------------------------
 	 tagged LW .it :
 	    begin
-Addr addr = rf.rd1(it.rbase) + sext(it.offset);
+	       let val_rbase <- rf.rd1(it.rbase);
+Addr addr = val_rbase + sext(it.offset);
 dataReqQ.enq( LoadReq{ addr:addr, tag:zeroExtend(it.rdst) } );
 wbQ.enq(tagged WB_Load it.rdst);
 	    end
 	 tagged SW .it :
 	    begin
-Addr addr = rf.rd1(it.rbase) + sext(it.offset);
+	       let val_rbase <- rf.rd1(it.rbase);
-dataReqQ.enq( StoreReq{ tag:0, addr:addr, data:rf.rd2(it.rsrc) } );
+	       let val_rsrc2 <- rf.rd2(it.rsrc);
+Addr addr = val_rbase + sext(it.offset);
+dataReqQ.enq( StoreReq{ tag:0, addr:addr, data:val_rsrc2 } );
 wbQ.enq(tagged WB_Store);
 	    end
 	 // -- Simple Ops ------------------------------------------------
 	 tagged ADDIU .it :
 	    begin
-	       Bit#(32) result = rf.rd1(it.rsrc) + sext(it.imm);
+	       let val_rsrc1 <- rf.rd1(it.rsrc);
+	       Bit#(32) result = val_rsrc1 + sext(it.imm);
 	       wbQ.enq(tagged WB_ALU {data:result, dest:it.rdst});
 	    end
-	 tagged SLTI  .it : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:slt( rf.rd1(it.rsrc), sext(it.imm) )});
+	 tagged SLTI  .it :
-	 tagged SLTIU .it : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:sltu( rf.rd1(it.rsrc), sext(it.imm) ) });
+	    begin
+	       let val_rsrc1 <- rf.rd1(it.rsrc);
+	       wbQ.enq(tagged WB_ALU {dest:it.rdst, data:slt( val_rsrc1, sext(it.imm) )});
+	    end
+	 tagged SLTIU .it :
+	    begin
+	       let val_rsrc1 <- rf.rd1(it.rsrc);
+	       wbQ.enq(tagged WB_ALU {dest:it.rdst, data:sltu( val_rsrc1, sext(it.imm) ) });
+	    end
 	 tagged ANDI  .it :
 	    begin
+	       let val_rsrc1 <- rf.rd1(it.rsrc);
 	       Bit#(32) zext_it_imm = zext(it.imm);
-	       wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(rf.rd1(it.rsrc) & zext_it_imm)} );
+	       wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(val_rsrc1 & zext_it_imm)} );
 	    end
 	 tagged ORI   .it :
 	    begin
+	       let val_rsrc1 <- rf.rd1(it.rsrc);
 	       Bit#(32) zext_it_imm = zext(it.imm);
-	       wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(rf.rd1(it.rsrc) | zext_it_imm)} );
+	       wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(val_rsrc1 | zext_it_imm)} );
 	    end
 	 tagged XORI  .it :
 	    begin
+	       let val_rsrc1 <- rf.rd1(it.rsrc);
 	       Bit#(32) zext_it_imm = zext(it.imm);
-	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) ^ zext_it_imm )});
+	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc1 ^ zext_it_imm )});
 	    end
 	 tagged LUI   .it :
 	    begin
 	       Bit#(32) zext_it_imm = zext(it.imm);
 	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(zext_it_imm << 32'd16) });
 	    end
 	 tagged SLL   .it :
 	    begin
+	       let val_rsrc1 <- rf.rd1(it.rsrc);
 	       Bit#(32) zext_it_shamt = zext(it.shamt);
-	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) << zext_it_shamt )} );
+	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc1 << zext_it_shamt )} );
 	    end
 	 tagged SRL   .it :
 	    begin
+	       let val_rsrc1 <- rf.rd1(it.rsrc);
 	       Bit#(32) zext_it_shamt = zext(it.shamt);
-	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) >> zext_it_shamt )});
+	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc1 >> zext_it_shamt )});
 	    end
 	 tagged SRA   .it :
 	    begin
+	       let val_rsrc1 <- rf.rd1(it.rsrc);
 	       Bit#(32) zext_it_shamt = zext(it.shamt);
-	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( rf.rd1(it.rsrc), zext_it_shamt )});
+	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( val_rsrc1, zext_it_shamt )});
 	    end
-	 tagged SLLV  .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) << rshft(rf.rd2(it.rshamt)) )});
+	 tagged SLLV  .it :
-	 tagged SRLV  .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) >> rshft(rf.rd2(it.rshamt)) )} );
+	    begin
-	 tagged SRAV  .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( rf.rd1(it.rsrc), rshft(rf.rd2(it.rshamt)) ) });
+	       let val_rsrc1 <- rf.rd1(it.rsrc);
-	 tagged ADDU  .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) + rf.rd2(it.rsrc2) )} );
+	       let val_rshamt <- rf.rd2(it.rshamt);
-	 tagged SUBU  .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) - rf.rd2(it.rsrc2) )} );
+	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc1 << rshft(val_rshamt) )});
-	 tagged AND   .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) & rf.rd2(it.rsrc2) )} );
+	    end
-	 tagged OR    .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) | rf.rd2(it.rsrc2) )} );
+	 tagged SRLV  .it :
-	 tagged XOR   .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) ^ rf.rd2(it.rsrc2) )} );
+	    begin
-	 tagged NOR   .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(~(rf.rd1(it.rsrc1) | rf.rd2(it.rsrc2)) )} );
+	       let val_rsrc1 <- rf.rd1(it.rsrc);
-	 tagged SLT   .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:slt( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) });
+	       let val_rshamt <- rf.rd2(it.rshamt);
-	 tagged SLTU  .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sltu( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) });
+	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc1 >> rshft(val_rshamt) )} );
+	    end
+	 tagged SRAV  .it :
+	    begin
+	       let val_rsrc1 <- rf.rd1(it.rsrc);
+	       let val_rshamt <- rf.rd2(it.rshamt);
+	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( val_rsrc1, rshft(val_rshamt) ) });
+	    end
+	 tagged ADDU  .it :
+	    begin
+	       let val_rsrc11 <- rf.rd1(it.rsrc1);
+	       let val_rsrc22 <- rf.rd2(it.rsrc2);
+	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc11 + val_rsrc22 )} );
+	    end
+	 tagged SUBU  .it :
+	    begin
+	       let val_rsrc11 <- rf.rd1(it.rsrc1);
+	       let val_rsrc22 <- rf.rd2(it.rsrc2);
+	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc11 - val_rsrc22 )} );
+	    end
+	 tagged AND   .it :
+	    begin
+	       let val_rsrc11 <- rf.rd1(it.rsrc1);
+	       let val_rsrc22 <- rf.rd2(it.rsrc2);
+	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc11 & val_rsrc22 )} );
+	    end
+	 tagged OR    .it :
+	    begin
+	       let val_rsrc11 <- rf.rd1(it.rsrc1);
+	       let val_rsrc22 <- rf.rd2(it.rsrc2);
+	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc11 | val_rsrc22 )} );
+	    end
+	 tagged XOR   .it :
+	    begin
+	       let val_rsrc11 <- rf.rd1(it.rsrc1);
+	       let val_rsrc22 <- rf.rd2(it.rsrc2);
+	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc11 ^ val_rsrc22 )} );
+	    end
+	 tagged NOR   .it :
+	    begin
+	       let val_rsrc11 <- rf.rd1(it.rsrc1);
+	       let val_rsrc22 <- rf.rd2(it.rsrc2);
+	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(~(val_rsrc11 | val_rsrc22) )} );
+	    end
+	 tagged SLT   .it :
+	    begin
+	       let val_rsrc11 <- rf.rd1(it.rsrc1);
+	       let val_rsrc22 <- rf.rd2(it.rsrc2);
+	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:slt( val_rsrc11, val_rsrc22 ) });
+	    end
+	 tagged SLTU  .it :
+	    begin
+	       let val_rsrc11 <- rf.rd1(it.rsrc1);
+	       let val_rsrc22 <- rf.rd2(it.rsrc2);
+	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sltu( val_rsrc11, val_rsrc22 ) });
+	    end
 	 // -- Branches --------------------------------------------------
 	 tagged BLEZ  .it :
-if ( signedLE( rf.rd1(it.rsrc), 0 ) )
+	    begin
-	       begin
+	       let val_rsrc1 <- rf.rd1(it.rsrc);
+	         if ( signedLE( val_rsrc1, 0 ) )
+	       	 begin
 		  newPC = pc_plus4 + (sext(it.offset) << 2);
 		  branchTaken = True;
-	       end
+	       	 end
+	    end
 	 tagged BGTZ  .it :
-if ( signedGT( rf.rd1(it.rsrc), 0 ) )
+	    begin
+	       let val_rsrc1 <- rf.rd1(it.rsrc);
+if ( signedGT( val_rsrc1, 0 ) )
 begin
 		  newPC = pc_plus4 + (sext(it.offset) << 2);
 		  branchTaken = True;
 	       end
+	    end
 	 tagged BLTZ  .it :
-if ( signedLT( rf.rd1(it.rsrc), 0 ) )
+	    begin
+	       let val_rsrc1 <- rf.rd1(it.rsrc);
+if ( signedLT( val_rsrc1, 0 ) )
 begin
 		  newPC = pc_plus4 + (sext(it.offset) << 2);
 		  branchTaken = True;
 	       end
+	    end
 	 tagged BGEZ  .it :
-if ( signedGE( rf.rd1(it.rsrc), 0 ) )
+	    begin
-begin
+	       let val_rsrc1 <- rf.rd1(it.rsrc);
-		  newPC = pc_plus4 + (sext(it.offset) << 2);
+if ( signedGE( val_rsrc1, 0 ) )
-		  branchTaken = True;
+	 begin
-	       end
+		        newPC = pc_plus4 + (sext(it.offset) << 2);
+		  	branchTaken = True;
+	         end
+	    end
 tagged BEQ   .it :
-if ( rf.rd1(it.rsrc1) == rf.rd2(it.rsrc2) )
+begin
+	  let val_rsrc11 <- rf.rd1(it.rsrc1);
+	  let val_rsrc22 <- rf.rd2(it.rsrc2);
+if ( val_rsrc11 == val_rsrc22 )
 begin
 	     newPC = pc_plus4 + (sext(it.offset) << 2);
 	     branchTaken = True;
 	  end
+	end
 tagged BNE   .it :
-if ( rf.rd1(it.rsrc1) != rf.rd2(it.rsrc2) )
+begin
+	  let val_rsrc11 <- rf.rd1(it.rsrc1);
+	  let val_rsrc22 <- rf.rd2(it.rsrc2);
+if ( val_rsrc11 != val_rsrc22 )
 begin
 	     newPC = pc_plus4 + (sext(it.offset) << 2);
 	     branchTaken = True;
 	  end
+	end
 // -- Jumps -----------------------------------------------------
 tagged J     .it :
 begin
 	   newPC = { pc_plus4[31:28], it.target, 2'b0 };
 	   branchTaken = True;
 	end
 tagged JR    .it :
 begin
-	   newPC = rf.rd1(it.rsrc);
+	   let val_rsrc1 <- rf.rd1(it.rsrc);
+	   newPC = val_rsrc1;
 	   branchTaken = True;
 	end
 tagged JAL   .it :
 begin
 	  branchTaken = True;
 end
 tagged JALR  .it :
 begin
+	  let val_rsrc1 <- rf.rd1(it.rsrc);
 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:pc_plus4 });
-newPC = rf.rd1(it.rsrc);
+newPC = val_rsrc1;
 	  branchTaken = True;
 end
 // -- Cop0 ------------------------------------------------------
 tagged MTC0  .it : //Recieve things from host computer
 	 begin
+	  let val_rsrc1 <- rf.rd1(it.rsrc);
 //	    $display( " PROCESSOR MTC0 call\n");
 case ( it.cop0dst )
-	       5'd10 : cp0_statsEn <= unpack(truncate(rf.rd1(it.rsrc)));
+	       5'd10 : cp0_statsEn <= unpack(truncate(val_rsrc1));
-	       5'd21 : cp0_tohost  <= truncate(rf.rd1(it.rsrc));
+	       5'd21 : cp0_tohost  <= truncate(val_rsrc1);
-	       5'd26 : cp0_progComp <= unpack(truncate(rf.rd1(it.rsrc))); //states audio program completed and termination okay
+	       5'd26 : cp0_progComp <= unpack(truncate(val_rsrc1)); //states audio program completed and termination okay
-	       5'd27 : outAudioFifo.enq(tagged Sample unpack(truncate(rf.rd1(it.rsrc))));  //Bit size is 16 not 32
+	       5'd27 : outAudioFifo.enq(tagged Sample unpack(truncate(val_rsrc1)));  //Bit size is 16 not 32
 	       default :
 	       $display( " RTL-ERROR : %m : Illegal MTC0 cop0dst register!" );
 	    endcase
 	    wbQ.enq(tagged WB_Host 0); //no idea wwhat this actually should be.
 	 end

Mercurial > pygar

comparison modules/bluespec/Pygar/core/Processor.bsv @ 63:1d5cbb5343d2 pygar svn.64