view modules/bluespec/Pygar/core/Processor.bsv @ 65:cf8bb3038cbd pygar svn.66

[svn r66] sim passes
author punk
date Tue, 11 May 2010 09:05:22 -0400
parents 1d5cbb5343d2
children 44cc00df1168
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1 // The MIT License
3 // Copyright (c) 2009 Massachusetts Institute of Technology
5 // Permission is hereby granted, free of charge, to any person obtaining a copy
6 // of this software and associated documentation files (the "Software"), to deal
7 // in the Software without restriction, including without limitation the rights
8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 // copies of the Software, and to permit persons to whom the Software is
10 // furnished to do so, subject to the following conditions:
12 // The above copyright notice and this permission notice shall be included in
13 // all copies or substantial portions of the Software.
15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
21 // THE SOFTWARE.
24 import Connectable::*;
25 import GetPut::*;
26 import ClientServer::*;
27 import RegFile::*;
29 import FIFO::*;
30 import FIFOF::*;
31 import SFIFO::*;
32 import RWire::*;
34 import Trace::*;
35 import BFIFO::*;
36 import MemTypes::*;
37 import ProcTypes::*;
38 import BRegFile::*;
39 import BranchPred::*;
40 //import PathTypes::*; This is only there to force the debugging
42 //AWB includes
43 `include "asim/provides/low_level_platform_interface.bsh"
44 `include "asim/provides/soft_connections.bsh"
45 `include "asim/provides/common_services.bsh"
47 // Local includes
48 //`include "asim/provides/processor_library.bsh" (included above directly)
50 `include "asim/provides/common_services.bsh"
51 `include "asim/provides/processor_library.bsh"
53 // Local includes. Look for the correspondingly named .awb files
54 // workspace/labs/src/mit-6.375/modules/bluespec/mit-6.375/common/
55 // to find the actual Bluespec files which are used to generate
56 // these includes. These files are specific to this audio processing
57 // pipeline
59 `include "asim/provides/audio_pipe_types.bsh"
61 //interface CPUToHost;
62 // method Bit#(32) cpuToHost(int req);
63 //endinterface
65 interface Proc;
67 // Interface from processor to caches
68 interface Client#(DataReq,DataResp) dmem_client;
69 interface Client#(InstReq,InstResp) imem_client;
71 // Interface for enabling/disabling statistics on the rest of the core
72 interface Get#(Bool) statsEn_get;
74 // // Interface to host
75 // interface CPUToHost tohost;
77 // Interface to Audio Pipeline
78 interface Get#(AudioProcessorUnit) sampleOutput;
79 interface Put#(AudioProcessorUnit) sampleInput;
81 endinterface
83 typedef enum { PCgen, Exec, Writeback } Stage deriving(Eq,Bits);
85 //-----------------------------------------------------------
86 // Helper functions
87 //-----------------------------------------------------------
89 function Bit#(32) slt( Bit#(32) val1, Bit#(32) val2 );
90 return zeroExtend( pack( signedLT(val1,val2) ) );
91 endfunction
93 function Bit#(32) sltu( Bit#(32) val1, Bit#(32) val2 );
94 return zeroExtend( pack( val1 < val2 ) );
95 endfunction
97 function Bit#(32) rshft( Bit#(32) val );
98 return zeroExtend(val[4:0]);
99 endfunction
102 //-----------------------------------------------------------
103 // Find funct for wbQ
104 //-----------------------------------------------------------
105 function Bool findwbf(Rindx fVal, WBResult cmpVal);
106 case (cmpVal) matches
107 tagged WB_ALU {data:.res, dest:.rd} :
108 return (fVal == rd);
109 tagged WB_Load .rd :
110 return (fVal == rd);
111 tagged WB_Store .st :
112 return False;
113 tagged WB_Host .x :
114 return False;
115 endcase
116 endfunction
119 //-----------------------------------------------------------
120 // Stall funct for wbQ
121 //-----------------------------------------------------------
122 function Bool stall(Instr inst, SFIFO#(WBResult, Rindx) f);
123 case (inst) matches
124 // -- Memory Ops ------------------------------------------------
125 tagged LW .it :
126 return f.find(it.rbase);
127 tagged SW {rsrc:.dreg, rbase:.addr, offset:.o} :
128 return (f.find(addr) || f.find2(dreg));
130 // -- Simple Ops ------------------------------------------------
131 tagged ADDIU .it : return f.find(it.rsrc);
132 tagged SLTI .it : return f.find(it.rsrc);
133 tagged SLTIU .it : return f.find(it.rsrc);
134 tagged ANDI .it : return f.find(it.rsrc);
135 tagged ORI .it : return f.find(it.rsrc);
136 tagged XORI .it : return f.find(it.rsrc);
138 tagged LUI .it : return f.find(it.rdst); //this rds/wrs itself
139 tagged SLL .it : return f.find(it.rsrc);
140 tagged SRL .it : return f.find(it.rsrc);
141 tagged SRA .it : return f.find(it.rsrc);
142 tagged SLLV .it : return (f.find(it.rsrc) || f.find(it.rshamt));
143 tagged SRLV .it : return (f.find(it.rsrc) || f.find(it.rshamt));
144 tagged SRAV .it : return (f.find(it.rsrc) || f.find(it.rshamt));
145 tagged ADDU .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
146 tagged SUBU .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
147 tagged AND .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
148 tagged OR .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
149 tagged XOR .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
150 tagged NOR .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
151 tagged SLT .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
152 tagged SLTU .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
155 // -- Branches --------------------------------------------------
157 tagged BLEZ .it : return (f.find(it.rsrc));
158 tagged BGTZ .it : return (f.find(it.rsrc));
159 tagged BLTZ .it : return (f.find(it.rsrc));
160 tagged BGEZ .it : return (f.find(it.rsrc));
161 tagged BEQ .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
162 tagged BNE .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
164 // -- Jumps -----------------------------------------------------
166 tagged J .it : return False;
167 tagged JR .it : return f.find(it.rsrc);
168 tagged JALR .it : return f.find(it.rsrc);
169 tagged JAL .it : return False;
171 // -- Cop0 ------------------------------------------------------
173 tagged MTC0 .it : return f.find(it.rsrc);
174 tagged MFC0 .it : return False;
176 // -- Illegal ---------------------------------------------------
178 default : return False;
180 endcase
181 endfunction
182 //-----------------------------------------------------------
183 // Reference processor
184 //-----------------------------------------------------------
187 //(* doc = "synthesis attribute ram_style mkProc distributed;" *)
188 //(* synthesize *)
190 module mkProc( Proc );
192 //-----------------------------------------------------------
193 // State
195 // Standard processor state
197 Reg#(Addr) pc <- mkReg(32'h00001000);
198 Reg#(Epoch) epoch <- mkReg(0);
199 Reg#(Stage) stage <- mkReg(PCgen);
200 BRegFile rf <- mkBRegFile;
202 // Branch Prediction
203 BranchPred bp <- mkBranchPred();
204 FIFO#(PCStat) execpc <- mkLFIFO();
206 // Pipelines
207 FIFO#(PCStat) pcQ <-mkSizedFIFO(3);
208 SFIFO#(WBResult, Rindx) wbQ <-mkSFIFO(findwbf);
210 // NEED TO ADD CAPABILITY FOR RESET (should be able to just say if I get valid in and these are flagged, clear them.
211 Reg#(Bit#(32)) cp0_tohost <- mkReg(0);
212 Reg#(Bit#(32)) cp0_fromhost <- mkReg(0);
213 Reg#(Bool) cp0_statsEn <- mkReg(False);
214 Reg#(Bool) cp0_audioEOF <- mkReg(False); // Register to let code that EOF is reached
215 Reg#(Bool) cp0_progComp <- mkReg(False); // Register to let processor know that the program is complete (as this terminates)
217 // Memory request/response state
219 FIFO#(InstReq) instReqQ <- mkBFIFO1();
220 FIFO#(InstResp) instRespQ <- mkFIFO();
222 FIFO#(DataReq) dataReqQ <- mkBFIFO1();
223 FIFO#(DataResp) dataRespQ <- mkFIFO();
225 // Audio I/O
226 FIFO#(AudioProcessorUnit) inAudioFifo <- mkSizedFIFO(512);
227 FIFO#(AudioProcessorUnit) outAudioFifo <- mkFIFO;
230 // Statistics state (2010)
231 // Reg#(Stat) num_cycles <- mkReg(0);
232 // Reg#(Stat) num_inst <- mkReg(0);
234 //Or:
235 // Statistics state
237 //rlm: removing these to avoid their broken stupidness.
238 //STAT num_cycles <- mkStatCounter(`STATS_PROCESSOR_CYCLE_COUNT);
239 //STAT num_inst <- mkStatCounter(`STATS_PROCESSOR_INST_COUNT);
241 //-----------------------------------------------------------
242 // Rules
244 (* descending_urgency = "exec, pcgen" *)
245 rule pcgen; //( stage == PCgen );
246 let pc_plus4 = pc + 4;
248 traceTiny("mkProc", "pc",pc);
249 traceTiny("mkProc", "pcgen","P");
250 instReqQ.enq( LoadReq{ addr:pc, tag:epoch} );
252 let next_pc = bp.get(pc);
253 if (next_pc matches tagged Valid .npc)
254 begin
255 pcQ.enq(PCStat {qpc:pc, qnxtpc:npc, qepoch:epoch});
256 pc <= npc;
257 end
258 else
259 begin
260 pcQ.enq(PCStat {qpc:pc, qnxtpc:pc_plus4, qepoch:epoch});
261 pc <= pc_plus4;
262 end
264 endrule
266 rule discard (instRespQ.first() matches tagged LoadResp .ld
267 &&& ld.tag != epoch);
268 traceTiny("mkProc", "stage", "D");
269 instRespQ.deq();
270 endrule
272 (* conflict_free = "exec, writeback" *)
273 rule exec (instRespQ.first() matches tagged LoadResp.ld
274 &&& (ld.tag == epoch)
275 &&& unpack(ld.data) matches .inst
276 &&& !stall(inst, wbQ));
278 // Some abbreviations
279 let sext = signExtend;
280 let zext = zeroExtend;
281 let sra = signedShiftRight;
283 // Get the instruction
285 instRespQ.deq();
286 Instr inst
287 = case ( instRespQ.first() ) matches
288 tagged LoadResp .ld : return unpack(ld.data);
289 tagged StoreResp .st : return ?;
290 endcase;
292 // Get the PC info
293 let instrpc = pcQ.first().qpc;
294 let pc_plus4 = instrpc + 4;
296 Bool branchTaken = False;
297 Addr newPC = pc_plus4;
299 // Tracing
300 traceTiny("mkProc", "exec","X");
301 traceTiny("mkProc", "exInstTiny",inst);
302 traceFull("mkProc", "exInstFull",inst);
304 case ( inst ) matches
306 // -- Memory Ops ------------------------------------------------
308 tagged LW .it :
309 begin
310 let val_rbase <- rf.rd1(it.rbase);
311 Addr addr = val_rbase + sext(it.offset);
312 dataReqQ.enq( LoadReq{ addr:addr, tag:zeroExtend(it.rdst) } );
313 wbQ.enq(tagged WB_Load it.rdst);
314 end
316 tagged SW .it :
317 begin
318 let val_rbase <- rf.rd1(it.rbase);
319 let val_rsrc2 <- rf.rd2(it.rsrc);
320 Addr addr = val_rbase + sext(it.offset);
321 dataReqQ.enq( StoreReq{ tag:0, addr:addr, data:val_rsrc2 } );
322 wbQ.enq(tagged WB_Store);
323 end
325 // -- Simple Ops ------------------------------------------------
327 tagged ADDIU .it :
328 begin
329 let val_rsrc1 <- rf.rd1(it.rsrc);
330 Bit#(32) result = val_rsrc1 + sext(it.imm);
331 wbQ.enq(tagged WB_ALU {data:result, dest:it.rdst});
332 end
333 tagged SLTI .it :
334 begin
335 let val_rsrc1 <- rf.rd1(it.rsrc);
336 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:slt( val_rsrc1, sext(it.imm) )});
337 end
338 tagged SLTIU .it :
339 begin
340 let val_rsrc1 <- rf.rd1(it.rsrc);
341 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:sltu( val_rsrc1, sext(it.imm) ) });
342 end
343 tagged ANDI .it :
344 begin
345 let val_rsrc1 <- rf.rd1(it.rsrc);
346 Bit#(32) zext_it_imm = zext(it.imm);
347 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(val_rsrc1 & zext_it_imm)} );
348 end
349 tagged ORI .it :
350 begin
351 let val_rsrc1 <- rf.rd1(it.rsrc);
352 Bit#(32) zext_it_imm = zext(it.imm);
353 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(val_rsrc1 | zext_it_imm)} );
354 end
355 tagged XORI .it :
356 begin
357 let val_rsrc1 <- rf.rd1(it.rsrc);
358 Bit#(32) zext_it_imm = zext(it.imm);
359 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc1 ^ zext_it_imm )});
360 end
361 tagged LUI .it :
362 begin
363 Bit#(32) zext_it_imm = zext(it.imm);
364 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(zext_it_imm << 32'd16) });
365 end
367 tagged SLL .it :
368 begin
369 let val_rsrc1 <- rf.rd1(it.rsrc);
370 Bit#(32) zext_it_shamt = zext(it.shamt);
371 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc1 << zext_it_shamt )} );
372 end
373 tagged SRL .it :
374 begin
375 let val_rsrc1 <- rf.rd1(it.rsrc);
376 Bit#(32) zext_it_shamt = zext(it.shamt);
377 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc1 >> zext_it_shamt )});
378 end
379 tagged SRA .it :
380 begin
381 let val_rsrc1 <- rf.rd1(it.rsrc);
382 Bit#(32) zext_it_shamt = zext(it.shamt);
383 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( val_rsrc1, zext_it_shamt )});
384 end
385 tagged SLLV .it :
386 begin
387 let val_rsrc1 <- rf.rd1(it.rsrc);
388 let val_rshamt <- rf.rd2(it.rshamt);
389 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc1 << rshft(val_rshamt) )});
390 end
391 tagged SRLV .it :
392 begin
393 let val_rsrc1 <- rf.rd1(it.rsrc);
394 let val_rshamt <- rf.rd2(it.rshamt);
395 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc1 >> rshft(val_rshamt) )} );
396 end
397 tagged SRAV .it :
398 begin
399 let val_rsrc1 <- rf.rd1(it.rsrc);
400 let val_rshamt <- rf.rd2(it.rshamt);
401 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( val_rsrc1, rshft(val_rshamt) ) });
402 end
403 tagged ADDU .it :
404 begin
405 let val_rsrc11 <- rf.rd1(it.rsrc1);
406 let val_rsrc22 <- rf.rd2(it.rsrc2);
407 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc11 + val_rsrc22 )} );
408 end
409 tagged SUBU .it :
410 begin
411 let val_rsrc11 <- rf.rd1(it.rsrc1);
412 let val_rsrc22 <- rf.rd2(it.rsrc2);
413 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc11 - val_rsrc22 )} );
414 end
415 tagged AND .it :
416 begin
417 let val_rsrc11 <- rf.rd1(it.rsrc1);
418 let val_rsrc22 <- rf.rd2(it.rsrc2);
419 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc11 & val_rsrc22 )} );
420 end
421 tagged OR .it :
422 begin
423 let val_rsrc11 <- rf.rd1(it.rsrc1);
424 let val_rsrc22 <- rf.rd2(it.rsrc2);
425 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc11 | val_rsrc22 )} );
426 end
427 tagged XOR .it :
428 begin
429 let val_rsrc11 <- rf.rd1(it.rsrc1);
430 let val_rsrc22 <- rf.rd2(it.rsrc2);
431 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc11 ^ val_rsrc22 )} );
432 end
433 tagged NOR .it :
434 begin
435 let val_rsrc11 <- rf.rd1(it.rsrc1);
436 let val_rsrc22 <- rf.rd2(it.rsrc2);
437 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(~(val_rsrc11 | val_rsrc22) )} );
438 end
439 tagged SLT .it :
440 begin
441 let val_rsrc11 <- rf.rd1(it.rsrc1);
442 let val_rsrc22 <- rf.rd2(it.rsrc2);
443 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:slt( val_rsrc11, val_rsrc22 ) });
444 end
445 tagged SLTU .it :
446 begin
447 let val_rsrc11 <- rf.rd1(it.rsrc1);
448 let val_rsrc22 <- rf.rd2(it.rsrc2);
449 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sltu( val_rsrc11, val_rsrc22 ) });
450 end
452 // -- Branches --------------------------------------------------
454 tagged BLEZ .it :
455 begin
456 let val_rsrc1 <- rf.rd1(it.rsrc);
457 if ( signedLE( val_rsrc1, 0 ) )
458 begin
459 newPC = pc_plus4 + (sext(it.offset) << 2);
460 branchTaken = True;
461 end
462 end
464 tagged BGTZ .it :
465 begin
466 let val_rsrc1 <- rf.rd1(it.rsrc);
467 if ( signedGT( val_rsrc1, 0 ) )
468 begin
469 newPC = pc_plus4 + (sext(it.offset) << 2);
470 branchTaken = True;
471 end
472 end
474 tagged BLTZ .it :
475 begin
476 let val_rsrc1 <- rf.rd1(it.rsrc);
477 if ( signedLT( val_rsrc1, 0 ) )
478 begin
479 newPC = pc_plus4 + (sext(it.offset) << 2);
480 branchTaken = True;
481 end
482 end
484 tagged BGEZ .it :
485 begin
486 let val_rsrc1 <- rf.rd1(it.rsrc);
487 if ( signedGE( val_rsrc1, 0 ) )
488 begin
489 newPC = pc_plus4 + (sext(it.offset) << 2);
490 branchTaken = True;
491 end
492 end
494 tagged BEQ .it :
495 begin
496 let val_rsrc11 <- rf.rd1(it.rsrc1);
497 let val_rsrc22 <- rf.rd2(it.rsrc2);
498 if ( val_rsrc11 == val_rsrc22 )
499 begin
500 newPC = pc_plus4 + (sext(it.offset) << 2);
501 branchTaken = True;
502 end
503 end
505 tagged BNE .it :
506 begin
507 let val_rsrc11 <- rf.rd1(it.rsrc1);
508 let val_rsrc22 <- rf.rd2(it.rsrc2);
509 if ( val_rsrc11 != val_rsrc22 )
510 begin
511 newPC = pc_plus4 + (sext(it.offset) << 2);
512 branchTaken = True;
513 end
514 end
516 // -- Jumps -----------------------------------------------------
518 tagged J .it :
519 begin
520 newPC = { pc_plus4[31:28], it.target, 2'b0 };
521 branchTaken = True;
522 end
524 tagged JR .it :
525 begin
526 let val_rsrc1 <- rf.rd1(it.rsrc);
527 newPC = val_rsrc1;
528 branchTaken = True;
529 end
531 tagged JAL .it :
532 begin
533 wbQ.enq(tagged WB_ALU {dest:31, data:pc_plus4 });
534 newPC = { pc_plus4[31:28], it.target, 2'b0 };
535 branchTaken = True;
536 end
538 tagged JALR .it :
539 begin
540 let val_rsrc1 <- rf.rd1(it.rsrc);
541 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:pc_plus4 });
542 newPC = val_rsrc1;
543 branchTaken = True;
544 end
546 // -- Cop0 ------------------------------------------------------
548 tagged MTC0 .it : //Recieve things from host computer
549 begin
550 let val_rsrc1 <- rf.rd1(it.rsrc);
551 // $display( " PROCESSOR MTC0 call\n");
552 case ( it.cop0dst )
553 5'd10 : cp0_statsEn <= unpack(truncate(val_rsrc1));
554 5'd21 : cp0_tohost <= truncate(val_rsrc1);
555 5'd26 : cp0_progComp <= unpack(truncate(val_rsrc1)); //states audio program completed and termination okay
556 5'd27 : outAudioFifo.enq(tagged Sample unpack(truncate(val_rsrc1))); //Bit size is 16 not 32
557 default :
558 $display( " RTL-ERROR : %m : Illegal MTC0 cop0dst register!" );
559 endcase
560 wbQ.enq(tagged WB_Host 0); //no idea wwhat this actually should be.
561 end
563 //this is host stuff?
564 tagged MFC0 .it : //Things out
565 begin
566 case ( it.cop0src )
567 // not actually an ALU instruction but don't have the format otherwise
568 5'd10 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(cp0_statsEn)) });
569 5'd20 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_fromhost });
570 5'd21 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_tohost });
571 5'd25 : begin
572 // $display( "**** EOF Requested");
573 let sample = inAudioFifo.first();
574 case (sample) matches
575 tagged EndOfFile :
576 begin
577 $display("PROCESSOR sent toC EOF");
578 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(True)) }); // Reading clears bit
579 inAudioFifo.deq;
580 end
581 tagged Sample .data:
582 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(False)) }); // Reading clears bit
583 endcase
584 end
585 5'd28 : begin
586 $display( "***** Reqesting Sample");
587 let sample = inAudioFifo.first(); // is this going to cause perf. delay?
588 if (sample matches tagged Sample .audio) // if it is EOF another rule sets the cp0_audioEOF
589 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(audio)) }); // do I need pack?
590 else $display ( "Audio File EOF Reached. Invalid sample request.");
591 inAudioFifo.deq();
592 end
593 default :
594 $display( " RTL-ERROR : %m : Illegal MFC0 cop0src register!" );
595 endcase
596 end
598 // -- Illegal ---------------------------------------------------
600 default :
601 $display( " RTL-ERROR : %m : Illegal instruction !" );
603 endcase
605 //evaluate branch prediction
606 Addr ppc = pcQ.first().qnxtpc; //predicted branch
607 if (ppc != newPC) //prediction wrong
608 begin
609 epoch <= pcQ.first().qepoch + 1;
610 bp.upd(instrpc, newPC); //update branch predictor
611 pcQ.clear();
612 pc <= newPC;
613 end
614 else
615 pcQ.deq();
616 //rlm: removing
617 // if ( cp0_statsEn )
618 // num_inst.incr();
620 endrule
622 rule writeback; // ( stage == Writeback );
623 traceTiny("mkProc", "writeback","W");
626 // get what to do off the writeback queue
627 wbQ.deq();
628 case (wbQ.first()) matches
629 tagged WB_ALU {data:.res, dest:.rdst} : rf.wr(rdst, res);
630 tagged WB_Load .regWr :
631 begin
632 dataRespQ.deq();
633 if (dataRespQ.first() matches tagged LoadResp .ld)
634 rf.wr(truncate(ld.tag), ld.data); // no need to use Rindx from queue? Duplicate?
635 end
636 tagged WB_Store : dataRespQ.deq();
637 tagged WB_Host .dat : noAction;
638 endcase
640 endrule
642 //rlm remove
643 // rule inc_num_cycles;
644 // if ( cp0_statsEn )
645 // num_cycles.incr();
646 // endrule
648 /*
649 // for now, we don't do anything.
650 rule connectAudioReqResp;
651 $display("rlm: PROCESSOR copies a datum\n");
652 outAudioFifo.enq(inAudioFifo.first());
653 inAudioFifo.deq;
654 endrule
655 */
656 /*
657 rule flagAudioEnd (inAudioFifo.first() matches tagged EndOfFile);
658 $display (" PROCESSOR End Audio Flag Set ");
659 cp0_audioEOF <= True;
660 inAudioFifo.deq;
661 endrule
662 */
663 rule sendProcEnd (cp0_progComp);
664 $display (" PROCESSOR Says Program Complete ");
665 outAudioFifo.enq(tagged EndOfFile);
666 cp0_progComp <= False; //only send one. And functions to reset
667 endrule
670 //-----------------------------------------------------------
671 // Methods
673 interface Client imem_client;
674 interface Get request = fifoToGet(instReqQ);
675 interface Put response = fifoToPut(instRespQ);
676 endinterface
678 interface Client dmem_client;
679 interface Get request = fifoToGet(dataReqQ);
680 interface Put response = fifoToPut(dataRespQ);
681 endinterface
683 interface Get statsEn_get = toGet(asReg(cp0_statsEn));
685 /*
686 interface CPUToHost tohost;
687 method Bit#(32) cpuToHost(int req);
688 return (case (req)
689 0: cp0_tohost;
690 1: pc;
691 2: zeroExtend(pack(stage));
692 endcase);
693 endmethod
694 endinterface
695 */
697 interface Get sampleOutput = fifoToGet(outAudioFifo);
698 interface Put sampleInput = fifoToPut(inAudioFifo);
700 endmodule