pygar: modules/bluespec/Pygar/core/Processor.bsv annotate

annotate modules/bluespec/Pygar/core/Processor.bsv @ 23:90197e3375e2 pygar svn.24

[svn r24] added testing, but something is wrong with our c++ file.

author	rlm
date	Wed, 28 Apr 2010 08:19:09 -0400
parents	cffe0829ce14
children	220c14f5963c

rev	line source
rlm@8	1 /// The MIT License
rlm@8	2
rlm@8	3 // Copyright (c) 2009 Massachusetts Institute of Technology
rlm@8	4
rlm@8	5 // Permission is hereby granted, free of charge, to any person obtaining a copy
rlm@8	6 // of this software and associated documentation files (the "Software"), to deal
rlm@8	7 // in the Software without restriction, including without limitation the rights
rlm@8	8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
rlm@8	9 // copies of the Software, and to permit persons to whom the Software is
rlm@8	10 // furnished to do so, subject to the following conditions:
rlm@8	11
rlm@8	12 // The above copyright notice and this permission notice shall be included in
rlm@8	13 // all copies or substantial portions of the Software.
rlm@8	14
rlm@8	15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
rlm@8	16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
rlm@8	17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
rlm@8	18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
rlm@8	19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
rlm@8	20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
rlm@8	21 // THE SOFTWARE.
rlm@8	22
rlm@19	23
rlm@19	24
rlm@8	25 import Connectable::*;
rlm@8	26 import GetPut::*;
rlm@8	27 import ClientServer::*;
rlm@8	28 import RegFile::*;
rlm@8	29
rlm@8	30 import FIFO::*;
rlm@8	31 import FIFOF::*;
rlm@8	32 import SFIFO::*;
rlm@8	33 import RWire::*;
rlm@8	34
punk@11	35 import Trace::*;
rlm@8	36 import BFIFO::*;
rlm@8	37 import MemTypes::*;
rlm@8	38 import ProcTypes::*;
rlm@8	39 import BRegFile::*;
rlm@8	40 import BranchPred::*;
rlm@8	41 //import PathTypes::*; This is only there to force the debugging
rlm@8	42
rlm@8	43 //AWB includes
rlm@8	44 `include "asim/provides/low_level_platform_interface.bsh"
rlm@8	45 `include "asim/provides/soft_connections.bsh"
rlm@8	46 `include "asim/provides/common_services.bsh"
rlm@8	47
rlm@8	48 // Local includes
punk@11	49 //`include "asim/provides/processor_library.bsh" (included above directly)
punk@12	50 `include "asim/rrr/remote_server_stub_AUDIOCORERRR.bsh"
rlm@8	51 `include "asim/provides/common_services.bsh"
rlm@8	52 `include "asim/dict/STATS_PROCESSOR.bsh"
rlm@8	53
punk@11	54 // Local includes. Look for the correspondingly named .awb files
punk@11	55 // workspace/labs/src/mit-6.375/modules/bluespec/mit-6.375/common/
punk@11	56 // to find the actual Bluespec files which are used to generate
punk@11	57 // these includes. These files are specific to this audio processing
punk@11	58 // pipeline
punk@11	59
punk@12	60 `include "asim/provides/audio_pipe_types.bsh"
rlm@8	61
punk@12	62 //interface CPUToHost;
punk@12	63 // method Bit#(32) cpuToHost(int req);
punk@12	64 //endinterface
rlm@8	65
rlm@8	66 interface Proc;
rlm@8	67
rlm@8	68 // Interface from processor to caches
rlm@8	69 interface Client#(DataReq,DataResp) dmem_client;
rlm@8	70 interface Client#(InstReq,InstResp) imem_client;
rlm@8	71
rlm@8	72 // Interface for enabling/disabling statistics on the rest of the core
rlm@8	73 interface Get#(Bool) statsEn_get;
rlm@8	74
punk@12	75 // // Interface to host
punk@12	76 // interface CPUToHost tohost;
rlm@8	77
punk@11	78 // Interface to Audio Pipeline
punk@15	79 interface Get#(AudioProcessorUnit) sampleOutput;
punk@11	80
rlm@8	81 endinterface
rlm@8	82
punk@11	83 //The full interface for this is as below in the common file for audioProcessorTypes.bsv
punk@15	84 //interface AudioOut;
punk@15	85 // interface Get#(AudioProcessorUnit) audioSampleOutput;
punk@15	86 //endinterface
rlm@8	87
punk@12	88 //interface AudioIn;
punk@12	89 // interface Put#(AudioProcessorUnit) audioSampleInput;
punk@12	90 //endinterface
punk@12	91
rlm@8	92 typedef enum { PCgen, Exec, Writeback } Stage deriving(Eq,Bits);
rlm@8	93
rlm@8	94 //-----------------------------------------------------------
rlm@8	95 // Register file module
rlm@8	96 //-----------------------------------------------------------
rlm@8	97
rlm@8	98 interface BRFile;
rlm@8	99 method Action wr( Rindx rindx, Bit#(32) data );
rlm@8	100 method Bit#(32) rd1( Rindx rindx );
rlm@8	101 method Bit#(32) rd2( Rindx rindx );
rlm@8	102 endinterface
rlm@8	103
rlm@8	104 module mkBRFile( BRFile );
rlm@8	105
rlm@8	106 RegFile#(Rindx,Bit#(32)) rfile <- mkBRegFile();
rlm@8	107
rlm@8	108 method Action wr( Rindx rindx, Bit#(32) data );
rlm@8	109 rfile.upd( rindx, data );
rlm@8	110 endmethod
rlm@8	111
rlm@8	112 method Bit#(32) rd1( Rindx rindx );
rlm@8	113 return ( rindx == 0 ) ? 0 : rfile.sub(rindx);
rlm@8	114 endmethod
rlm@8	115
rlm@8	116 method Bit#(32) rd2( Rindx rindx );
rlm@8	117 return ( rindx == 0 ) ? 0 : rfile.sub(rindx);
rlm@8	118 endmethod
rlm@8	119
rlm@8	120 endmodule
rlm@8	121
rlm@8	122 //-----------------------------------------------------------
rlm@8	123 // Helper functions
rlm@8	124 //-----------------------------------------------------------
rlm@8	125
rlm@8	126 function Bit#(32) slt( Bit#(32) val1, Bit#(32) val2 );
rlm@8	127 return zeroExtend( pack( signedLT(val1,val2) ) );
rlm@8	128 endfunction
rlm@8	129
rlm@8	130 function Bit#(32) sltu( Bit#(32) val1, Bit#(32) val2 );
rlm@8	131 return zeroExtend( pack( val1 < val2 ) );
rlm@8	132 endfunction
rlm@8	133
rlm@8	134 function Bit#(32) rshft( Bit#(32) val );
rlm@8	135 return zeroExtend(val[4:0]);
rlm@8	136 endfunction
rlm@8	137
rlm@8	138
rlm@8	139 //-----------------------------------------------------------
rlm@8	140 // Find funct for wbQ
rlm@8	141 //-----------------------------------------------------------
rlm@8	142 function Bool findwbf(Rindx fVal, WBResult cmpVal);
rlm@8	143 case (cmpVal) matches
rlm@8	144 tagged WB_ALU {data:.res, dest:.rd} :
rlm@8	145 return (fVal == rd);
rlm@8	146 tagged WB_Load .rd :
rlm@8	147 return (fVal == rd);
rlm@8	148 tagged WB_Store .st :
rlm@8	149 return False;
rlm@8	150 tagged WB_Host .x :
rlm@8	151 return False;
rlm@8	152 endcase
rlm@8	153 endfunction
rlm@8	154
rlm@8	155
rlm@8	156 //-----------------------------------------------------------
rlm@8	157 // Stall funct for wbQ
rlm@8	158 //-----------------------------------------------------------
rlm@8	159 function Bool stall(Instr inst, SFIFO#(WBResult, Rindx) f);
rlm@8	160 case (inst) matches
rlm@8	161 // -- Memory Ops ------------------------------------------------
rlm@8	162 tagged LW .it :
rlm@8	163 return f.find(it.rbase);
rlm@8	164 tagged SW {rsrc:.dreg, rbase:.addr, offset:.o} :
rlm@8	165 return (f.find(addr) \|\| f.find2(dreg));
rlm@8	166
rlm@8	167 // -- Simple Ops ------------------------------------------------
rlm@8	168 tagged ADDIU .it : return f.find(it.rsrc);
rlm@8	169 tagged SLTI .it : return f.find(it.rsrc);
rlm@8	170 tagged SLTIU .it : return f.find(it.rsrc);
rlm@8	171 tagged ANDI .it : return f.find(it.rsrc);
rlm@8	172 tagged ORI .it : return f.find(it.rsrc);
rlm@8	173 tagged XORI .it : return f.find(it.rsrc);
rlm@8	174
rlm@8	175 tagged LUI .it : return f.find(it.rdst); //this rds/wrs itself
rlm@8	176 tagged SLL .it : return f.find(it.rsrc);
rlm@8	177 tagged SRL .it : return f.find(it.rsrc);
rlm@8	178 tagged SRA .it : return f.find(it.rsrc);
rlm@8	179 tagged SLLV .it : return (f.find(it.rsrc) \|\| f.find(it.rshamt));
rlm@8	180 tagged SRLV .it : return (f.find(it.rsrc) \|\| f.find(it.rshamt));
rlm@8	181 tagged SRAV .it : return (f.find(it.rsrc) \|\| f.find(it.rshamt));
rlm@8	182 tagged ADDU .it : return (f.find(it.rsrc1) \|\| f.find2(it.rsrc2));
rlm@8	183 tagged SUBU .it : return (f.find(it.rsrc1) \|\| f.find2(it.rsrc2));
rlm@8	184 tagged AND .it : return (f.find(it.rsrc1) \|\| f.find2(it.rsrc2));
rlm@8	185 tagged OR .it : return (f.find(it.rsrc1) \|\| f.find2(it.rsrc2));
rlm@8	186 tagged XOR .it : return (f.find(it.rsrc1) \|\| f.find2(it.rsrc2));
rlm@8	187 tagged NOR .it : return (f.find(it.rsrc1) \|\| f.find2(it.rsrc2));
rlm@8	188 tagged SLT .it : return (f.find(it.rsrc1) \|\| f.find2(it.rsrc2));
rlm@8	189 tagged SLTU .it : return (f.find(it.rsrc1) \|\| f.find2(it.rsrc2));
rlm@8	190
rlm@8	191
rlm@8	192 // -- Branches --------------------------------------------------
rlm@8	193
rlm@8	194 tagged BLEZ .it : return (f.find(it.rsrc));
rlm@8	195 tagged BGTZ .it : return (f.find(it.rsrc));
rlm@8	196 tagged BLTZ .it : return (f.find(it.rsrc));
rlm@8	197 tagged BGEZ .it : return (f.find(it.rsrc));
rlm@8	198 tagged BEQ .it : return (f.find(it.rsrc1) \|\| f.find2(it.rsrc2));
rlm@8	199 tagged BNE .it : return (f.find(it.rsrc1) \|\| f.find2(it.rsrc2));
rlm@8	200
rlm@8	201 // -- Jumps -----------------------------------------------------
rlm@8	202
rlm@8	203 tagged J .it : return False;
rlm@8	204 tagged JR .it : return f.find(it.rsrc);
rlm@8	205 tagged JALR .it : return f.find(it.rsrc);
rlm@8	206 tagged JAL .it : return False;
rlm@8	207
rlm@8	208 // -- Cop0 ------------------------------------------------------
rlm@8	209
rlm@8	210 tagged MTC0 .it : return f.find(it.rsrc);
rlm@8	211 tagged MFC0 .it : return False;
rlm@8	212
rlm@8	213 // -- Illegal ---------------------------------------------------
rlm@8	214
rlm@8	215 default : return False;
rlm@8	216
rlm@8	217 endcase
rlm@8	218 endfunction
rlm@8	219 //-----------------------------------------------------------
rlm@8	220 // Reference processor
rlm@8	221 //-----------------------------------------------------------
rlm@8	222
rlm@8	223
rlm@8	224 //(* doc = "synthesis attribute ram_style mkProc distributed;" *)
rlm@8	225 //(* synthesize *)
rlm@8	226
rlm@8	227 module [CONNECTED_MODULE] mkProc( Proc );
rlm@8	228
rlm@8	229 //-----------------------------------------------------------
rlm@8	230 // Debug port
rlm@8	231
punk@12	232 ServerStub_AUDIOCORERRR server_stub <- mkServerStub_AUDIOCORERRR();
rlm@8	233
rlm@8	234
rlm@8	235 //-----------------------------------------------------------
rlm@8	236 // State
rlm@8	237
rlm@8	238 // Standard processor state
rlm@8	239
rlm@8	240 Reg#(Addr) pc <- mkReg(32'h00001000);
rlm@8	241 Reg#(Epoch) epoch <- mkReg(0);
rlm@8	242 Reg#(Stage) stage <- mkReg(PCgen);
rlm@8	243 BRFile rf <- mkBRFile;
rlm@8	244
rlm@8	245 // Branch Prediction
rlm@8	246 BranchPred bp <- mkBranchPred();
rlm@8	247 FIFO#(PCStat) execpc <- mkLFIFO();
rlm@8	248
rlm@8	249 // Pipelines
rlm@8	250 FIFO#(PCStat) pcQ <-mkSizedFIFO(3);
rlm@8	251 SFIFO#(WBResult, Rindx) wbQ <-mkSFIFO(findwbf);
rlm@8	252
rlm@8	253 Reg#(Bit#(32)) cp0_tohost <- mkReg(0);
rlm@8	254 Reg#(Bit#(32)) cp0_fromhost <- mkReg(0);
rlm@8	255 Reg#(Bool) cp0_statsEn <- mkReg(False);
rlm@8	256
rlm@8	257 // Memory request/response state
rlm@8	258
rlm@8	259 FIFO#(InstReq) instReqQ <- mkBFIFO1();
rlm@8	260 FIFO#(InstResp) instRespQ <- mkFIFO();
rlm@8	261
rlm@8	262 FIFO#(DataReq) dataReqQ <- mkBFIFO1();
rlm@8	263 FIFO#(DataResp) dataRespQ <- mkFIFO();
rlm@8	264
punk@11	265 // Audio I/O
punk@11	266 FIFO#(AudioProcessorUnit) inAudioFifo <- mkFIFO;
punk@11	267 FIFO#(AudioProcessorUnit) outAudioFifo <- mkFIFO;
punk@11	268
punk@11	269
punk@11	270 // Statistics state (2010)
punk@11	271 // Reg#(Stat) num_cycles <- mkReg(0);
punk@11	272 // Reg#(Stat) num_inst <- mkReg(0);
rlm@8	273
rlm@8	274 //Or:
punk@11	275 // Statistics state
punk@11	276 STAT num_cycles <- mkStatCounter(`STATS_PROCESSOR_CYCLE_COUNT);
punk@11	277 STAT num_inst <- mkStatCounter(`STATS_PROCESSOR_INST_COUNT);
rlm@8	278
rlm@8	279 //-----------------------------------------------------------
rlm@8	280 // Rules
rlm@8	281
rlm@8	282 (* descending_urgency = "exec, pcgen" *)
rlm@8	283 rule pcgen; //( stage == PCgen );
rlm@8	284 let pc_plus4 = pc + 4;
rlm@8	285
rlm@8	286 traceTiny("mkProc", "pc",pc);
rlm@8	287 traceTiny("mkProc", "pcgen","P");
rlm@8	288 instReqQ.enq( LoadReq{ addr:pc, tag:epoch} );
rlm@8	289
rlm@8	290 let next_pc = bp.get(pc);
rlm@8	291 if (next_pc matches tagged Valid .npc)
rlm@8	292 begin
rlm@8	293 pcQ.enq(PCStat {qpc:pc, qnxtpc:npc, qepoch:epoch});
rlm@8	294 pc <= npc;
rlm@8	295 end
rlm@8	296 else
rlm@8	297 begin
rlm@8	298 pcQ.enq(PCStat {qpc:pc, qnxtpc:pc_plus4, qepoch:epoch});
rlm@8	299 pc <= pc_plus4;
rlm@8	300 end
rlm@8	301
rlm@8	302 endrule
rlm@8	303
rlm@8	304 rule discard (instRespQ.first() matches tagged LoadResp .ld
rlm@8	305 &&& ld.tag != epoch);
rlm@8	306 traceTiny("mkProc", "stage", "D");
rlm@8	307 instRespQ.deq();
rlm@8	308 endrule
rlm@8	309
rlm@8	310 (* conflict_free = "exec, writeback" *)
rlm@8	311 rule exec (instRespQ.first() matches tagged LoadResp.ld
rlm@8	312 &&& (ld.tag == epoch)
rlm@8	313 &&& unpack(ld.data) matches .inst
rlm@8	314 &&& !stall(inst, wbQ));
rlm@8	315
rlm@8	316 // Some abbreviations
rlm@8	317 let sext = signExtend;
rlm@8	318 let zext = zeroExtend;
rlm@8	319 let sra = signedShiftRight;
rlm@8	320
rlm@8	321 // Get the instruction
rlm@8	322
rlm@8	323 instRespQ.deq();
rlm@8	324 Instr inst
rlm@8	325 = case ( instRespQ.first() ) matches
rlm@8	326 tagged LoadResp .ld : return unpack(ld.data);
rlm@8	327 tagged StoreResp .st : return ?;
rlm@8	328 endcase;
rlm@8	329
rlm@8	330 // Get the PC info
rlm@8	331 let instrpc = pcQ.first().qpc;
rlm@8	332 let pc_plus4 = instrpc + 4;
rlm@8	333
rlm@8	334 Bool branchTaken = False;
rlm@8	335 Addr newPC = pc_plus4;
rlm@8	336
rlm@8	337 // Tracing
rlm@8	338 traceTiny("mkProc", "exec","X");
rlm@8	339 traceTiny("mkProc", "exInstTiny",inst);
rlm@8	340 traceFull("mkProc", "exInstFull",inst);
rlm@8	341
rlm@8	342 case ( inst ) matches
rlm@8	343
rlm@8	344 // -- Memory Ops ------------------------------------------------
rlm@8	345
rlm@8	346 tagged LW .it :
rlm@8	347 begin
rlm@8	348 Addr addr = rf.rd1(it.rbase) + sext(it.offset);
rlm@8	349 dataReqQ.enq( LoadReq{ addr:addr, tag:zeroExtend(it.rdst) } );
rlm@8	350 wbQ.enq(tagged WB_Load it.rdst);
rlm@8	351 end
rlm@8	352
rlm@8	353 tagged SW .it :
rlm@8	354 begin
rlm@8	355 Addr addr = rf.rd1(it.rbase) + sext(it.offset);
rlm@8	356 dataReqQ.enq( StoreReq{ tag:0, addr:addr, data:rf.rd2(it.rsrc) } );
rlm@8	357 wbQ.enq(tagged WB_Store);
rlm@8	358 end
rlm@8	359
rlm@8	360 // -- Simple Ops ------------------------------------------------
rlm@8	361
rlm@8	362 tagged ADDIU .it :
rlm@8	363 begin
rlm@8	364 Bit#(32) result = rf.rd1(it.rsrc) + sext(it.imm);
rlm@8	365 wbQ.enq(tagged WB_ALU {data:result, dest:it.rdst});
rlm@8	366 end
rlm@8	367 tagged SLTI .it : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:slt( rf.rd1(it.rsrc), sext(it.imm) )});
rlm@8	368 tagged SLTIU .it : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:sltu( rf.rd1(it.rsrc), sext(it.imm) ) });
rlm@8	369 tagged ANDI .it :
rlm@8	370 begin
rlm@8	371 Bit#(32) zext_it_imm = zext(it.imm);
rlm@8	372 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(rf.rd1(it.rsrc) & zext_it_imm)} );
rlm@8	373 end
rlm@8	374 tagged ORI .it :
rlm@8	375 begin
rlm@8	376 Bit#(32) zext_it_imm = zext(it.imm);
rlm@8	377 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(rf.rd1(it.rsrc) \| zext_it_imm)} );
rlm@8	378 end
rlm@8	379 tagged XORI .it :
rlm@8	380 begin
rlm@8	381 Bit#(32) zext_it_imm = zext(it.imm);
rlm@8	382 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) ^ zext_it_imm )});
rlm@8	383 end
rlm@8	384 tagged LUI .it :
rlm@8	385 begin
rlm@8	386 Bit#(32) zext_it_imm = zext(it.imm);
rlm@8	387 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(zext_it_imm << 32'd16) });
rlm@8	388 end
rlm@8	389
rlm@8	390 tagged SLL .it :
rlm@8	391 begin
rlm@8	392 Bit#(32) zext_it_shamt = zext(it.shamt);
rlm@8	393 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) << zext_it_shamt )} );
rlm@8	394 end
rlm@8	395 tagged SRL .it :
rlm@8	396 begin
rlm@8	397 Bit#(32) zext_it_shamt = zext(it.shamt);
rlm@8	398 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) >> zext_it_shamt )});
rlm@8	399 end
rlm@8	400 tagged SRA .it :
rlm@8	401 begin
rlm@8	402 Bit#(32) zext_it_shamt = zext(it.shamt);
rlm@8	403 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( rf.rd1(it.rsrc), zext_it_shamt )});
rlm@8	404 end
rlm@8	405 tagged SLLV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) << rshft(rf.rd2(it.rshamt)) )});
rlm@8	406 tagged SRLV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) >> rshft(rf.rd2(it.rshamt)) )} );
rlm@8	407 tagged SRAV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( rf.rd1(it.rsrc), rshft(rf.rd2(it.rshamt)) ) });
rlm@8	408 tagged ADDU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) + rf.rd2(it.rsrc2) )} );
rlm@8	409 tagged SUBU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) - rf.rd2(it.rsrc2) )} );
rlm@8	410 tagged AND .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) & rf.rd2(it.rsrc2) )} );
rlm@8	411 tagged OR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) \| rf.rd2(it.rsrc2) )} );
rlm@8	412 tagged XOR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) ^ rf.rd2(it.rsrc2) )} );
rlm@8	413 tagged NOR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(~(rf.rd1(it.rsrc1) \| rf.rd2(it.rsrc2)) )} );
rlm@8	414 tagged SLT .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:slt( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) });
rlm@8	415 tagged SLTU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sltu( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) });
rlm@8	416
rlm@8	417 // -- Branches --------------------------------------------------
rlm@8	418
rlm@8	419 tagged BLEZ .it :
rlm@8	420 if ( signedLE( rf.rd1(it.rsrc), 0 ) )
rlm@8	421 begin
rlm@8	422 newPC = pc_plus4 + (sext(it.offset) << 2);
rlm@8	423 branchTaken = True;
rlm@8	424 end
rlm@8	425
rlm@8	426 tagged BGTZ .it :
rlm@8	427 if ( signedGT( rf.rd1(it.rsrc), 0 ) )
rlm@8	428 begin
rlm@8	429 newPC = pc_plus4 + (sext(it.offset) << 2);
rlm@8	430 branchTaken = True;
rlm@8	431 end
rlm@8	432
rlm@8	433 tagged BLTZ .it :
rlm@8	434 if ( signedLT( rf.rd1(it.rsrc), 0 ) )
rlm@8	435 begin
rlm@8	436 newPC = pc_plus4 + (sext(it.offset) << 2);
rlm@8	437 branchTaken = True;
rlm@8	438 end
rlm@8	439
rlm@8	440 tagged BGEZ .it :
rlm@8	441 if ( signedGE( rf.rd1(it.rsrc), 0 ) )
rlm@8	442 begin
rlm@8	443 newPC = pc_plus4 + (sext(it.offset) << 2);
rlm@8	444 branchTaken = True;
rlm@8	445 end
rlm@8	446
rlm@8	447 tagged BEQ .it :
rlm@8	448 if ( rf.rd1(it.rsrc1) == rf.rd2(it.rsrc2) )
rlm@8	449 begin
rlm@8	450 newPC = pc_plus4 + (sext(it.offset) << 2);
rlm@8	451 branchTaken = True;
rlm@8	452 end
rlm@8	453
rlm@8	454 tagged BNE .it :
rlm@8	455 if ( rf.rd1(it.rsrc1) != rf.rd2(it.rsrc2) )
rlm@8	456 begin
rlm@8	457 newPC = pc_plus4 + (sext(it.offset) << 2);
rlm@8	458 branchTaken = True;
rlm@8	459 end
rlm@8	460
rlm@8	461 // -- Jumps -----------------------------------------------------
rlm@8	462
rlm@8	463 tagged J .it :
rlm@8	464 begin
rlm@8	465 newPC = { pc_plus4[31:28], it.target, 2'b0 };
rlm@8	466 branchTaken = True;
rlm@8	467 end
rlm@8	468
rlm@8	469 tagged JR .it :
rlm@8	470 begin
rlm@8	471 newPC = rf.rd1(it.rsrc);
rlm@8	472 branchTaken = True;
rlm@8	473 end
rlm@8	474
rlm@8	475 tagged JAL .it :
rlm@8	476 begin
rlm@8	477 wbQ.enq(tagged WB_ALU {dest:31, data:pc_plus4 });
rlm@8	478 newPC = { pc_plus4[31:28], it.target, 2'b0 };
rlm@8	479 branchTaken = True;
rlm@8	480 end
rlm@8	481
rlm@8	482 tagged JALR .it :
rlm@8	483 begin
rlm@8	484 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:pc_plus4 });
rlm@8	485 newPC = rf.rd1(it.rsrc);
rlm@8	486 branchTaken = True;
rlm@8	487 end
rlm@8	488
rlm@8	489 // -- Cop0 ------------------------------------------------------
rlm@8	490
rlm@8	491 tagged MTC0 .it :
rlm@8	492 begin
rlm@8	493 case ( it.cop0dst )
rlm@8	494 5'd10 : cp0_statsEn <= unpack(truncate(rf.rd1(it.rsrc)));
rlm@8	495 5'd21 : cp0_tohost <= truncate(rf.rd1(it.rsrc));
rlm@8	496 default :
rlm@8	497 $display( " RTL-ERROR : %m : Illegal MTC0 cop0dst register!" );
rlm@8	498 endcase
rlm@8	499 wbQ.enq(tagged WB_Host 0); //no idea wwhat this actually should be.
rlm@8	500 end
rlm@8	501
rlm@8	502 //this is host stuff?
rlm@8	503 tagged MFC0 .it :
rlm@8	504 begin
rlm@8	505 case ( it.cop0src )
rlm@8	506 // not actually an ALU instruction but don't have the format otherwise
rlm@8	507 5'd10 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(cp0_statsEn)) });
rlm@8	508 5'd20 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_fromhost });
rlm@8	509 5'd21 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_tohost });
rlm@8	510 default :
rlm@8	511 $display( " RTL-ERROR : %m : Illegal MFC0 cop0src register!" );
rlm@8	512 endcase
rlm@8	513 end
rlm@8	514
rlm@8	515 // -- Illegal ---------------------------------------------------
rlm@8	516
rlm@8	517 default :
rlm@8	518 $display( " RTL-ERROR : %m : Illegal instruction !" );
rlm@8	519
rlm@8	520 endcase
rlm@8	521
rlm@8	522 //evaluate branch prediction
rlm@8	523 Addr ppc = pcQ.first().qnxtpc; //predicted branch
rlm@8	524 if (ppc != newPC) //prediction wrong
rlm@8	525 begin
rlm@8	526 epoch <= pcQ.first().qepoch + 1;
rlm@8	527 bp.upd(instrpc, newPC); //update branch predictor
rlm@8	528 pcQ.clear();
rlm@8	529 pc <= newPC;
rlm@8	530 end
rlm@8	531 else
rlm@8	532 pcQ.deq();
rlm@8	533
rlm@8	534 if ( cp0_statsEn )
punk@11	535 num_inst.incr();
rlm@8	536
rlm@8	537 endrule
rlm@8	538
rlm@8	539 rule writeback; // ( stage == Writeback );
rlm@8	540 traceTiny("mkProc", "writeback","W");
rlm@8	541
rlm@8	542
rlm@8	543 // get what to do off the writeback queue
rlm@8	544 wbQ.deq();
rlm@8	545 case (wbQ.first()) matches
rlm@8	546 tagged WB_ALU {data:.res, dest:.rdst} : rf.wr(rdst, res);
rlm@8	547 tagged WB_Load .regWr :
rlm@8	548 begin
rlm@8	549 dataRespQ.deq();
rlm@8	550 if (dataRespQ.first() matches tagged LoadResp .ld)
rlm@8	551 rf.wr(truncate(ld.tag), ld.data); // no need to use Rindx from queue? Duplicate?
rlm@8	552 end
rlm@8	553 tagged WB_Store : dataRespQ.deq();
rlm@8	554 tagged WB_Host .dat : noAction;
rlm@8	555 endcase
rlm@8	556
rlm@8	557 endrule
rlm@8	558
rlm@8	559 rule inc_num_cycles;
rlm@8	560 if ( cp0_statsEn )
punk@11	561 num_cycles.incr();
rlm@8	562 endrule
punk@11	563
punk@11	564 (* conservative_implicit_conditions *)
punk@11	565 rule handleCPUToHost;
punk@11	566 let req <- server_stub.acceptRequest_ReadCPUToHost();
punk@11	567 case (req)
punk@15	568 0: server_stub.sendResponse_ReadCPUToHost(cp0_tohost);
punk@11	569 1: server_stub.sendResponse_ReadCPUToHost(pc);
punk@11	570 2: server_stub.sendResponse_ReadCPUToHost(zeroExtend(pack(stage)));
punk@11	571 endcase
punk@11	572 endrule
punk@11	573
punk@11	574 // for now, we don't do anything.
punk@11	575 rule connectAudioReqResp;
rlm@23	576 $display("rlm: PROCESSOR copies a datum\n");
rlm@23	577 outAudioFifo.enq(inAudioFifo.first());
rlm@23	578 inAudioFifo.deq;
punk@11	579 endrule
rlm@8	580
punk@12	581 // Server items & rules:
punk@12	582
punk@12	583 rule feedInput;
punk@12	584 let command <- server_stub.acceptRequest_SendUnprocessedStream();
punk@12	585 AudioProcessorControl ctrl = unpack(truncate(command.ctrl));
rlm@23	586 $display("rlm: PROCESSOR: recieved data\n");
punk@12	587 if(ctrl == EndOfFile)
punk@12	588 begin
punk@12	589 inAudioFifo.enq(tagged EndOfFile);
punk@12	590 end
punk@12	591 else
punk@12	592 begin
punk@12	593 inAudioFifo.enq(tagged Sample unpack(truncate(command.sample)));
punk@12	594 end
punk@12	595 endrule
punk@12	596
punk@12	597
rlm@8	598 //-----------------------------------------------------------
rlm@8	599 // Methods
rlm@8	600
rlm@8	601 interface Client imem_client;
punk@21	602 interface Get request = fifoToGet(instReqQ);
punk@21	603 interface Put response = fifoToPut(instRespQ);
rlm@8	604 endinterface
rlm@8	605
rlm@8	606 interface Client dmem_client;
punk@21	607 interface Get request = fifoToGet(dataReqQ);
punk@21	608 interface Put response = fifoToPut(dataRespQ);
rlm@8	609 endinterface
rlm@8	610
rlm@8	611 interface Get statsEn_get = toGet(asReg(cp0_statsEn));
rlm@8	612
punk@12	613 // interface CPUToHost tohost;
punk@12	614 // method Bit#(32) cpuToHost(int req);
punk@12	615 // return (case (req)
punk@12	616 // 0: cp0_tohost;
punk@12	617 // 1: pc;
punk@12	618 // 2: zeroExtend(pack(stage));
punk@12	619 // endcase);
punk@12	620 // endmethod
punk@12	621 // endinterface
punk@12	622
punk@21	623 interface Get sampleOutput = fifoToGet(outAudioFifo);
punk@11	624
rlm@8	625 endmodule
rlm@8	626

Mercurial > pygar

annotate modules/bluespec/Pygar/core/Processor.bsv @ 23:90197e3375e2 pygar svn.24