rlm@8: /// The MIT License rlm@8: rlm@8: // Copyright (c) 2009 Massachusetts Institute of Technology rlm@8: rlm@8: // Permission is hereby granted, free of charge, to any person obtaining a copy rlm@8: // of this software and associated documentation files (the "Software"), to deal rlm@8: // in the Software without restriction, including without limitation the rights rlm@8: // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell rlm@8: // copies of the Software, and to permit persons to whom the Software is rlm@8: // furnished to do so, subject to the following conditions: rlm@8: rlm@8: // The above copyright notice and this permission notice shall be included in rlm@8: // all copies or substantial portions of the Software. rlm@8: rlm@8: // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR rlm@8: // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, rlm@8: // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE rlm@8: // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER rlm@8: // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, rlm@8: // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN rlm@8: // THE SOFTWARE. rlm@8: rlm@19: rlm@19: rlm@8: import Connectable::*; rlm@8: import GetPut::*; rlm@8: import ClientServer::*; rlm@8: import RegFile::*; rlm@8: rlm@8: import FIFO::*; rlm@8: import FIFOF::*; rlm@8: import SFIFO::*; rlm@8: import RWire::*; rlm@8: punk@11: import Trace::*; rlm@8: import BFIFO::*; rlm@8: import MemTypes::*; rlm@8: import ProcTypes::*; rlm@8: import BRegFile::*; rlm@8: import BranchPred::*; rlm@8: //import PathTypes::*; This is only there to force the debugging rlm@8: rlm@8: //AWB includes rlm@8: `include "asim/provides/low_level_platform_interface.bsh" rlm@8: `include "asim/provides/soft_connections.bsh" rlm@8: `include "asim/provides/common_services.bsh" rlm@8: rlm@8: // Local includes punk@11: //`include "asim/provides/processor_library.bsh" (included above directly) punk@12: `include "asim/rrr/remote_server_stub_AUDIOCORERRR.bsh" rlm@8: `include "asim/provides/common_services.bsh" rlm@8: `include "asim/dict/STATS_PROCESSOR.bsh" rlm@8: punk@11: // Local includes. Look for the correspondingly named .awb files punk@11: // workspace/labs/src/mit-6.375/modules/bluespec/mit-6.375/common/ punk@11: // to find the actual Bluespec files which are used to generate punk@11: // these includes. These files are specific to this audio processing punk@11: // pipeline punk@11: punk@12: `include "asim/provides/audio_pipe_types.bsh" rlm@8: punk@12: //interface CPUToHost; punk@12: // method Bit#(32) cpuToHost(int req); punk@12: //endinterface rlm@8: rlm@8: interface Proc; rlm@8: rlm@8: // Interface from processor to caches rlm@8: interface Client#(DataReq,DataResp) dmem_client; rlm@8: interface Client#(InstReq,InstResp) imem_client; rlm@8: rlm@8: // Interface for enabling/disabling statistics on the rest of the core rlm@8: interface Get#(Bool) statsEn_get; rlm@8: punk@12: // // Interface to host punk@12: // interface CPUToHost tohost; rlm@8: punk@11: // Interface to Audio Pipeline punk@15: interface Get#(AudioProcessorUnit) sampleOutput; punk@11: rlm@8: endinterface rlm@8: punk@11: //The full interface for this is as below in the common file for audioProcessorTypes.bsv punk@15: //interface AudioOut; punk@15: // interface Get#(AudioProcessorUnit) audioSampleOutput; punk@15: //endinterface rlm@8: punk@12: //interface AudioIn; punk@12: // interface Put#(AudioProcessorUnit) audioSampleInput; punk@12: //endinterface punk@12: rlm@8: typedef enum { PCgen, Exec, Writeback } Stage deriving(Eq,Bits); rlm@8: rlm@8: //----------------------------------------------------------- rlm@8: // Register file module rlm@8: //----------------------------------------------------------- rlm@8: rlm@8: interface BRFile; rlm@8: method Action wr( Rindx rindx, Bit#(32) data ); rlm@8: method Bit#(32) rd1( Rindx rindx ); rlm@8: method Bit#(32) rd2( Rindx rindx ); rlm@8: endinterface rlm@8: rlm@8: module mkBRFile( BRFile ); rlm@8: rlm@8: RegFile#(Rindx,Bit#(32)) rfile <- mkBRegFile(); rlm@8: rlm@8: method Action wr( Rindx rindx, Bit#(32) data ); rlm@8: rfile.upd( rindx, data ); rlm@8: endmethod rlm@8: rlm@8: method Bit#(32) rd1( Rindx rindx ); rlm@8: return ( rindx == 0 ) ? 0 : rfile.sub(rindx); rlm@8: endmethod rlm@8: rlm@8: method Bit#(32) rd2( Rindx rindx ); rlm@8: return ( rindx == 0 ) ? 0 : rfile.sub(rindx); rlm@8: endmethod rlm@8: rlm@8: endmodule rlm@8: rlm@8: //----------------------------------------------------------- rlm@8: // Helper functions rlm@8: //----------------------------------------------------------- rlm@8: rlm@8: function Bit#(32) slt( Bit#(32) val1, Bit#(32) val2 ); rlm@8: return zeroExtend( pack( signedLT(val1,val2) ) ); rlm@8: endfunction rlm@8: rlm@8: function Bit#(32) sltu( Bit#(32) val1, Bit#(32) val2 ); rlm@8: return zeroExtend( pack( val1 < val2 ) ); rlm@8: endfunction rlm@8: rlm@8: function Bit#(32) rshft( Bit#(32) val ); rlm@8: return zeroExtend(val[4:0]); rlm@8: endfunction rlm@8: rlm@8: rlm@8: //----------------------------------------------------------- rlm@8: // Find funct for wbQ rlm@8: //----------------------------------------------------------- rlm@8: function Bool findwbf(Rindx fVal, WBResult cmpVal); rlm@8: case (cmpVal) matches rlm@8: tagged WB_ALU {data:.res, dest:.rd} : rlm@8: return (fVal == rd); rlm@8: tagged WB_Load .rd : rlm@8: return (fVal == rd); rlm@8: tagged WB_Store .st : rlm@8: return False; rlm@8: tagged WB_Host .x : rlm@8: return False; rlm@8: endcase rlm@8: endfunction rlm@8: rlm@8: rlm@8: //----------------------------------------------------------- rlm@8: // Stall funct for wbQ rlm@8: //----------------------------------------------------------- rlm@8: function Bool stall(Instr inst, SFIFO#(WBResult, Rindx) f); rlm@8: case (inst) matches rlm@8: // -- Memory Ops ------------------------------------------------ rlm@8: tagged LW .it : rlm@8: return f.find(it.rbase); rlm@8: tagged SW {rsrc:.dreg, rbase:.addr, offset:.o} : rlm@8: return (f.find(addr) || f.find2(dreg)); rlm@8: rlm@8: // -- Simple Ops ------------------------------------------------ rlm@8: tagged ADDIU .it : return f.find(it.rsrc); rlm@8: tagged SLTI .it : return f.find(it.rsrc); rlm@8: tagged SLTIU .it : return f.find(it.rsrc); rlm@8: tagged ANDI .it : return f.find(it.rsrc); rlm@8: tagged ORI .it : return f.find(it.rsrc); rlm@8: tagged XORI .it : return f.find(it.rsrc); rlm@8: rlm@8: tagged LUI .it : return f.find(it.rdst); //this rds/wrs itself rlm@8: tagged SLL .it : return f.find(it.rsrc); rlm@8: tagged SRL .it : return f.find(it.rsrc); rlm@8: tagged SRA .it : return f.find(it.rsrc); rlm@8: tagged SLLV .it : return (f.find(it.rsrc) || f.find(it.rshamt)); rlm@8: tagged SRLV .it : return (f.find(it.rsrc) || f.find(it.rshamt)); rlm@8: tagged SRAV .it : return (f.find(it.rsrc) || f.find(it.rshamt)); rlm@8: tagged ADDU .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); rlm@8: tagged SUBU .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); rlm@8: tagged AND .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); rlm@8: tagged OR .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); rlm@8: tagged XOR .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); rlm@8: tagged NOR .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); rlm@8: tagged SLT .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); rlm@8: tagged SLTU .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); rlm@8: rlm@8: rlm@8: // -- Branches -------------------------------------------------- rlm@8: rlm@8: tagged BLEZ .it : return (f.find(it.rsrc)); rlm@8: tagged BGTZ .it : return (f.find(it.rsrc)); rlm@8: tagged BLTZ .it : return (f.find(it.rsrc)); rlm@8: tagged BGEZ .it : return (f.find(it.rsrc)); rlm@8: tagged BEQ .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); rlm@8: tagged BNE .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); rlm@8: rlm@8: // -- Jumps ----------------------------------------------------- rlm@8: rlm@8: tagged J .it : return False; rlm@8: tagged JR .it : return f.find(it.rsrc); rlm@8: tagged JALR .it : return f.find(it.rsrc); rlm@8: tagged JAL .it : return False; rlm@8: rlm@8: // -- Cop0 ------------------------------------------------------ rlm@8: rlm@8: tagged MTC0 .it : return f.find(it.rsrc); rlm@8: tagged MFC0 .it : return False; rlm@8: rlm@8: // -- Illegal --------------------------------------------------- rlm@8: rlm@8: default : return False; rlm@8: rlm@8: endcase rlm@8: endfunction rlm@8: //----------------------------------------------------------- rlm@8: // Reference processor rlm@8: //----------------------------------------------------------- rlm@8: rlm@8: rlm@8: //(* doc = "synthesis attribute ram_style mkProc distributed;" *) rlm@8: //(* synthesize *) rlm@8: rlm@8: module [CONNECTED_MODULE] mkProc( Proc ); rlm@8: rlm@8: //----------------------------------------------------------- rlm@8: // Debug port rlm@8: punk@12: ServerStub_AUDIOCORERRR server_stub <- mkServerStub_AUDIOCORERRR(); rlm@8: rlm@8: rlm@8: //----------------------------------------------------------- rlm@8: // State rlm@8: rlm@8: // Standard processor state rlm@8: rlm@8: Reg#(Addr) pc <- mkReg(32'h00001000); rlm@8: Reg#(Epoch) epoch <- mkReg(0); rlm@8: Reg#(Stage) stage <- mkReg(PCgen); rlm@8: BRFile rf <- mkBRFile; rlm@8: rlm@8: // Branch Prediction rlm@8: BranchPred bp <- mkBranchPred(); rlm@8: FIFO#(PCStat) execpc <- mkLFIFO(); rlm@8: rlm@8: // Pipelines rlm@8: FIFO#(PCStat) pcQ <-mkSizedFIFO(3); rlm@8: SFIFO#(WBResult, Rindx) wbQ <-mkSFIFO(findwbf); rlm@8: rlm@8: Reg#(Bit#(32)) cp0_tohost <- mkReg(0); rlm@8: Reg#(Bit#(32)) cp0_fromhost <- mkReg(0); rlm@8: Reg#(Bool) cp0_statsEn <- mkReg(False); rlm@8: rlm@8: // Memory request/response state rlm@8: rlm@8: FIFO#(InstReq) instReqQ <- mkBFIFO1(); rlm@8: FIFO#(InstResp) instRespQ <- mkFIFO(); rlm@8: rlm@8: FIFO#(DataReq) dataReqQ <- mkBFIFO1(); rlm@8: FIFO#(DataResp) dataRespQ <- mkFIFO(); rlm@8: punk@11: // Audio I/O punk@11: FIFO#(AudioProcessorUnit) inAudioFifo <- mkFIFO; punk@11: FIFO#(AudioProcessorUnit) outAudioFifo <- mkFIFO; punk@11: punk@11: punk@11: // Statistics state (2010) punk@11: // Reg#(Stat) num_cycles <- mkReg(0); punk@11: // Reg#(Stat) num_inst <- mkReg(0); rlm@8: rlm@8: //Or: punk@11: // Statistics state punk@11: STAT num_cycles <- mkStatCounter(`STATS_PROCESSOR_CYCLE_COUNT); punk@11: STAT num_inst <- mkStatCounter(`STATS_PROCESSOR_INST_COUNT); rlm@8: rlm@8: //----------------------------------------------------------- rlm@8: // Rules rlm@8: rlm@8: (* descending_urgency = "exec, pcgen" *) rlm@8: rule pcgen; //( stage == PCgen ); rlm@8: let pc_plus4 = pc + 4; rlm@8: rlm@8: traceTiny("mkProc", "pc",pc); rlm@8: traceTiny("mkProc", "pcgen","P"); rlm@8: instReqQ.enq( LoadReq{ addr:pc, tag:epoch} ); rlm@8: rlm@8: let next_pc = bp.get(pc); rlm@8: if (next_pc matches tagged Valid .npc) rlm@8: begin rlm@8: pcQ.enq(PCStat {qpc:pc, qnxtpc:npc, qepoch:epoch}); rlm@8: pc <= npc; rlm@8: end rlm@8: else rlm@8: begin rlm@8: pcQ.enq(PCStat {qpc:pc, qnxtpc:pc_plus4, qepoch:epoch}); rlm@8: pc <= pc_plus4; rlm@8: end rlm@8: rlm@8: endrule rlm@8: rlm@8: rule discard (instRespQ.first() matches tagged LoadResp .ld rlm@8: &&& ld.tag != epoch); rlm@8: traceTiny("mkProc", "stage", "D"); rlm@8: instRespQ.deq(); rlm@8: endrule rlm@8: rlm@8: (* conflict_free = "exec, writeback" *) rlm@8: rule exec (instRespQ.first() matches tagged LoadResp.ld rlm@8: &&& (ld.tag == epoch) rlm@8: &&& unpack(ld.data) matches .inst rlm@8: &&& !stall(inst, wbQ)); rlm@8: rlm@8: // Some abbreviations rlm@8: let sext = signExtend; rlm@8: let zext = zeroExtend; rlm@8: let sra = signedShiftRight; rlm@8: rlm@8: // Get the instruction rlm@8: rlm@8: instRespQ.deq(); rlm@8: Instr inst rlm@8: = case ( instRespQ.first() ) matches rlm@8: tagged LoadResp .ld : return unpack(ld.data); rlm@8: tagged StoreResp .st : return ?; rlm@8: endcase; rlm@8: rlm@8: // Get the PC info rlm@8: let instrpc = pcQ.first().qpc; rlm@8: let pc_plus4 = instrpc + 4; rlm@8: rlm@8: Bool branchTaken = False; rlm@8: Addr newPC = pc_plus4; rlm@8: rlm@8: // Tracing rlm@8: traceTiny("mkProc", "exec","X"); rlm@8: traceTiny("mkProc", "exInstTiny",inst); rlm@8: traceFull("mkProc", "exInstFull",inst); rlm@8: rlm@8: case ( inst ) matches rlm@8: rlm@8: // -- Memory Ops ------------------------------------------------ rlm@8: rlm@8: tagged LW .it : rlm@8: begin rlm@8: Addr addr = rf.rd1(it.rbase) + sext(it.offset); rlm@8: dataReqQ.enq( LoadReq{ addr:addr, tag:zeroExtend(it.rdst) } ); rlm@8: wbQ.enq(tagged WB_Load it.rdst); rlm@8: end rlm@8: rlm@8: tagged SW .it : rlm@8: begin rlm@8: Addr addr = rf.rd1(it.rbase) + sext(it.offset); rlm@8: dataReqQ.enq( StoreReq{ tag:0, addr:addr, data:rf.rd2(it.rsrc) } ); rlm@8: wbQ.enq(tagged WB_Store); rlm@8: end rlm@8: rlm@8: // -- Simple Ops ------------------------------------------------ rlm@8: rlm@8: tagged ADDIU .it : rlm@8: begin rlm@8: Bit#(32) result = rf.rd1(it.rsrc) + sext(it.imm); rlm@8: wbQ.enq(tagged WB_ALU {data:result, dest:it.rdst}); rlm@8: end rlm@8: tagged SLTI .it : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:slt( rf.rd1(it.rsrc), sext(it.imm) )}); rlm@8: tagged SLTIU .it : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:sltu( rf.rd1(it.rsrc), sext(it.imm) ) }); rlm@8: tagged ANDI .it : rlm@8: begin rlm@8: Bit#(32) zext_it_imm = zext(it.imm); rlm@8: wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(rf.rd1(it.rsrc) & zext_it_imm)} ); rlm@8: end rlm@8: tagged ORI .it : rlm@8: begin rlm@8: Bit#(32) zext_it_imm = zext(it.imm); rlm@8: wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(rf.rd1(it.rsrc) | zext_it_imm)} ); rlm@8: end rlm@8: tagged XORI .it : rlm@8: begin rlm@8: Bit#(32) zext_it_imm = zext(it.imm); rlm@8: wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) ^ zext_it_imm )}); rlm@8: end rlm@8: tagged LUI .it : rlm@8: begin rlm@8: Bit#(32) zext_it_imm = zext(it.imm); rlm@8: wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(zext_it_imm << 32'd16) }); rlm@8: end rlm@8: rlm@8: tagged SLL .it : rlm@8: begin rlm@8: Bit#(32) zext_it_shamt = zext(it.shamt); rlm@8: wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) << zext_it_shamt )} ); rlm@8: end rlm@8: tagged SRL .it : rlm@8: begin rlm@8: Bit#(32) zext_it_shamt = zext(it.shamt); rlm@8: wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) >> zext_it_shamt )}); rlm@8: end rlm@8: tagged SRA .it : rlm@8: begin rlm@8: Bit#(32) zext_it_shamt = zext(it.shamt); rlm@8: wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( rf.rd1(it.rsrc), zext_it_shamt )}); rlm@8: end rlm@8: tagged SLLV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) << rshft(rf.rd2(it.rshamt)) )}); rlm@8: tagged SRLV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) >> rshft(rf.rd2(it.rshamt)) )} ); rlm@8: tagged SRAV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( rf.rd1(it.rsrc), rshft(rf.rd2(it.rshamt)) ) }); rlm@8: tagged ADDU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) + rf.rd2(it.rsrc2) )} ); rlm@8: tagged SUBU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) - rf.rd2(it.rsrc2) )} ); rlm@8: tagged AND .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) & rf.rd2(it.rsrc2) )} ); rlm@8: tagged OR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) | rf.rd2(it.rsrc2) )} ); rlm@8: tagged XOR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) ^ rf.rd2(it.rsrc2) )} ); rlm@8: tagged NOR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(~(rf.rd1(it.rsrc1) | rf.rd2(it.rsrc2)) )} ); rlm@8: tagged SLT .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:slt( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) }); rlm@8: tagged SLTU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sltu( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) }); rlm@8: rlm@8: // -- Branches -------------------------------------------------- rlm@8: rlm@8: tagged BLEZ .it : rlm@8: if ( signedLE( rf.rd1(it.rsrc), 0 ) ) rlm@8: begin rlm@8: newPC = pc_plus4 + (sext(it.offset) << 2); rlm@8: branchTaken = True; rlm@8: end rlm@8: rlm@8: tagged BGTZ .it : rlm@8: if ( signedGT( rf.rd1(it.rsrc), 0 ) ) rlm@8: begin rlm@8: newPC = pc_plus4 + (sext(it.offset) << 2); rlm@8: branchTaken = True; rlm@8: end rlm@8: rlm@8: tagged BLTZ .it : rlm@8: if ( signedLT( rf.rd1(it.rsrc), 0 ) ) rlm@8: begin rlm@8: newPC = pc_plus4 + (sext(it.offset) << 2); rlm@8: branchTaken = True; rlm@8: end rlm@8: rlm@8: tagged BGEZ .it : rlm@8: if ( signedGE( rf.rd1(it.rsrc), 0 ) ) rlm@8: begin rlm@8: newPC = pc_plus4 + (sext(it.offset) << 2); rlm@8: branchTaken = True; rlm@8: end rlm@8: rlm@8: tagged BEQ .it : rlm@8: if ( rf.rd1(it.rsrc1) == rf.rd2(it.rsrc2) ) rlm@8: begin rlm@8: newPC = pc_plus4 + (sext(it.offset) << 2); rlm@8: branchTaken = True; rlm@8: end rlm@8: rlm@8: tagged BNE .it : rlm@8: if ( rf.rd1(it.rsrc1) != rf.rd2(it.rsrc2) ) rlm@8: begin rlm@8: newPC = pc_plus4 + (sext(it.offset) << 2); rlm@8: branchTaken = True; rlm@8: end rlm@8: rlm@8: // -- Jumps ----------------------------------------------------- rlm@8: rlm@8: tagged J .it : rlm@8: begin rlm@8: newPC = { pc_plus4[31:28], it.target, 2'b0 }; rlm@8: branchTaken = True; rlm@8: end rlm@8: rlm@8: tagged JR .it : rlm@8: begin rlm@8: newPC = rf.rd1(it.rsrc); rlm@8: branchTaken = True; rlm@8: end rlm@8: rlm@8: tagged JAL .it : rlm@8: begin rlm@8: wbQ.enq(tagged WB_ALU {dest:31, data:pc_plus4 }); rlm@8: newPC = { pc_plus4[31:28], it.target, 2'b0 }; rlm@8: branchTaken = True; rlm@8: end rlm@8: rlm@8: tagged JALR .it : rlm@8: begin rlm@8: wbQ.enq(tagged WB_ALU {dest:it.rdst, data:pc_plus4 }); rlm@8: newPC = rf.rd1(it.rsrc); rlm@8: branchTaken = True; rlm@8: end rlm@8: rlm@8: // -- Cop0 ------------------------------------------------------ rlm@8: rlm@8: tagged MTC0 .it : rlm@8: begin rlm@8: case ( it.cop0dst ) rlm@8: 5'd10 : cp0_statsEn <= unpack(truncate(rf.rd1(it.rsrc))); rlm@8: 5'd21 : cp0_tohost <= truncate(rf.rd1(it.rsrc)); rlm@8: default : rlm@8: $display( " RTL-ERROR : %m : Illegal MTC0 cop0dst register!" ); rlm@8: endcase rlm@8: wbQ.enq(tagged WB_Host 0); //no idea wwhat this actually should be. rlm@8: end rlm@8: rlm@8: //this is host stuff? rlm@8: tagged MFC0 .it : rlm@8: begin rlm@8: case ( it.cop0src ) rlm@8: // not actually an ALU instruction but don't have the format otherwise rlm@8: 5'd10 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(cp0_statsEn)) }); rlm@8: 5'd20 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_fromhost }); rlm@8: 5'd21 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_tohost }); rlm@8: default : rlm@8: $display( " RTL-ERROR : %m : Illegal MFC0 cop0src register!" ); rlm@8: endcase rlm@8: end rlm@8: rlm@8: // -- Illegal --------------------------------------------------- rlm@8: rlm@8: default : rlm@8: $display( " RTL-ERROR : %m : Illegal instruction !" ); rlm@8: rlm@8: endcase rlm@8: rlm@8: //evaluate branch prediction rlm@8: Addr ppc = pcQ.first().qnxtpc; //predicted branch rlm@8: if (ppc != newPC) //prediction wrong rlm@8: begin rlm@8: epoch <= pcQ.first().qepoch + 1; rlm@8: bp.upd(instrpc, newPC); //update branch predictor rlm@8: pcQ.clear(); rlm@8: pc <= newPC; rlm@8: end rlm@8: else rlm@8: pcQ.deq(); rlm@8: rlm@8: if ( cp0_statsEn ) punk@11: num_inst.incr(); rlm@8: rlm@8: endrule rlm@8: rlm@8: rule writeback; // ( stage == Writeback ); rlm@8: traceTiny("mkProc", "writeback","W"); rlm@8: rlm@8: rlm@8: // get what to do off the writeback queue rlm@8: wbQ.deq(); rlm@8: case (wbQ.first()) matches rlm@8: tagged WB_ALU {data:.res, dest:.rdst} : rf.wr(rdst, res); rlm@8: tagged WB_Load .regWr : rlm@8: begin rlm@8: dataRespQ.deq(); rlm@8: if (dataRespQ.first() matches tagged LoadResp .ld) rlm@8: rf.wr(truncate(ld.tag), ld.data); // no need to use Rindx from queue? Duplicate? rlm@8: end rlm@8: tagged WB_Store : dataRespQ.deq(); rlm@8: tagged WB_Host .dat : noAction; rlm@8: endcase rlm@8: rlm@8: endrule rlm@8: rlm@8: rule inc_num_cycles; rlm@8: if ( cp0_statsEn ) punk@11: num_cycles.incr(); rlm@8: endrule punk@11: punk@11: (* conservative_implicit_conditions *) punk@11: rule handleCPUToHost; punk@11: let req <- server_stub.acceptRequest_ReadCPUToHost(); punk@11: case (req) punk@15: 0: server_stub.sendResponse_ReadCPUToHost(cp0_tohost); punk@11: 1: server_stub.sendResponse_ReadCPUToHost(pc); punk@11: 2: server_stub.sendResponse_ReadCPUToHost(zeroExtend(pack(stage))); punk@11: endcase punk@11: endrule punk@11: punk@11: // for now, we don't do anything. punk@11: rule connectAudioReqResp; rlm@23: $display("rlm: PROCESSOR copies a datum\n"); rlm@23: outAudioFifo.enq(inAudioFifo.first()); rlm@23: inAudioFifo.deq; punk@11: endrule rlm@8: punk@12: // Server items & rules: punk@12: punk@12: rule feedInput; punk@12: let command <- server_stub.acceptRequest_SendUnprocessedStream(); punk@12: AudioProcessorControl ctrl = unpack(truncate(command.ctrl)); rlm@23: $display("rlm: PROCESSOR: recieved data\n"); punk@12: if(ctrl == EndOfFile) punk@12: begin punk@12: inAudioFifo.enq(tagged EndOfFile); punk@12: end punk@12: else punk@12: begin punk@12: inAudioFifo.enq(tagged Sample unpack(truncate(command.sample))); punk@12: end punk@12: endrule punk@12: punk@12: rlm@8: //----------------------------------------------------------- rlm@8: // Methods rlm@8: rlm@8: interface Client imem_client; punk@21: interface Get request = fifoToGet(instReqQ); punk@21: interface Put response = fifoToPut(instRespQ); rlm@8: endinterface rlm@8: rlm@8: interface Client dmem_client; punk@21: interface Get request = fifoToGet(dataReqQ); punk@21: interface Put response = fifoToPut(dataRespQ); rlm@8: endinterface rlm@8: rlm@8: interface Get statsEn_get = toGet(asReg(cp0_statsEn)); rlm@8: punk@12: // interface CPUToHost tohost; punk@12: // method Bit#(32) cpuToHost(int req); punk@12: // return (case (req) punk@12: // 0: cp0_tohost; punk@12: // 1: pc; punk@12: // 2: zeroExtend(pack(stage)); punk@12: // endcase); punk@12: // endmethod punk@12: // endinterface punk@12: punk@21: interface Get sampleOutput = fifoToGet(outAudioFifo); punk@11: rlm@8: endmodule rlm@8: