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1 import RegFile::*;
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2 import RWire::*;
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3 import ProcTypes::*;
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4
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5 `include "asim/provides/low_level_platform_interface.bsh"
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6 `include "asim/provides/soft_connections.bsh"
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7 `include "asim/provides/fpga_components.bsh"
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8 `include "asim/provides/common_services.bsh"
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9
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10 //-----------------------------------------------------------
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11 // Register file module
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12 //-----------------------------------------------------------
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13
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14 interface BRegFile;
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15 method Action wr( Rindx rindx, Bit#(32) data );
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16 method ActionValue#( Bit#(32)) rd1( Rindx rindx );
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17 method ActionValue#( Bit#(32)) rd2( Rindx rindx );
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18 endinterface
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19
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20 (* doc = "synthesis attribute ram_style mkBRegFile distributed;" *)
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21 (* synthesize *)
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22 module mkBRegFile(BRegFile);
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23
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24 LUTRAM#(Rindx, Bit#(32)) rf <- mkLUTRAMU_RegFile();
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25 RWire#(Tuple2#(Rindx, Bit#(32))) rw <-mkRWire();
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26
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27 method Action wr( Rindx rindx, Bit#(32) data );
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28 rf.upd( rindx, data );
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29 rw.wset(tuple2(rindx,data));
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30 endmethod
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31
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32 method ActionValue#(Bit#(32)) rd1 (Rindx r);
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33 if (r == 0) return 0;
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34 else begin
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35 case (rw.wget()) matches
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36 tagged Valid {.wr, .d} :
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37 return (wr == r) ? d : rf.sub(r);
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38 tagged Invalid : return rf.sub(r);
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39 endcase
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40 end
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41 endmethod
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42
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43 method ActionValue#(Bit#(32)) rd2 (Rindx r);
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44 if (r == 0) return 0;
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45 else begin
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46 case (rw.wget()) matches
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47 tagged Valid {.wr, .d} :
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48 return (wr == r) ? d : rf.sub(r);
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49 tagged Invalid : return rf.sub(r);
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50 endcase
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51 end
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52 endmethod
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53
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54 endmodule
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