1.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     1.2 +++ b/modules/bluespec/Pygar/core/#AudioCoreRRR.cpp#	Fri Apr 30 09:03:10 2010 -0400
     1.3 @@ -0,0 +1,116 @@
     1.4 +#include <cstdio>
     1.5 +#include <cstdlib>
     1.6 +#include <iostream>
     1.7 +#include <iomanip>
     1.8 +#include <stdio.h>
     1.9 +#include <sys/stat.h>
    1.10 +
    1.11 +#include "asim/rrr/service_ids.h"
    1.12 +
    1.13 +#include "asim/provides/connected_application.h"
    1.14 +
    1.15 +using namespace std;
    1.16 +
    1.17 +// ===== service instantiation =====
    1.18 +AUDIOCORERRR_SERVER_CLASS AUDIOCORERRR_SERVER_CLASS::instance;
    1.19 +
    1.20 +// constructor
    1.21 +AUDIOCORERRR_SERVER_CLASS::AUDIOCORERRR_SERVER_CLASS() :
    1.22 +  serverStub(new AUDIOCORERRR_SERVER_STUB_CLASS(this))
    1.23 +{
    1.24 +    // instantiate stub
    1.25 +    printf("AUDIOCORERRR init called\n");
    1.26 +    outputFile = NULL;
    1.27 +    memory = NULL;
    1.28 +    fflush(stdout);
    1.29 +}
    1.30 +
    1.31 +// destructor
    1.32 +AUDIOCORERRR_SERVER_CLASS::~AUDIOCORERRR_SERVER_CLASS()
    1.33 +{
    1.34 +    Cleanup();
    1.35 +}
    1.36 +
    1.37 +// init
    1.38 +void
    1.39 +AUDIOCORERRR_SERVER_CLASS::Init(PLATFORMS_MODULE p)
    1.40 +{
    1.41 +    parent = p;
    1.42 +}
    1.43 +
    1.44 +// uninit
    1.45 +void
    1.46 +AUDIOCORERRR_SERVER_CLASS::Uninit()
    1.47 +{
    1.48 +    Cleanup();
    1.49 +}
    1.50 +
    1.51 +// cleanup
    1.52 +void
    1.53 +AUDIOCORERRR_SERVER_CLASS::Cleanup()
    1.54 +{
    1.55 +    delete serverStub;
    1.56 +}
    1.57 +
    1.58 +
    1.59 +//
    1.60 +// RRR service methods
    1.61 +//
    1.62 +
    1.63 +UINT32
    1.64 +AUDIOCORERRR_SERVER_CLASS::MemoryRequestLoad (UINT32 address)
    1.65 +{
    1.66 +  UINT32 returnVal;
    1.67 +  
    1.68 +  if(memory == NULL) {
    1.69 +    memory = new FUNCP_SIMULATED_MEMORY_CLASS();
    1.70 +  }
    1.71 +
    1.72 + 
    1.73 +  memory->Read(0,(UINT64) address, sizeof(UINT32), &returnVal); 
    1.74 +  return returnVal;
    1.75 +}
    1.76 +
    1.77 +void
    1.78 +AUDIOCORERRR_SERVER_CLASS::MemoryRequestStore (UINT32 address, UINT32 data)
    1.79 +{
    1.80 +  if(memory == NULL) {
    1.81 +    memory = new FUNCP_SIMULATED_MEMORY_CLASS();
    1.82 +  }
    1.83 +
    1.84 +  memory->Write(0,(UINT64) address, sizeof(UINT32), &data); 
    1.85 +}
    1.86 +
    1.87 +void
    1.88 +AUDIOCORERRR_SERVER_CLASS::SendProcessedStream(UINT16 control, UINT16 data)
    1.89 +{
    1.90 +
    1.91 +  AudioProcessorControl audioProcessorControl = (AudioProcessorControl) control;
    1.92 +  switch(control) {
    1.93 +    case EndOfFile:
    1.94 +      if(outputFile != NULL) {
    1.95 +        fflush(outputFile);
    1.96 +        fclose(outputFile);
    1.97 +        outputFile = NULL;
    1.98 +      } else {
    1.99 +        outputFile = fopen("out_hw.pcm","w");
   1.100 +        assert(outputFile);
   1.101 +        fflush(outputFile);
   1.102 +        fclose(outputFile);
   1.103 +      }
   1.104 +
   1.105 +      // Long term this should be in the data portion.  But until I have code running, keep it here.
   1.106 +      CONNECTED_APPLICATION_CLASS::EndSimulation(); 
   1.107 +    break;
   1.108 +
   1.109 +    case Data:
   1.110 +      if(outputFile == NULL) {
   1.111 +        outputFile = fopen("out_hw.pcm","w");
   1.112 +        assert(outputFile);
   1.113 +      }
   1.114 +
   1.115 +      CONNECTED_APPLICATION_CLASS::UpdateSemaphore();  
   1.116 +      fwrite(&data, 2,1 , outputFile);
   1.117 +    break;
   1.118 +  }
   1.119 +}

     2.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     2.2 +++ b/modules/bluespec/Pygar/core/#Processor.bsv#	Fri Apr 30 09:03:10 2010 -0400
     2.3 @@ -0,0 +1,625 @@
     2.4 +/// The MIT License
     2.5 +
     2.6 +// Copyright (c) 2009 Massachusetts Institute of Technology
     2.7 +
     2.8 +// Permission is hereby granted, free of charge, to any person obtaining a copy
     2.9 +// of this software and associated documentation files (the "Software"), to deal
    2.10 +// in the Software without restriction, including without limitation the rights
    2.11 +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
    2.12 +// copies of the Software, and to permit persons to whom the Software is
    2.13 +// furnished to do so, subject to the following conditions:
    2.14 +
    2.15 +// The above copyright notice and this permission notice shall be included in
    2.16 +// all copies or substantial portions of the Software.
    2.17 +
    2.18 +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    2.19 +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
    2.20 +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
    2.21 +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
    2.22 +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
    2.23 +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
    2.24 +// THE SOFTWARE.
    2.25 +
    2.26 +
    2.27 +import Connectable::*;
    2.28 +import GetPut::*;
    2.29 +import ClientServer::*;
    2.30 +import RegFile::*;
    2.31 +
    2.32 +import FIFO::*;
    2.33 +import FIFOF::*;
    2.34 +import SFIFO::*;
    2.35 +import RWire::*;
    2.36 +import Trace::*;
    2.37 +import BFIFO::*;
    2.38 +import ProcTypes::*;
    2.39 +import BRegFile::*;
    2.40 +import BranchPred::*;
    2.41 +//import PathTypes::*;  This is only there to force the debugging
    2.42 +
    2.43 +//AWB includes
    2.44 +`include "asim/provides/low_level_platform_interface.bsh"
    2.45 +`include "asim/provides/soft_connections.bsh"
    2.46 +`include "asim/provides/common_services.bsh"
    2.47 +
    2.48 +// Local includes
    2.49 +//`include "asim/provides/processor_library.bsh" (included above directly)
    2.50 +`include "asim/rrr/remote_server_stub_AUDIOCORERRR.bsh"
    2.51 +`include "asim/provides/common_services.bsh"
    2.52 +`include "asim/dict/STATS_PROCESSOR.bsh"
    2.53 +`include "asim/provides/processor_library.bsh"
    2.54 +
    2.55 +// Local includes. Look for the correspondingly named .awb files
    2.56 +// workspace/labs/src/mit-6.375/modules/bluespec/mit-6.375/common/
    2.57 +// to find the actual Bluespec files which are used to generate
    2.58 +// these includes.  These files are specific to this audio processing
    2.59 +// pipeline
    2.60 +
    2.61 +`include "asim/provides/audio_pipe_types.bsh"
    2.62 +
    2.63 +//interface CPUToHost;
    2.64 +//  method Bit#(32) cpuToHost(int req);
    2.65 +//endinterface
    2.66 +
    2.67 +interface Proc;
    2.68 +
    2.69 +  // Interface from processor to caches
    2.70 +  interface Client#(DataReq,DataResp) dmem_client;
    2.71 +  interface Client#(InstReq,InstResp) imem_client;
    2.72 +
    2.73 +  // Interface for enabling/disabling statistics on the rest of the core
    2.74 +  interface Get#(Bool) statsEn_get;
    2.75 +
    2.76 +//  // Interface to host
    2.77 +//  interface CPUToHost tohost;
    2.78 +
    2.79 +  // Interface to Audio Pipeline
    2.80 +  interface Get#(AudioProcessorUnit) sampleOutput;
    2.81 +	
    2.82 +endinterface
    2.83 +
    2.84 +//The full interface for this is as below in the common file for audioProcessorTypes.bsv
    2.85 +//interface AudioOut;
    2.86 +//  interface Get#(AudioProcessorUnit) audioSampleOutput;
    2.87 +//endinterface
    2.88 +
    2.89 +//interface AudioIn;
    2.90 +//  interface Put#(AudioProcessorUnit) audioSampleInput;
    2.91 +//endinterface	
    2.92 +
    2.93 +typedef enum { PCgen, Exec, Writeback } Stage deriving(Eq,Bits);
    2.94 +
    2.95 +//-----------------------------------------------------------
    2.96 +// Register file module
    2.97 +//-----------------------------------------------------------
    2.98 +
    2.99 +interface BRFile;
   2.100 +   method Action   wr( Rindx rindx, Bit#(32) data );
   2.101 +   method Bit#(32) rd1( Rindx rindx );
   2.102 +   method Bit#(32) rd2( Rindx rindx );
   2.103 +endinterface
   2.104 +
   2.105 +module mkBRFile( BRFile );
   2.106 +   
   2.107 +   RegFile#(Rindx,Bit#(32)) rfile <- mkBRegFile();
   2.108 +   
   2.109 +   method Action wr( Rindx rindx, Bit#(32) data );
   2.110 +      rfile.upd( rindx, data );
   2.111 +   endmethod
   2.112 +   
   2.113 +   method Bit#(32) rd1( Rindx rindx );
   2.114 +      return ( rindx == 0 ) ? 0 : rfile.sub(rindx);
   2.115 +   endmethod
   2.116 +   
   2.117 +   method Bit#(32) rd2( Rindx rindx );
   2.118 +      return ( rindx == 0 ) ? 0 : rfile.sub(rindx);
   2.119 +   endmethod
   2.120 +
   2.121 +endmodule
   2.122 +
   2.123 +//-----------------------------------------------------------
   2.124 +// Helper functions
   2.125 +//-----------------------------------------------------------
   2.126 +
   2.127 +function Bit#(32) slt( Bit#(32) val1, Bit#(32) val2 );
   2.128 +   return zeroExtend( pack( signedLT(val1,val2) ) );
   2.129 +endfunction
   2.130 +
   2.131 +function Bit#(32) sltu( Bit#(32) val1, Bit#(32) val2 );
   2.132 +   return zeroExtend( pack( val1 < val2 ) );
   2.133 +endfunction
   2.134 +
   2.135 +function Bit#(32) rshft( Bit#(32) val );
   2.136 +   return zeroExtend(val[4:0]);
   2.137 +endfunction
   2.138 +
   2.139 +
   2.140 +//-----------------------------------------------------------
   2.141 +// Find funct for wbQ
   2.142 +//-----------------------------------------------------------
   2.143 +function Bool findwbf(Rindx fVal, WBResult cmpVal);
   2.144 +  case (cmpVal) matches   
   2.145 +     tagged WB_ALU  {data:.res, dest:.rd} :
   2.146 +	return (fVal == rd);
   2.147 +     tagged WB_Load .rd  :
   2.148 +	return (fVal == rd);
   2.149 +     tagged WB_Store .st :
   2.150 +	return False;
   2.151 +     tagged WB_Host .x   :
   2.152 +	return False;
   2.153 +  endcase
   2.154 +endfunction
   2.155 +
   2.156 +     
   2.157 +//-----------------------------------------------------------
   2.158 +// Stall funct for wbQ
   2.159 +//-----------------------------------------------------------
   2.160 +function Bool stall(Instr inst, SFIFO#(WBResult, Rindx) f);
   2.161 +   case (inst) matches
   2.162 +      	 // -- Memory Ops ------------------------------------------------      
   2.163 +      tagged LW .it :
   2.164 +	 return f.find(it.rbase);
   2.165 +      tagged SW {rsrc:.dreg, rbase:.addr, offset:.o} :
   2.166 +	 return (f.find(addr) ||  f.find2(dreg));
   2.167 +
   2.168 +	 // -- Simple Ops ------------------------------------------------      
   2.169 +      tagged ADDIU .it : return f.find(it.rsrc);
   2.170 +      tagged SLTI  .it : return f.find(it.rsrc);
   2.171 +      tagged SLTIU .it : return f.find(it.rsrc);
   2.172 +      tagged ANDI  .it : return f.find(it.rsrc);
   2.173 +      tagged ORI   .it : return f.find(it.rsrc);
   2.174 +      tagged XORI  .it : return f.find(it.rsrc);
   2.175 +      
   2.176 +      tagged LUI   .it : return f.find(it.rdst);  //this rds/wrs itself
   2.177 +      tagged SLL   .it : return f.find(it.rsrc);
   2.178 +      tagged SRL   .it : return f.find(it.rsrc);
   2.179 +      tagged SRA   .it : return f.find(it.rsrc);
   2.180 +      tagged SLLV  .it : return (f.find(it.rsrc) || f.find(it.rshamt));
   2.181 +      tagged SRLV  .it : return (f.find(it.rsrc) || f.find(it.rshamt));
   2.182 +      tagged SRAV  .it : return (f.find(it.rsrc) || f.find(it.rshamt));
   2.183 +      tagged ADDU  .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
   2.184 +      tagged SUBU  .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
   2.185 +      tagged AND   .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
   2.186 +      tagged OR    .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
   2.187 +      tagged XOR   .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
   2.188 +      tagged NOR   .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
   2.189 +      tagged SLT   .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
   2.190 +      tagged SLTU  .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
   2.191 +   
   2.192 +
   2.193 +      // -- Branches --------------------------------------------------
   2.194 +    
   2.195 +      tagged BLEZ  .it : return (f.find(it.rsrc));
   2.196 +      tagged BGTZ  .it : return (f.find(it.rsrc));
   2.197 +      tagged BLTZ  .it : return (f.find(it.rsrc));
   2.198 +      tagged BGEZ  .it : return (f.find(it.rsrc));
   2.199 +      tagged BEQ   .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
   2.200 +      tagged BNE   .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
   2.201 +      
   2.202 +      // -- Jumps -----------------------------------------------------
   2.203 +      
   2.204 +      tagged J     .it : return False;
   2.205 +      tagged JR    .it : return f.find(it.rsrc);
   2.206 +      tagged JALR  .it : return f.find(it.rsrc);
   2.207 +      tagged JAL   .it : return False;
   2.208 +      
   2.209 +      // -- Cop0 ------------------------------------------------------
   2.210 +      
   2.211 +      tagged MTC0  .it : return f.find(it.rsrc);      
   2.212 +      tagged MFC0  .it : return False; 
   2.213 +
   2.214 +      // -- Illegal ---------------------------------------------------
   2.215 +
   2.216 +      default : return False;
   2.217 +
   2.218 +    endcase
   2.219 +endfunction
   2.220 +//-----------------------------------------------------------
   2.221 +// Reference processor
   2.222 +//-----------------------------------------------------------
   2.223 +
   2.224 +
   2.225 +//(* doc = "synthesis attribute ram_style mkProc distributed;" *)
   2.226 +//(* synthesize *)
   2.227 +
   2.228 +module  [CONNECTED_MODULE] mkProc( Proc );
   2.229 +
   2.230 +   //-----------------------------------------------------------
   2.231 +   // Debug port
   2.232 +   
   2.233 +   ServerStub_AUDIOCORERRR server_stub <- mkServerStub_AUDIOCORERRR();   
   2.234 +
   2.235 +   
   2.236 +   //-----------------------------------------------------------
   2.237 +   // State
   2.238 +
   2.239 +   // Standard processor state
   2.240 +   
   2.241 +   Reg#(Addr)  pc    <- mkReg(32'h00001000);
   2.242 +   Reg#(Epoch) epoch <- mkReg(0);
   2.243 +   Reg#(Stage) stage <- mkReg(PCgen);
   2.244 +   BRFile      rf    <- mkBRFile;
   2.245 +
   2.246 +   // Branch Prediction
   2.247 +   BranchPred               bp <- mkBranchPred();
   2.248 +   FIFO#(PCStat)        execpc <- mkLFIFO();
   2.249 +   
   2.250 +   // Pipelines
   2.251 +   FIFO#(PCStat)           pcQ <-mkSizedFIFO(3);
   2.252 +   SFIFO#(WBResult, Rindx) wbQ <-mkSFIFO(findwbf);
   2.253 +
   2.254 +   Reg#(Bit#(32)) cp0_tohost   <- mkReg(0);
   2.255 +   Reg#(Bit#(32)) cp0_fromhost <- mkReg(0);
   2.256 +   Reg#(Bool)     cp0_statsEn  <- mkReg(False);
   2.257 +
   2.258 +   // Memory request/response state
   2.259 +   
   2.260 +   FIFO#(InstReq)  instReqQ    <- mkBFIFO1();
   2.261 +   FIFO#(InstResp) instRespQ   <- mkFIFO();
   2.262 +
   2.263 +   FIFO#(DataReq)  dataReqQ    <- mkBFIFO1();
   2.264 +   FIFO#(DataResp) dataRespQ   <- mkFIFO();
   2.265 +
   2.266 +   // Audio I/O
   2.267 +   FIFO#(AudioProcessorUnit) inAudioFifo <- mkFIFO;
   2.268 +   FIFO#(AudioProcessorUnit) outAudioFifo <- mkFIFO;
   2.269 +
   2.270 +
   2.271 +   // Statistics state (2010)
   2.272 +//   Reg#(Stat) num_cycles <- mkReg(0);
   2.273 +//   Reg#(Stat) num_inst <- mkReg(0);
   2.274 +
   2.275 +   //Or:
   2.276 +   // Statistics state
   2.277 +   STAT num_cycles <- mkStatCounter(`STATS_PROCESSOR_CYCLE_COUNT);
   2.278 +   STAT num_inst <- mkStatCounter(`STATS_PROCESSOR_INST_COUNT);
   2.279 +
   2.280 +   //-----------------------------------------------------------
   2.281 +   // Rules
   2.282 +
   2.283 +   (* descending_urgency = "exec, pcgen" *)
   2.284 +   rule pcgen; //( stage == PCgen );
   2.285 +      let pc_plus4 = pc + 4;
   2.286 +
   2.287 +      traceTiny("mkProc", "pc",pc);
   2.288 +      traceTiny("mkProc", "pcgen","P");
   2.289 +      instReqQ.enq( LoadReq{ addr:pc, tag:epoch} );
   2.290 +      
   2.291 +      let next_pc = bp.get(pc);
   2.292 +      if (next_pc matches tagged Valid .npc) 
   2.293 +	begin
   2.294 +	   pcQ.enq(PCStat {qpc:pc, qnxtpc:npc, qepoch:epoch});
   2.295 +	   pc <= npc;
   2.296 +	end
   2.297 +     else
   2.298 +	 begin
   2.299 +	   pcQ.enq(PCStat {qpc:pc, qnxtpc:pc_plus4, qepoch:epoch});
   2.300 +	   pc <= pc_plus4;
   2.301 +	 end
   2.302 +      
   2.303 +   endrule
   2.304 +
   2.305 +   rule discard (instRespQ.first() matches tagged LoadResp .ld
   2.306 +					      &&& ld.tag != epoch);
   2.307 +      traceTiny("mkProc", "stage", "D");
   2.308 +      instRespQ.deq();
   2.309 +   endrule
   2.310 +
   2.311 +   (* conflict_free = "exec, writeback" *)		      
   2.312 +   rule exec (instRespQ.first() matches tagged LoadResp.ld
   2.313 +	      &&& (ld.tag == epoch)
   2.314 +	      &&& unpack(ld.data) matches .inst
   2.315 +              &&& !stall(inst, wbQ));
   2.316 +
   2.317 +      // Some abbreviations
   2.318 +      let sext = signExtend;
   2.319 +      let zext = zeroExtend;
   2.320 +      let sra  = signedShiftRight;
   2.321 +      
   2.322 +      // Get the instruction
   2.323 +      
   2.324 +      instRespQ.deq();
   2.325 +      Instr inst 
   2.326 +      = case ( instRespQ.first() ) matches
   2.327 +	   tagged LoadResp  .ld : return unpack(ld.data);
   2.328 +	   tagged StoreResp .st : return ?;
   2.329 +	endcase;
   2.330 +
   2.331 +      // Get the PC info
   2.332 +      let instrpc = pcQ.first().qpc;
   2.333 +      let pc_plus4 = instrpc + 4;
   2.334 +      
   2.335 +      Bool branchTaken = False;
   2.336 +      Addr newPC = pc_plus4;
   2.337 +
   2.338 +      // Tracing
   2.339 +      traceTiny("mkProc", "exec","X");
   2.340 +      traceTiny("mkProc", "exInstTiny",inst);
   2.341 +      traceFull("mkProc", "exInstFull",inst);
   2.342 +
   2.343 +      case ( inst ) matches
   2.344 +
   2.345 +	 // -- Memory Ops ------------------------------------------------      
   2.346 +
   2.347 +	 tagged LW .it : 
   2.348 +	    begin
   2.349 +               Addr addr = rf.rd1(it.rbase) + sext(it.offset);
   2.350 +               dataReqQ.enq( LoadReq{ addr:addr, tag:zeroExtend(it.rdst) } );
   2.351 +               wbQ.enq(tagged WB_Load it.rdst);
   2.352 +	    end
   2.353 +
   2.354 +	 tagged SW .it : 
   2.355 +	    begin
   2.356 +               Addr addr = rf.rd1(it.rbase) + sext(it.offset);
   2.357 +               dataReqQ.enq( StoreReq{ tag:0, addr:addr, data:rf.rd2(it.rsrc) } );
   2.358 +               wbQ.enq(tagged WB_Store);
   2.359 +	    end
   2.360 +
   2.361 +	 // -- Simple Ops ------------------------------------------------      
   2.362 +
   2.363 +	 tagged ADDIU .it : 
   2.364 +	    begin
   2.365 +	       Bit#(32) result = rf.rd1(it.rsrc) + sext(it.imm);
   2.366 +	       wbQ.enq(tagged WB_ALU {data:result, dest:it.rdst});
   2.367 +	    end
   2.368 +	 tagged SLTI  .it : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:slt( rf.rd1(it.rsrc), sext(it.imm) )});
   2.369 +	 tagged SLTIU .it : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:sltu( rf.rd1(it.rsrc), sext(it.imm) ) });
   2.370 +	 tagged ANDI  .it : 
   2.371 +	    begin
   2.372 +	       Bit#(32) zext_it_imm = zext(it.imm);
   2.373 +	       wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(rf.rd1(it.rsrc) & zext_it_imm)} );
   2.374 +	    end
   2.375 +	 tagged ORI   .it : 
   2.376 +	    begin
   2.377 +	       Bit#(32) zext_it_imm = zext(it.imm);
   2.378 +	       wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(rf.rd1(it.rsrc) | zext_it_imm)} );
   2.379 +	    end
   2.380 +	 tagged XORI  .it : 
   2.381 +	    begin
   2.382 +	       Bit#(32) zext_it_imm = zext(it.imm);
   2.383 +	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) ^ zext_it_imm )});
   2.384 +	    end
   2.385 +	 tagged LUI   .it : 
   2.386 +	    begin
   2.387 +	       Bit#(32) zext_it_imm = zext(it.imm);
   2.388 +	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(zext_it_imm << 32'd16) });
   2.389 +	    end
   2.390 +	 
   2.391 +	 tagged SLL   .it : 
   2.392 +	    begin
   2.393 +	       Bit#(32) zext_it_shamt = zext(it.shamt);
   2.394 +	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) << zext_it_shamt )} );
   2.395 +	    end
   2.396 +	 tagged SRL   .it : 
   2.397 +	    begin
   2.398 +	       Bit#(32) zext_it_shamt = zext(it.shamt);
   2.399 +	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) >> zext_it_shamt )});
   2.400 +	    end
   2.401 +	 tagged SRA   .it : 
   2.402 +	    begin
   2.403 +	       Bit#(32) zext_it_shamt = zext(it.shamt);
   2.404 +	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( rf.rd1(it.rsrc), zext_it_shamt )});
   2.405 +	    end
   2.406 +	 tagged SLLV  .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) << rshft(rf.rd2(it.rshamt)) )});
   2.407 +	 tagged SRLV  .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) >> rshft(rf.rd2(it.rshamt)) )} );
   2.408 +	 tagged SRAV  .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( rf.rd1(it.rsrc), rshft(rf.rd2(it.rshamt)) ) });
   2.409 +	 tagged ADDU  .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) + rf.rd2(it.rsrc2) )} );
   2.410 +	 tagged SUBU  .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) - rf.rd2(it.rsrc2) )} );
   2.411 +	 tagged AND   .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) & rf.rd2(it.rsrc2) )} );
   2.412 +	 tagged OR    .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) | rf.rd2(it.rsrc2) )} );
   2.413 +	 tagged XOR   .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) ^ rf.rd2(it.rsrc2) )} );
   2.414 +	 tagged NOR   .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(~(rf.rd1(it.rsrc1) | rf.rd2(it.rsrc2)) )} );
   2.415 +	 tagged SLT   .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:slt( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) });
   2.416 +	 tagged SLTU  .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sltu( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) });
   2.417 +
   2.418 +	 // -- Branches --------------------------------------------------
   2.419 +
   2.420 +	 tagged BLEZ  .it : 
   2.421 +            if ( signedLE( rf.rd1(it.rsrc), 0 ) )
   2.422 +	       begin
   2.423 +		  newPC = pc_plus4 + (sext(it.offset) << 2);
   2.424 +		  branchTaken = True;
   2.425 +	       end
   2.426 +
   2.427 +	 tagged BGTZ  .it : 
   2.428 +            if ( signedGT( rf.rd1(it.rsrc), 0 ) ) 
   2.429 +               begin 
   2.430 +		  newPC = pc_plus4 + (sext(it.offset) << 2);
   2.431 +		  branchTaken = True;
   2.432 +	       end
   2.433 +
   2.434 +	 tagged BLTZ  .it : 
   2.435 +            if ( signedLT( rf.rd1(it.rsrc), 0 ) )
   2.436 +               begin 
   2.437 +		  newPC = pc_plus4 + (sext(it.offset) << 2);
   2.438 +		  branchTaken = True;
   2.439 +	       end
   2.440 +		  
   2.441 +	 tagged BGEZ  .it : 
   2.442 +            if ( signedGE( rf.rd1(it.rsrc), 0 ) )
   2.443 +               begin 
   2.444 +		  newPC = pc_plus4 + (sext(it.offset) << 2);		  
   2.445 +		  branchTaken = True;
   2.446 +	       end
   2.447 +
   2.448 +      tagged BEQ   .it : 
   2.449 +        if ( rf.rd1(it.rsrc1) == rf.rd2(it.rsrc2) )
   2.450 +          begin 
   2.451 +	     newPC = pc_plus4 + (sext(it.offset) << 2);
   2.452 +	     branchTaken = True;
   2.453 +	  end
   2.454 +
   2.455 +      tagged BNE   .it : 
   2.456 +        if ( rf.rd1(it.rsrc1) != rf.rd2(it.rsrc2) )
   2.457 +          begin 
   2.458 +	     newPC = pc_plus4 + (sext(it.offset) << 2);
   2.459 +	     branchTaken = True;
   2.460 +	  end
   2.461 +
   2.462 +      // -- Jumps -----------------------------------------------------
   2.463 +      
   2.464 +      tagged J     .it : 
   2.465 +        begin 
   2.466 +	   newPC = { pc_plus4[31:28], it.target, 2'b0 };
   2.467 +	   branchTaken = True;
   2.468 +	end
   2.469 +      
   2.470 +      tagged JR    .it : 
   2.471 +        begin 
   2.472 +	   newPC = rf.rd1(it.rsrc);
   2.473 +	   branchTaken = True;
   2.474 +	end
   2.475 +
   2.476 +      tagged JAL   .it : 
   2.477 +       begin
   2.478 +          wbQ.enq(tagged WB_ALU {dest:31, data:pc_plus4 });
   2.479 +          newPC = { pc_plus4[31:28], it.target, 2'b0 };		  
   2.480 +	  branchTaken = True;
   2.481 +       end
   2.482 +
   2.483 +      tagged JALR  .it : 
   2.484 +       begin
   2.485 +          wbQ.enq(tagged WB_ALU {dest:it.rdst, data:pc_plus4 });
   2.486 +          newPC = rf.rd1(it.rsrc);
   2.487 +	  branchTaken = True;
   2.488 +       end
   2.489 +
   2.490 +      // -- Cop0 ------------------------------------------------------
   2.491 +      
   2.492 +      tagged MTC0  .it : 
   2.493 +	 begin
   2.494 +            case ( it.cop0dst )
   2.495 +	       5'd10 : cp0_statsEn <= unpack(truncate(rf.rd1(it.rsrc)));
   2.496 +	       5'd21 : cp0_tohost  <= truncate(rf.rd1(it.rsrc));
   2.497 +	       default :
   2.498 +	       $display( " RTL-ERROR : %m : Illegal MTC0 cop0dst register!" );
   2.499 +	    endcase
   2.500 +	    wbQ.enq(tagged WB_Host 0); //no idea wwhat this actually should be.
   2.501 +	 end
   2.502 +
   2.503 +//this is host stuff?
   2.504 +      tagged MFC0  .it :
   2.505 +	 begin
   2.506 +            case ( it.cop0src )
   2.507 +	    // not actually an ALU instruction but don't have the format otherwise
   2.508 +               5'd10 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(cp0_statsEn)) });
   2.509 +               5'd20 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_fromhost });
   2.510 +               5'd21 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_tohost   });
   2.511 +              default : 
   2.512 +                $display( " RTL-ERROR : %m : Illegal MFC0 cop0src register!" );
   2.513 +            endcase
   2.514 +	end
   2.515 +
   2.516 +      // -- Illegal ---------------------------------------------------
   2.517 +
   2.518 +      default : 
   2.519 +        $display( " RTL-ERROR : %m : Illegal instruction !" );
   2.520 +
   2.521 +    endcase
   2.522 +
   2.523 +//evaluate branch prediction
   2.524 +     Addr ppc = pcQ.first().qnxtpc; //predicted branch
   2.525 +     if (ppc != newPC) //prediction wrong
   2.526 +       begin
   2.527 +	  epoch <= pcQ.first().qepoch + 1;
   2.528 +	  bp.upd(instrpc, newPC); //update branch predictor
   2.529 +	  pcQ.clear();
   2.530 +	  pc <= newPC;
   2.531 +       end
   2.532 +     else
   2.533 +	pcQ.deq();
   2.534 +
   2.535 +    if ( cp0_statsEn )
   2.536 +      num_inst.incr();
   2.537 +
   2.538 +  endrule
   2.539 +
   2.540 +  rule writeback; // ( stage == Writeback );
   2.541 +     traceTiny("mkProc", "writeback","W");
   2.542 +     
   2.543 +
   2.544 +    // get what to do off the writeback queue
   2.545 +     wbQ.deq();
   2.546 +     case (wbQ.first()) matches
   2.547 +	tagged WB_ALU {data:.res, dest:.rdst} : rf.wr(rdst, res);
   2.548 +	tagged WB_Load .regWr : 
   2.549 +	   begin
   2.550 +	      dataRespQ.deq();
   2.551 +	      if (dataRespQ.first() matches tagged LoadResp .ld)
   2.552 +		rf.wr(truncate(ld.tag), ld.data); // no need to use Rindx from queue?  Duplicate?
   2.553 +	   end
   2.554 +	tagged WB_Store : dataRespQ.deq();
   2.555 +	tagged WB_Host .dat : noAction;
   2.556 +     endcase
   2.557 +           
   2.558 +  endrule
   2.559 +
   2.560 +  rule inc_num_cycles;
   2.561 +    if ( cp0_statsEn )
   2.562 +      num_cycles.incr();
   2.563 +  endrule
   2.564 +
   2.565 +(* conservative_implicit_conditions *)
   2.566 +  rule handleCPUToHost;
   2.567 +   let req <- server_stub.acceptRequest_ReadCPUToHost();
   2.568 +    case (req)
   2.569 +     0: server_stub.sendResponse_ReadCPUToHost(cp0_tohost);
   2.570 +     1: server_stub.sendResponse_ReadCPUToHost(pc);
   2.571 +     2: server_stub.sendResponse_ReadCPUToHost(zeroExtend(pack(stage)));
   2.572 +    endcase
   2.573 +  endrule
   2.574 +
   2.575 + // for now, we don't do anything.
   2.576 +  rule connectAudioReqResp;
   2.577 +//    $display("rlm: PROCESSOR copies a datum\n");
   2.578 +    outAudioFifo.enq(inAudioFifo.first());
   2.579 +    inAudioFifo.deq;
   2.580 +  endrule
   2.581 +
   2.582 +  // Server items & rules:
   2.583 +   
   2.584 +   rule feedInput;
   2.585 +     let command <- server_stub.acceptRequest_SendUnprocessedStream();
   2.586 +     AudioProcessorControl ctrl = unpack(truncate(command.ctrl));
   2.587 +     if(ctrl == EndOfFile)
   2.588 +	begin
   2.589 +//	  $display("lsp: PROCESSOR received EOF   ");
   2.590 +          inAudioFifo.enq(tagged EndOfFile);
   2.591 +       end
   2.592 +     else 
   2.593 +	begin
   2.594 +//	  $display("lsp: PROCESSOR received Data   ");
   2.595 +          inAudioFifo.enq(tagged Sample unpack(truncate(command.sample)));
   2.596 +       end
   2.597 +   endrule     
   2.598 +  
   2.599 + 
   2.600 +  //-----------------------------------------------------------
   2.601 +  // Methods
   2.602 +
   2.603 +  interface Client imem_client;
   2.604 +    interface Get request  = fifoToGet(instReqQ);
   2.605 +    interface Put response = fifoToPut(instRespQ);
   2.606 +  endinterface
   2.607 +
   2.608 +  interface Client dmem_client;
   2.609 +    interface Get request  = fifoToGet(dataReqQ);
   2.610 +    interface Put response = fifoToPut(dataRespQ);
   2.611 +  endinterface
   2.612 +
   2.613 +  interface Get statsEn_get = toGet(asReg(cp0_statsEn));
   2.614 +
   2.615 +//  interface CPUToHost tohost;
   2.616 +//    method Bit#(32) cpuToHost(int req);
   2.617 +//      return (case (req)
   2.618 +//       0: cp0_tohost;
   2.619 +//       1: pc;
   2.620 +//       2: zeroExtend(pack(stage));
   2.621 +//      endcase);
   2.622 +//    endmethod
   2.623 +//  endinterface
   2.624 +     
   2.625 +  interface Get sampleOutput = fifoToGet(outAudioFifo);
   2.626 +
   2.627 +endmodule
   2.628 +

     3.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     3.2 +++ b/modules/bluespec/Pygar/core/#trace.awb#	Fri Apr 30 09:03:10 2010 -0400
     3.3 @@ -0,0 +1,10 @@
     3.4 +%name Trace 
     3.5 +%desc Round-robin memory arbiter 
     3.6 +
     3.7 +%provides mem_arb
     3.8 +
     3.9 +%attributes 6_375
    3.10 +
    3.11 +%public MemArb.bsv
    3.12 +
    3.13 +

     4.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     4.2 +++ b/modules/bluespec/Pygar/core/ProcTrace.bsv~	Fri Apr 30 09:03:10 2010 -0400
     4.3 @@ -0,0 +1,375 @@
     4.4 +import Trace::*;
     4.5 +
     4.6 +
     4.7 +//----------------------------------------------------------------------
     4.8 +// Other typedefs
     4.9 +//----------------------------------------------------------------------
    4.10 +
    4.11 +typedef Bit#(32) Addr;
    4.12 +typedef Int#(18) Stat;
    4.13 +
    4.14 +//----------------------------------------------------------------------
    4.15 +// Basic instruction type
    4.16 +//----------------------------------------------------------------------
    4.17 +
    4.18 +typedef Bit#(5)  Rindx;
    4.19 +typedef Bit#(16) Simm;
    4.20 +typedef Bit#(16) Zimm;
    4.21 +typedef Bit#(8)  Epoch;
    4.22 +typedef Bit#(5)  Shamt;
    4.23 +typedef Bit#(26) Target;
    4.24 +typedef Bit#(5)  CP0indx;
    4.25 +typedef Bit#(32) Data;
    4.26 +
    4.27 +typedef enum
    4.28 +{
    4.29 + Taken,
    4.30 + NotTaken
    4.31 +}
    4.32 +  Direction
    4.33 +    deriving(Bits,Eq);   
    4.34 +
    4.35 +
    4.36 +//----------------------------------------------------------------------
    4.37 +// Pipeline typedefs
    4.38 +//----------------------------------------------------------------------
    4.39 +
    4.40 +typedef union tagged
    4.41 +{
    4.42 +  Tuple2#(Rindx,Data) ALUWB;
    4.43 +  Rindx               MemWB;
    4.44 +  Tuple2#(Rindx,Data) CoWB;
    4.45 +}     
    4.46 +  WritebackType
    4.47 +    deriving(Bits,Eq);	 
    4.48 +
    4.49 +////////////////////////
    4.50 +// I Add Writeback queue type
    4.51 +////////////
    4.52 +typedef union tagged
    4.53 +{
    4.54 +  struct {Bit#(32) data; Rindx dest; } WB_ALU;
    4.55 +  Bit#(32) WB_Host;
    4.56 +  Rindx WB_Load;
    4.57 +  void WB_Store;
    4.58 +} 
    4.59 +WBResult deriving(Eq, Bits);
    4.60 +
    4.61 +typedef struct{Addr qpc; Addr qnxtpc; Epoch qepoch;} PCStat deriving(Eq, Bits);
    4.62 +//typedef struct{Addr qpc; Epoch qepoch;} PCStat deriving(Eq, Bits);
    4.63 +
    4.64 +typedef union tagged                
    4.65 +{
    4.66 +
    4.67 +  struct { Rindx rbase; Rindx rdst;  Simm offset;  } LW;
    4.68 +  struct { Rindx rbase; Rindx rsrc;  Simm offset;  } SW; 
    4.69 +
    4.70 +  struct { Rindx rsrc;  Rindx rdst;  Simm imm;     } ADDIU;
    4.71 +  struct { Rindx rsrc;  Rindx rdst;  Simm imm;     } SLTI;
    4.72 +  struct { Rindx rsrc;  Rindx rdst;  Simm imm;     } SLTIU;
    4.73 +  struct { Rindx rsrc;  Rindx rdst;  Zimm imm;     } ANDI;
    4.74 +  struct { Rindx rsrc;  Rindx rdst;  Zimm imm;     } ORI;
    4.75 +  struct { Rindx rsrc;  Rindx rdst;  Zimm imm;     } XORI;
    4.76 +  struct {              Rindx rdst;  Zimm imm;     } LUI;
    4.77 +
    4.78 +  struct { Rindx rsrc;  Rindx rdst;  Shamt shamt;  } SLL;
    4.79 +  struct { Rindx rsrc;  Rindx rdst;  Shamt shamt;  } SRL;
    4.80 +  struct { Rindx rsrc;  Rindx rdst;  Shamt shamt;  } SRA;
    4.81 +  struct { Rindx rsrc;  Rindx rdst;  Rindx rshamt; } SLLV;
    4.82 +  struct { Rindx rsrc;  Rindx rdst;  Rindx rshamt; } SRLV;
    4.83 +  struct { Rindx rsrc;  Rindx rdst;  Rindx rshamt; } SRAV;
    4.84 +  struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst;   } ADDU;
    4.85 +  struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst;   } SUBU;
    4.86 +  struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst;   } AND;
    4.87 +  struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst;   } OR;
    4.88 +  struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst;   } XOR;
    4.89 +  struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst;   } NOR;
    4.90 +  struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst;   } SLT;
    4.91 +  struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst;   } SLTU;
    4.92 +
    4.93 +  struct { Target target;                          } J;
    4.94 +  struct { Target target;                          } JAL;
    4.95 +  struct { Rindx rsrc;                             } JR;
    4.96 +  struct { Rindx rsrc;  Rindx rdst;                } JALR;
    4.97 +  struct { Rindx rsrc1; Rindx rsrc2; Simm offset;  } BEQ;
    4.98 +  struct { Rindx rsrc1; Rindx rsrc2; Simm offset;  } BNE;
    4.99 +  struct { Rindx rsrc;  Simm offset;               } BLEZ;
   4.100 +  struct { Rindx rsrc;  Simm offset;               } BGTZ;
   4.101 +  struct { Rindx rsrc;  Simm offset;               } BLTZ;
   4.102 +  struct { Rindx rsrc;  Simm offset;               } BGEZ;
   4.103 +
   4.104 +  struct { Rindx rdst;  CP0indx cop0src;           } MFC0;
   4.105 +  struct { Rindx rsrc;  CP0indx cop0dst;           } MTC0; 
   4.106 +
   4.107 +  void                                               ILLEGAL;
   4.108 +
   4.109 +}
   4.110 +Instr deriving(Eq);
   4.111 +
   4.112 +//----------------------------------------------------------------------
   4.113 +// Pack and Unpack
   4.114 +//----------------------------------------------------------------------
   4.115 +
   4.116 +Bit#(6) opFUNC  = 6'b000000;  Bit#(6) fcSLL   = 6'b000000;
   4.117 +Bit#(6) opRT    = 6'b000001;  Bit#(6) fcSRL   = 6'b000010;
   4.118 +Bit#(6) opRS    = 6'b010000;  Bit#(6) fcSRA   = 6'b000011;
   4.119 +                              Bit#(6) fcSLLV  = 6'b000100;
   4.120 +Bit#(6) opLW    = 6'b100011;  Bit#(6) fcSRLV  = 6'b000110;
   4.121 +Bit#(6) opSW    = 6'b101011;  Bit#(6) fcSRAV  = 6'b000111;
   4.122 +                              Bit#(6) fcADDU  = 6'b100001;
   4.123 +Bit#(6) opADDIU = 6'b001001;  Bit#(6) fcSUBU  = 6'b100011;
   4.124 +Bit#(6) opSLTI  = 6'b001010;  Bit#(6) fcAND   = 6'b100100;
   4.125 +Bit#(6) opSLTIU = 6'b001011;  Bit#(6) fcOR    = 6'b100101;
   4.126 +Bit#(6) opANDI  = 6'b001100;  Bit#(6) fcXOR   = 6'b100110;
   4.127 +Bit#(6) opORI   = 6'b001101;  Bit#(6) fcNOR   = 6'b100111;
   4.128 +Bit#(6) opXORI  = 6'b001110;  Bit#(6) fcSLT   = 6'b101010;
   4.129 +Bit#(6) opLUI   = 6'b001111;  Bit#(6) fcSLTU  = 6'b101011;
   4.130 +
   4.131 +Bit#(6) opJ     = 6'b000010;
   4.132 +Bit#(6) opJAL   = 6'b000011;
   4.133 +Bit#(6) fcJR    = 6'b001000;
   4.134 +Bit#(6) fcJALR  = 6'b001001;
   4.135 +Bit#(6) opBEQ   = 6'b000100;
   4.136 +Bit#(6) opBNE   = 6'b000101;
   4.137 +Bit#(6) opBLEZ  = 6'b000110;
   4.138 +Bit#(6) opBGTZ  = 6'b000111;
   4.139 +Bit#(5) rtBLTZ  = 5'b00000;
   4.140 +Bit#(5) rtBGEZ  = 5'b00001;
   4.141 +
   4.142 +Bit#(5) rsMFC0  = 5'b00000;
   4.143 +Bit#(5) rsMTC0  = 5'b00100;
   4.144 +
   4.145 +instance Bits#(Instr,32);
   4.146 +
   4.147 +  // Pack Function
   4.148 +
   4.149 +  function Bit#(32) pack( Instr instr );
   4.150 +
   4.151 +    case ( instr ) matches
   4.152 +
   4.153 +      tagged LW    .it : return { opLW,    it.rbase, it.rdst,  it.offset };
   4.154 +      tagged SW    .it : return { opSW,    it.rbase, it.rsrc,  it.offset };
   4.155 +
   4.156 +      tagged ADDIU .it : return { opADDIU, it.rsrc,  it.rdst,  it.imm                      }; 
   4.157 +      tagged SLTI  .it : return { opSLTI,  it.rsrc,  it.rdst,  it.imm                      }; 
   4.158 +      tagged SLTIU .it : return { opSLTIU, it.rsrc,  it.rdst,  it.imm                      }; 
   4.159 +      tagged ANDI  .it : return { opANDI,  it.rsrc,  it.rdst,  it.imm                      }; 
   4.160 +      tagged ORI   .it : return { opORI,   it.rsrc,  it.rdst,  it.imm                      }; 
   4.161 +      tagged XORI  .it : return { opXORI,  it.rsrc,  it.rdst,  it.imm                      }; 
   4.162 +      tagged LUI   .it : return { opLUI,   5'b0,     it.rdst,  it.imm                      };
   4.163 +
   4.164 +      tagged SLL   .it : return { opFUNC,  5'b0,     it.rsrc,  it.rdst,   it.shamt, fcSLL  }; 
   4.165 +      tagged SRL   .it : return { opFUNC,  5'b0,     it.rsrc,  it.rdst,   it.shamt, fcSRL  }; 
   4.166 +      tagged SRA   .it : return { opFUNC,  5'b0,     it.rsrc,  it.rdst,   it.shamt, fcSRA  }; 
   4.167 +
   4.168 +      tagged SLLV  .it : return { opFUNC,  it.rshamt, it.rsrc, it.rdst,   5'b0,     fcSLLV }; 
   4.169 +      tagged SRLV  .it : return { opFUNC,  it.rshamt, it.rsrc, it.rdst,   5'b0,     fcSRLV }; 
   4.170 +      tagged SRAV  .it : return { opFUNC,  it.rshamt, it.rsrc, it.rdst,   5'b0,     fcSRAV }; 
   4.171 +
   4.172 +      tagged ADDU  .it : return { opFUNC,  it.rsrc1, it.rsrc2, it.rdst,   5'b0,     fcADDU }; 
   4.173 +      tagged SUBU  .it : return { opFUNC,  it.rsrc1, it.rsrc2, it.rdst,   5'b0,     fcSUBU }; 
   4.174 +      tagged AND   .it : return { opFUNC,  it.rsrc1, it.rsrc2, it.rdst,   5'b0,     fcAND  }; 
   4.175 +      tagged OR    .it : return { opFUNC,  it.rsrc1, it.rsrc2, it.rdst,   5'b0,     fcOR   }; 
   4.176 +      tagged XOR   .it : return { opFUNC,  it.rsrc1, it.rsrc2, it.rdst,   5'b0,     fcXOR  }; 
   4.177 +      tagged NOR   .it : return { opFUNC,  it.rsrc1, it.rsrc2, it.rdst,   5'b0,     fcNOR  }; 
   4.178 +      tagged SLT   .it : return { opFUNC,  it.rsrc1, it.rsrc2, it.rdst,   5'b0,     fcSLT  }; 
   4.179 +      tagged SLTU  .it : return { opFUNC,  it.rsrc1, it.rsrc2, it.rdst,   5'b0,     fcSLTU }; 
   4.180 +
   4.181 +      tagged J     .it : return { opJ,     it.target                                       }; 
   4.182 +      tagged JAL   .it : return { opJAL,   it.target                                       }; 
   4.183 +      tagged JR    .it : return { opFUNC,  it.rsrc,  5'b0,     5'b0,      5'b0,     fcJR   };
   4.184 +      tagged JALR  .it : return { opFUNC,  it.rsrc,  5'b0,     it.rdst,   5'b0,     fcJALR };
   4.185 +      tagged BEQ   .it : return { opBEQ,   it.rsrc1, it.rsrc2, it.offset                   }; 
   4.186 +      tagged BNE   .it : return { opBNE,   it.rsrc1, it.rsrc2, it.offset                   }; 
   4.187 +      tagged BLEZ  .it : return { opBLEZ,  it.rsrc,  5'b0,     it.offset                   }; 
   4.188 +      tagged BGTZ  .it : return { opBGTZ,  it.rsrc,  5'b0,     it.offset                   }; 
   4.189 +      tagged BLTZ  .it : return { opRT,    it.rsrc,  rtBLTZ,   it.offset                   }; 
   4.190 +      tagged BGEZ  .it : return { opRT,    it.rsrc,  rtBGEZ,   it.offset                   }; 
   4.191 +
   4.192 +      tagged MFC0  .it : return { opRS,    rsMFC0,   it.rdst,  it.cop0src, 11'b0           }; 
   4.193 +      tagged MTC0  .it : return { opRS,    rsMTC0,   it.rsrc,  it.cop0dst, 11'b0           };  
   4.194 +
   4.195 +    endcase
   4.196 +
   4.197 +  endfunction
   4.198 +
   4.199 +  // Unpack Function
   4.200 +
   4.201 +  function Instr unpack( Bit#(32) instrBits );
   4.202 +
   4.203 +    let opcode = instrBits[ 31 : 26 ];
   4.204 +    let rs     = instrBits[ 25 : 21 ];
   4.205 +    let rt     = instrBits[ 20 : 16 ];
   4.206 +    let rd     = instrBits[ 15 : 11 ];
   4.207 +    let shamt  = instrBits[ 10 :  6 ];
   4.208 +    let funct  = instrBits[  5 :  0 ];
   4.209 +    let imm    = instrBits[ 15 :  0 ];
   4.210 +    let target = instrBits[ 25 :  0 ];
   4.211 +
   4.212 +    case ( opcode )
   4.213 +
   4.214 +      opLW        : return LW    { rbase:rs, rdst:rt,  offset:imm  };
   4.215 +      opSW        : return SW    { rbase:rs, rsrc:rt,  offset:imm  };
   4.216 +      opADDIU     : return ADDIU { rsrc:rs,  rdst:rt,  imm:imm     };
   4.217 +      opSLTI      : return SLTI  { rsrc:rs,  rdst:rt,  imm:imm     };
   4.218 +      opSLTIU     : return SLTIU { rsrc:rs,  rdst:rt,  imm:imm     };
   4.219 +      opANDI      : return ANDI  { rsrc:rs,  rdst:rt,  imm:imm     };
   4.220 +      opORI       : return ORI   { rsrc:rs,  rdst:rt,  imm:imm     };
   4.221 +      opXORI      : return XORI  { rsrc:rs,  rdst:rt,  imm:imm     };
   4.222 +      opLUI       : return LUI   {           rdst:rt,  imm:imm     };
   4.223 +      opJ         : return J     { target:target                   };
   4.224 +      opJAL       : return JAL   { target:target                   };
   4.225 +      opBEQ       : return BEQ   { rsrc1:rs, rsrc2:rt, offset:imm  };
   4.226 +      opBNE       : return BNE   { rsrc1:rs, rsrc2:rt, offset:imm  };
   4.227 +      opBLEZ      : return BLEZ  { rsrc:rs,  offset:imm            };
   4.228 +      opBGTZ      : return BGTZ  { rsrc:rs,  offset:imm            };
   4.229 +
   4.230 +      opFUNC  : 
   4.231 +        case ( funct )
   4.232 +          fcSLL   : return SLL   { rsrc:rt,  rdst:rd,  shamt:shamt };
   4.233 +          fcSRL   : return SRL   { rsrc:rt,  rdst:rd,  shamt:shamt };
   4.234 +          fcSRA   : return SRA   { rsrc:rt,  rdst:rd,  shamt:shamt };
   4.235 +          fcSLLV  : return SLLV  { rsrc:rt,  rdst:rd,  rshamt:rs   };
   4.236 +          fcSRLV  : return SRLV  { rsrc:rt,  rdst:rd,  rshamt:rs   };
   4.237 +          fcSRAV  : return SRAV  { rsrc:rt,  rdst:rd,  rshamt:rs   };
   4.238 +          fcADDU  : return ADDU  { rsrc1:rs, rsrc2:rt, rdst:rd     };
   4.239 +          fcSUBU  : return SUBU  { rsrc1:rs, rsrc2:rt, rdst:rd     };
   4.240 +          fcAND   : return AND   { rsrc1:rs, rsrc2:rt, rdst:rd     };
   4.241 +          fcOR    : return OR    { rsrc1:rs, rsrc2:rt, rdst:rd     };
   4.242 +          fcXOR   : return XOR   { rsrc1:rs, rsrc2:rt, rdst:rd     };
   4.243 +          fcNOR   : return NOR   { rsrc1:rs, rsrc2:rt, rdst:rd     };
   4.244 +          fcSLT   : return SLT   { rsrc1:rs, rsrc2:rt, rdst:rd     }; 
   4.245 +          fcSLTU  : return SLTU  { rsrc1:rs, rsrc2:rt, rdst:rd     };
   4.246 +          fcJR    : return JR    { rsrc:rs                         };
   4.247 +          fcJALR  : return JALR  { rsrc:rs,  rdst:rd               };
   4.248 +          default : return ILLEGAL;
   4.249 +        endcase
   4.250 +
   4.251 +      opRT : 
   4.252 +        case ( rt )
   4.253 +          rtBLTZ  : return BLTZ  { rsrc:rs,  offset:imm            };
   4.254 +          rtBGEZ  : return BGEZ  { rsrc:rs,  offset:imm            };
   4.255 +          default : return ILLEGAL;
   4.256 +        endcase
   4.257 +
   4.258 +      opRS : 
   4.259 +        case ( rs )
   4.260 +          rsMFC0  : return MFC0  { rdst:rt,  cop0src:rd            };
   4.261 +          rsMTC0  : return MTC0  { rsrc:rt,  cop0dst:rd            };
   4.262 +          default : return ILLEGAL;
   4.263 +        endcase
   4.264 +
   4.265 +      default : return ILLEGAL;
   4.266 +      
   4.267 +    endcase
   4.268 +
   4.269 +  endfunction
   4.270 +
   4.271 +endinstance
   4.272 +
   4.273 +//----------------------------------------------------------------------
   4.274 +// Trace
   4.275 +//----------------------------------------------------------------------
   4.276 +
   4.277 +instance Traceable#(Instr);
   4.278 +
   4.279 +  function Action traceTiny( String loc, String ttag, Instr inst );
   4.280 +    case ( inst ) matches
   4.281 +
   4.282 +      tagged LW    .it : $fdisplay(stderr,  " => %s:%s lw", loc,   ttag );
   4.283 +      tagged SW    .it : $fdisplay(stderr,  " => %s:%s sw", loc,   ttag );
   4.284 +
   4.285 +      tagged ADDIU .it : $fdisplay(stderr,  " => %s:%s addi", loc, ttag );
   4.286 +      tagged SLTI  .it : $fdisplay(stderr,  " => %s:%s sli", loc,  ttag );
   4.287 +      tagged SLTIU .it : $fdisplay(stderr,  " => %s:%s sliu", loc, ttag );
   4.288 +      tagged ANDI  .it : $fdisplay(stderr,  " => %s:%s andi", loc, ttag );
   4.289 +      tagged ORI   .it : $fdisplay(stderr,  " => %s:%s ori", loc,  ttag );
   4.290 +      tagged XORI  .it : $fdisplay(stderr,  " => %s:%s xori", loc, ttag );
   4.291 +      tagged LUI   .it : $fdisplay(stderr,  " => %s:%s lui", loc,  ttag );
   4.292 +                                          
   4.293 +      tagged SLL   .it : $fdisplay(stderr,  " => %s:%s sll", loc,  ttag );
   4.294 +      tagged SRL   .it : $fdisplay(stderr,  " => %s:%s srl", loc,  ttag );
   4.295 +      tagged SRA   .it : $fdisplay(stderr,  " => %s:%s sra", loc,  ttag );
   4.296 +      tagged SLLV  .it : $fdisplay(stderr,  " => %s:%s sllv", loc, ttag );
   4.297 +      tagged SRLV  .it : $fdisplay(stderr,  " => %s:%s srlv", loc, ttag );
   4.298 +      tagged SRAV  .it : $fdisplay(stderr,  " => %s:%s srav", loc, ttag );
   4.299 +                                          
   4.300 +      tagged ADDU  .it : $fdisplay(stderr,  " => %s:%s addu", loc, ttag );
   4.301 +      tagged SUBU  .it : $fdisplay(stderr,  " => %s:%s subu", loc, ttag );
   4.302 +      tagged AND   .it : $fdisplay(stderr,  " => %s:%s and", loc,  ttag );
   4.303 +      tagged OR    .it : $fdisplay(stderr,  " => %s:%s or", loc,   ttag );
   4.304 +      tagged XOR   .it : $fdisplay(stderr,  " => %s:%s xor", loc,  ttag );
   4.305 +      tagged NOR   .it : $fdisplay(stderr,  " => %s:%s nor", loc,  ttag );
   4.306 +      tagged SLT   .it : $fdisplay(stderr,  " => %s:%s slt", loc,  ttag );
   4.307 +      tagged SLTU  .it : $fdisplay(stderr,  " => %s:%s sltu", loc, ttag );
   4.308 +                                          
   4.309 +      tagged J     .it : $fdisplay(stderr,  " => %s:%s j", loc,    ttag );
   4.310 +      tagged JAL   .it : $fdisplay(stderr,  " => %s:%s jal", loc,  ttag );
   4.311 +      tagged JR    .it : $fdisplay(stderr,  " => %s:%s jr", loc,   ttag );
   4.312 +      tagged JALR  .it : $fdisplay(stderr,  " => %s:%s jalr", loc, ttag );
   4.313 +      tagged BEQ   .it : $fdisplay(stderr,  " => %s:%s beq", loc,  ttag );
   4.314 +      tagged BNE   .it : $fdisplay(stderr,  " => %s:%s bne", loc,  ttag );
   4.315 +      tagged BLEZ  .it : $fdisplay(stderr,  " => %s:%s blez", loc, ttag );
   4.316 +      tagged BGTZ  .it : $fdisplay(stderr,  " => %s:%s bgtz", loc, ttag );
   4.317 +      tagged BLTZ  .it : $fdisplay(stderr,  " => %s:%s bltz", loc, ttag );
   4.318 +      tagged BGEZ  .it : $fdisplay(stderr,  " => %s:%s bgez", loc, ttag );
   4.319 +                                           
   4.320 +      tagged MFC0  .it : $fdisplay(stderr,  " => %s:%s mfc0", loc, ttag );
   4.321 +      tagged MTC0  .it : $fdisplay(stderr,  " => %s:%s mtc0", loc, ttag );
   4.322 +
   4.323 +      tagged ILLEGAL   : $fdisplay(stderr,  " => %s:%s ill", loc,  ttag );
   4.324 +
   4.325 +    endcase
   4.326 +  endfunction
   4.327 +
   4.328 +  function Action traceFull( String loc, String ttag, Instr inst );
   4.329 +    case ( inst ) matches
   4.330 +
   4.331 +      tagged LW    .it : $fdisplay(stderr,  " => %s:%s lw r%0d, 0x%x(r%0d)", loc, ttag, it.rdst, it.offset, it.rbase );
   4.332 +      tagged SW    .it : $fdisplay(stderr,  " => %s:%s sw r%0d, 0x%x(r%0d)", loc, ttag, it.rsrc, it.offset, it.rbase );
   4.333 +
   4.334 +      tagged ADDIU .it : $fdisplay(stderr,  " => %s:%s addiu r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm );
   4.335 +      tagged SLTI  .it : $fdisplay(stderr,  " => %s:%s slti r%0d, r%0d, 0x%x", loc,  ttag, it.rdst, it.rsrc, it.imm );
   4.336 +      tagged SLTIU .it : $fdisplay(stderr,  " => %s:%s sltiu r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm );
   4.337 +      tagged ANDI  .it : $fdisplay(stderr,  " => %s:%s andi r%0d, r%0d, 0x%x", loc,  ttag, it.rdst, it.rsrc, it.imm );
   4.338 +      tagged ORI   .it : $fdisplay(stderr,  " => %s:%s ori r%0d, r%0d, 0x%x", loc,   ttag, it.rdst, it.rsrc, it.imm );
   4.339 +      tagged XORI  .it : $fdisplay(stderr,  " => %s:%s xori r%0d, r%0d, 0x%x", loc,  ttag, it.rdst, it.rsrc, it.imm );
   4.340 +      tagged LUI   .it : $fdisplay(stderr,  " => %s:%s lui r%0d, 0x%x", loc,         ttag, it.rdst, it.imm );
   4.341 +                                      
   4.342 +      tagged SLL   .it : $fdisplay(stderr,  " => %s:%s sll r%0d, r%0d, %0d", loc,   ttag, it.rdst, it.rsrc, it.shamt );
   4.343 +      tagged SRL   .it : $fdisplay(stderr,  " => %s:%s srl r%0d, r%0d, %0d", loc,   ttag, it.rdst, it.rsrc, it.shamt );
   4.344 +      tagged SRA   .it : $fdisplay(stderr,  " => %s:%s sra r%0d, r%0d, %0d", loc,   ttag, it.rdst, it.rsrc, it.shamt );
   4.345 +      tagged SLLV  .it : $fdisplay(stderr,  " => %s:%s sllv r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc, it.rshamt );
   4.346 +      tagged SRLV  .it : $fdisplay(stderr,  " => %s:%s srlv r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc, it.rshamt );
   4.347 +      tagged SRAV  .it : $fdisplay(stderr,  " => %s:%s srav r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc, it.rshamt );
   4.348 +                                      
   4.349 +      tagged ADDU  .it : $fdisplay(stderr,  " => %s:%s addu r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 );
   4.350 +      tagged SUBU  .it : $fdisplay(stderr,  " => %s:%s subu r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 );
   4.351 +      tagged AND   .it : $fdisplay(stderr,  " => %s:%s and r%0d, r%0d, r%0d", loc,  ttag, it.rdst, it.rsrc1, it.rsrc2 );
   4.352 +      tagged OR    .it : $fdisplay(stderr,  " => %s:%s or r%0d, r%0d, r%0d", loc,   ttag, it.rdst, it.rsrc1, it.rsrc2 );
   4.353 +      tagged XOR   .it : $fdisplay(stderr,  " => %s:%s xor r%0d, r%0d, r%0d", loc,  ttag, it.rdst, it.rsrc1, it.rsrc2 );
   4.354 +      tagged NOR   .it : $fdisplay(stderr,  " => %s:%s nor r%0d, r%0d, r%0d", loc,  ttag, it.rdst, it.rsrc1, it.rsrc2 );
   4.355 +      tagged SLT   .it : $fdisplay(stderr,  " => %s:%s slt r%0d, r%0d, r%0d", loc,  ttag, it.rdst, it.rsrc1, it.rsrc2 );
   4.356 +      tagged SLTU  .it : $fdisplay(stderr,  " => %s:%s sltu r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 );
   4.357 +                                      
   4.358 +      tagged J     .it : $fdisplay(stderr,  " => %s:%s j 0x%x", loc,    ttag, it.target );
   4.359 +      tagged JAL   .it : $fdisplay(stderr,  " => %s:%s jal 0x%x", loc,  ttag, it.target );
   4.360 +      tagged JR    .it : $fdisplay(stderr,  " => %s:%s jr r%0d", loc,   ttag, it.rsrc );
   4.361 +      tagged JALR  .it : $fdisplay(stderr,  " => %s:%s jalr r%0d", loc, ttag, it.rsrc );
   4.362 +      tagged BEQ   .it : $fdisplay(stderr,  " => %s:%s beq r%0d, r%0d, 0x%x", loc, ttag, it.rsrc1, it.rsrc2, it.offset );
   4.363 +      tagged BNE   .it : $fdisplay(stderr,  " => %s:%s bne r%0d, r%0d, 0x%x", loc, ttag, it.rsrc1, it.rsrc2, it.offset );
   4.364 +      tagged BLEZ  .it : $fdisplay(stderr,  " => %s:%s blez r%0d, 0x%x", loc, ttag, it.rsrc, it.offset );
   4.365 +      tagged BGTZ  .it : $fdisplay(stderr,  " => %s:%s bgtz r%0d, 0x%x", loc, ttag, it.rsrc, it.offset );
   4.366 +      tagged BLTZ  .it : $fdisplay(stderr,  " => %s:%s bltz r%0d, 0x%x", loc, ttag, it.rsrc, it.offset );
   4.367 +      tagged BGEZ  .it : $fdisplay(stderr,  " => %s:%s bgez r%0d, 0x%x", loc, ttag, it.rsrc, it.offset );
   4.368 +                                      
   4.369 +      tagged MFC0  .it : $fdisplay(stderr,  " => %s:%s mfc0 r%0d, cpr%0d", loc, ttag, it.rdst, it.cop0src );
   4.370 +      tagged MTC0  .it : $fdisplay(stderr,  " => %s:%s mtc0 r%0d, cpr%0d", loc, ttag, it.rsrc, it.cop0dst );
   4.371 +
   4.372 +      tagged ILLEGAL   : $fdisplay(stderr,  " => %s:%s illegal instruction", loc, ttag );
   4.373 +
   4.374 +    endcase
   4.375 +  endfunction
   4.376 +
   4.377 +endinstance
   4.378 +

     5.1 --- a/modules/bluespec/Pygar/core/ProcTypes.bsv	Wed Apr 28 12:01:37 2010 -0400
     5.2 +++ b/modules/bluespec/Pygar/core/ProcTypes.bsv	Fri Apr 30 09:03:10 2010 -0400
     5.3 @@ -1,5 +1,5 @@
     5.4 +import Trace::*;
     5.5  
     5.6 -import Trace::*;
     5.7  
     5.8  //----------------------------------------------------------------------
     5.9  // Other typedefs

     6.1 --- a/modules/bluespec/Pygar/core/Processor.bsv	Wed Apr 28 12:01:37 2010 -0400
     6.2 +++ b/modules/bluespec/Pygar/core/Processor.bsv	Fri Apr 30 09:03:10 2010 -0400
     6.3 @@ -49,6 +49,7 @@
     6.4  `include "asim/rrr/remote_server_stub_AUDIOCORERRR.bsh"
     6.5  `include "asim/provides/common_services.bsh"
     6.6  `include "asim/dict/STATS_PROCESSOR.bsh"
     6.7 +`include "asim/provides/processor_library.bsh"
     6.8  
     6.9  // Local includes. Look for the correspondingly named .awb files
    6.10  // workspace/labs/src/mit-6.375/modules/bluespec/mit-6.375/common/

     7.1 --- a/modules/bluespec/Pygar/core/audioCore.bsv	Wed Apr 28 12:01:37 2010 -0400
     7.2 +++ b/modules/bluespec/Pygar/core/audioCore.bsv	Fri Apr 30 09:03:10 2010 -0400
     7.3 @@ -62,8 +62,8 @@
     7.4  
     7.5    mkConnection( proc.statsEn_get,   icache.statsEn_put );
     7.6    mkConnection( proc.statsEn_get,   dcache.statsEn_put );
     7.7 -//  mkConnection( proc.imem_client,   icache.proc_server );
     7.8 -//  mkConnection( proc.dmem_client,   dcache.proc_server );
     7.9 +  mkConnection( proc.imem_client,   icache.proc_server );
    7.10 +  mkConnection( proc.dmem_client,   dcache.proc_server );
    7.11    mkConnection( icache.mmem_client, marb.cache0_server );
    7.12    mkConnection( dcache.mmem_client, marb.cache1_server );
    7.13  
    7.14 @@ -72,8 +72,5 @@
    7.15     interface mmem_client = marb.mmem_client;
    7.16        
    7.17     interface sampleOutput = proc.sampleOutput;
    7.18 -  // interface sampleOutput = proc.audioOut;
    7.19 -  // interface AudioOut audio = proc.audioOut;
    7.20 -      
    7.21  
    7.22  endmodule

     8.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     8.2 +++ b/modules/bluespec/Pygar/core/proc_trace.awb	Fri Apr 30 09:03:10 2010 -0400
     8.3 @@ -0,0 +1,13 @@
     8.4 +%name 3-Stage Audio Processor  
     8.5 +%desc 3-Stage Processor, with audio in one stage per cycle.
     8.6 +
     8.7 +%provides processor
     8.8 +
     8.9 +%attributes 6_375
    8.10 +
    8.11 +%public Processor.bsv ProcTypes.bsv
    8.12 +%public Processor.dic
    8.13 +
    8.14 +
    8.15 +
    8.16 +

     9.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     9.2 +++ b/modules/bluespec/Pygar/core/proc_types.awb	Fri Apr 30 09:03:10 2010 -0400
     9.3 @@ -0,0 +1,10 @@
     9.4 +%name Round-robin Audio memory arbiter 
     9.5 +%desc Round-robin memory arbiter 
     9.6 +
     9.7 +%provides mem_arb
     9.8 +
     9.9 +%attributes 6_375
    9.10 +
    9.11 +%public MemArb.bsv
    9.12 +
    9.13 +

    10.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    10.2 +++ b/modules/bluespec/Pygar/core/proc_types.awb~	Fri Apr 30 09:03:10 2010 -0400
    10.3 @@ -0,0 +1,10 @@
    10.4 +%name Round-robin Audio memory arbiter 
    10.5 +%desc Round-robin memory arbiter 
    10.6 +
    10.7 +%provides mem_arb
    10.8 +
    10.9 +%attributes 6_375
   10.10 +
   10.11 +%public MemArb.bsv
   10.12 +
   10.13 +

    11.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    11.2 +++ b/modules/bluespec/Pygar/core/trace.awb	Fri Apr 30 09:03:10 2010 -0400
    11.3 @@ -0,0 +1,10 @@
    11.4 +%name Trace Functions
    11.5 +%desc Contains trace 
    11.6 +
    11.7 +%provides trace
    11.8 +
    11.9 +%attributes PYGAR
   11.10 +
   11.11 +%public Trace.bsv
   11.12 +
   11.13 +

    12.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    12.2 +++ b/modules/bluespec/Pygar/core/trace.awb~	Fri Apr 30 09:03:10 2010 -0400
    12.3 @@ -0,0 +1,10 @@
    12.4 +%name Audio Core Processor Types
    12.5 +%desc Contains types used in Processor including expanded trace 
    12.6 +
    12.7 +%provides proc_types
    12.8 +
    12.9 +%attributes PYGAR
   12.10 +
   12.11 +%public ProcTypes.bsv
   12.12 +
   12.13 +