# HG changeset patch
# User punk
# Date 1272632590 14400
# Node ID f5dfbe28fa5949d27fb23d9ee92ed121b939b446
# Parent  220c14f5963c7b8c9715a9d27031f92a3f61bc6a
[svn r27] Fixed Instruction trace issue.

diff -r 220c14f5963c -r f5dfbe28fa59 modules/bluespec/Pygar/core/#AudioCoreRRR.cpp#
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/modules/bluespec/Pygar/core/#AudioCoreRRR.cpp#	Fri Apr 30 09:03:10 2010 -0400
@@ -0,0 +1,116 @@
+#include <cstdio>
+#include <cstdlib>
+#include <iostream>
+#include <iomanip>
+#include <stdio.h>
+#include <sys/stat.h>
+
+#include "asim/rrr/service_ids.h"
+
+#include "asim/provides/connected_application.h"
+
+using namespace std;
+
+// ===== service instantiation =====
+AUDIOCORERRR_SERVER_CLASS AUDIOCORERRR_SERVER_CLASS::instance;
+
+// constructor
+AUDIOCORERRR_SERVER_CLASS::AUDIOCORERRR_SERVER_CLASS() :
+  serverStub(new AUDIOCORERRR_SERVER_STUB_CLASS(this))
+{
+    // instantiate stub
+    printf("AUDIOCORERRR init called\n");
+    outputFile = NULL;
+    memory = NULL;
+    fflush(stdout);
+}
+
+// destructor
+AUDIOCORERRR_SERVER_CLASS::~AUDIOCORERRR_SERVER_CLASS()
+{
+    Cleanup();
+}
+
+// init
+void
+AUDIOCORERRR_SERVER_CLASS::Init(PLATFORMS_MODULE p)
+{
+    parent = p;
+}
+
+// uninit
+void
+AUDIOCORERRR_SERVER_CLASS::Uninit()
+{
+    Cleanup();
+}
+
+// cleanup
+void
+AUDIOCORERRR_SERVER_CLASS::Cleanup()
+{
+    delete serverStub;
+}
+
+
+//
+// RRR service methods
+//
+
+UINT32
+AUDIOCORERRR_SERVER_CLASS::MemoryRequestLoad (UINT32 address)
+{
+  UINT32 returnVal;
+  
+  if(memory == NULL) {
+    memory = new FUNCP_SIMULATED_MEMORY_CLASS();
+  }
+
+ 
+  memory->Read(0,(UINT64) address, sizeof(UINT32), &returnVal); 
+  return returnVal;
+}
+
+void
+AUDIOCORERRR_SERVER_CLASS::MemoryRequestStore (UINT32 address, UINT32 data)
+{
+  if(memory == NULL) {
+    memory = new FUNCP_SIMULATED_MEMORY_CLASS();
+  }
+
+  memory->Write(0,(UINT64) address, sizeof(UINT32), &data); 
+}
+
+void
+AUDIOCORERRR_SERVER_CLASS::SendProcessedStream(UINT16 control, UINT16 data)
+{
+
+  AudioProcessorControl audioProcessorControl = (AudioProcessorControl) control;
+  switch(control) {
+    case EndOfFile:
+      if(outputFile != NULL) {
+        fflush(outputFile);
+        fclose(outputFile);
+        outputFile = NULL;
+      } else {
+        outputFile = fopen("out_hw.pcm","w");
+        assert(outputFile);
+        fflush(outputFile);
+        fclose(outputFile);
+      }
+
+      // Long term this should be in the data portion.  But until I have code running, keep it here.
+      CONNECTED_APPLICATION_CLASS::EndSimulation(); 
+    break;
+
+    case Data:
+      if(outputFile == NULL) {
+        outputFile = fopen("out_hw.pcm","w");
+        assert(outputFile);
+      }
+
+      CONNECTED_APPLICATION_CLASS::UpdateSemaphore();  
+      fwrite(&data, 2,1 , outputFile);
+    break;
+  }
+}
diff -r 220c14f5963c -r f5dfbe28fa59 modules/bluespec/Pygar/core/#Processor.bsv#
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/modules/bluespec/Pygar/core/#Processor.bsv#	Fri Apr 30 09:03:10 2010 -0400
@@ -0,0 +1,625 @@
+/// The MIT License
+
+// Copyright (c) 2009 Massachusetts Institute of Technology
+
+// Permission is hereby granted, free of charge, to any person obtaining a copy
+// of this software and associated documentation files (the "Software"), to deal
+// in the Software without restriction, including without limitation the rights
+// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+// copies of the Software, and to permit persons to whom the Software is
+// furnished to do so, subject to the following conditions:
+
+// The above copyright notice and this permission notice shall be included in
+// all copies or substantial portions of the Software.
+
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+// THE SOFTWARE.
+
+
+import Connectable::*;
+import GetPut::*;
+import ClientServer::*;
+import RegFile::*;
+
+import FIFO::*;
+import FIFOF::*;
+import SFIFO::*;
+import RWire::*;
+import Trace::*;
+import BFIFO::*;
+import ProcTypes::*;
+import BRegFile::*;
+import BranchPred::*;
+//import PathTypes::*;  This is only there to force the debugging
+
+//AWB includes
+`include "asim/provides/low_level_platform_interface.bsh"
+`include "asim/provides/soft_connections.bsh"
+`include "asim/provides/common_services.bsh"
+
+// Local includes
+//`include "asim/provides/processor_library.bsh" (included above directly)
+`include "asim/rrr/remote_server_stub_AUDIOCORERRR.bsh"
+`include "asim/provides/common_services.bsh"
+`include "asim/dict/STATS_PROCESSOR.bsh"
+`include "asim/provides/processor_library.bsh"
+
+// Local includes. Look for the correspondingly named .awb files
+// workspace/labs/src/mit-6.375/modules/bluespec/mit-6.375/common/
+// to find the actual Bluespec files which are used to generate
+// these includes.  These files are specific to this audio processing
+// pipeline
+
+`include "asim/provides/audio_pipe_types.bsh"
+
+//interface CPUToHost;
+//  method Bit#(32) cpuToHost(int req);
+//endinterface
+
+interface Proc;
+
+  // Interface from processor to caches
+  interface Client#(DataReq,DataResp) dmem_client;
+  interface Client#(InstReq,InstResp) imem_client;
+
+  // Interface for enabling/disabling statistics on the rest of the core
+  interface Get#(Bool) statsEn_get;
+
+//  // Interface to host
+//  interface CPUToHost tohost;
+
+  // Interface to Audio Pipeline
+  interface Get#(AudioProcessorUnit) sampleOutput;
+	
+endinterface
+
+//The full interface for this is as below in the common file for audioProcessorTypes.bsv
+//interface AudioOut;
+//  interface Get#(AudioProcessorUnit) audioSampleOutput;
+//endinterface
+
+//interface AudioIn;
+//  interface Put#(AudioProcessorUnit) audioSampleInput;
+//endinterface	
+
+typedef enum { PCgen, Exec, Writeback } Stage deriving(Eq,Bits);
+
+//-----------------------------------------------------------
+// Register file module
+//-----------------------------------------------------------
+
+interface BRFile;
+   method Action   wr( Rindx rindx, Bit#(32) data );
+   method Bit#(32) rd1( Rindx rindx );
+   method Bit#(32) rd2( Rindx rindx );
+endinterface
+
+module mkBRFile( BRFile );
+   
+   RegFile#(Rindx,Bit#(32)) rfile <- mkBRegFile();
+   
+   method Action wr( Rindx rindx, Bit#(32) data );
+      rfile.upd( rindx, data );
+   endmethod
+   
+   method Bit#(32) rd1( Rindx rindx );
+      return ( rindx == 0 ) ? 0 : rfile.sub(rindx);
+   endmethod
+   
+   method Bit#(32) rd2( Rindx rindx );
+      return ( rindx == 0 ) ? 0 : rfile.sub(rindx);
+   endmethod
+
+endmodule
+
+//-----------------------------------------------------------
+// Helper functions
+//-----------------------------------------------------------
+
+function Bit#(32) slt( Bit#(32) val1, Bit#(32) val2 );
+   return zeroExtend( pack( signedLT(val1,val2) ) );
+endfunction
+
+function Bit#(32) sltu( Bit#(32) val1, Bit#(32) val2 );
+   return zeroExtend( pack( val1 < val2 ) );
+endfunction
+
+function Bit#(32) rshft( Bit#(32) val );
+   return zeroExtend(val[4:0]);
+endfunction
+
+
+//-----------------------------------------------------------
+// Find funct for wbQ
+//-----------------------------------------------------------
+function Bool findwbf(Rindx fVal, WBResult cmpVal);
+  case (cmpVal) matches   
+     tagged WB_ALU  {data:.res, dest:.rd} :
+	return (fVal == rd);
+     tagged WB_Load .rd  :
+	return (fVal == rd);
+     tagged WB_Store .st :
+	return False;
+     tagged WB_Host .x   :
+	return False;
+  endcase
+endfunction
+
+     
+//-----------------------------------------------------------
+// Stall funct for wbQ
+//-----------------------------------------------------------
+function Bool stall(Instr inst, SFIFO#(WBResult, Rindx) f);
+   case (inst) matches
+      	 // -- Memory Ops ------------------------------------------------      
+      tagged LW .it :
+	 return f.find(it.rbase);
+      tagged SW {rsrc:.dreg, rbase:.addr, offset:.o} :
+	 return (f.find(addr) ||  f.find2(dreg));
+
+	 // -- Simple Ops ------------------------------------------------      
+      tagged ADDIU .it : return f.find(it.rsrc);
+      tagged SLTI  .it : return f.find(it.rsrc);
+      tagged SLTIU .it : return f.find(it.rsrc);
+      tagged ANDI  .it : return f.find(it.rsrc);
+      tagged ORI   .it : return f.find(it.rsrc);
+      tagged XORI  .it : return f.find(it.rsrc);
+      
+      tagged LUI   .it : return f.find(it.rdst);  //this rds/wrs itself
+      tagged SLL   .it : return f.find(it.rsrc);
+      tagged SRL   .it : return f.find(it.rsrc);
+      tagged SRA   .it : return f.find(it.rsrc);
+      tagged SLLV  .it : return (f.find(it.rsrc) || f.find(it.rshamt));
+      tagged SRLV  .it : return (f.find(it.rsrc) || f.find(it.rshamt));
+      tagged SRAV  .it : return (f.find(it.rsrc) || f.find(it.rshamt));
+      tagged ADDU  .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
+      tagged SUBU  .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
+      tagged AND   .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
+      tagged OR    .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
+      tagged XOR   .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
+      tagged NOR   .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
+      tagged SLT   .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
+      tagged SLTU  .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
+   
+
+      // -- Branches --------------------------------------------------
+    
+      tagged BLEZ  .it : return (f.find(it.rsrc));
+      tagged BGTZ  .it : return (f.find(it.rsrc));
+      tagged BLTZ  .it : return (f.find(it.rsrc));
+      tagged BGEZ  .it : return (f.find(it.rsrc));
+      tagged BEQ   .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
+      tagged BNE   .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
+      
+      // -- Jumps -----------------------------------------------------
+      
+      tagged J     .it : return False;
+      tagged JR    .it : return f.find(it.rsrc);
+      tagged JALR  .it : return f.find(it.rsrc);
+      tagged JAL   .it : return False;
+      
+      // -- Cop0 ------------------------------------------------------
+      
+      tagged MTC0  .it : return f.find(it.rsrc);      
+      tagged MFC0  .it : return False; 
+
+      // -- Illegal ---------------------------------------------------
+
+      default : return False;
+
+    endcase
+endfunction
+//-----------------------------------------------------------
+// Reference processor
+//-----------------------------------------------------------
+
+
+//(* doc = "synthesis attribute ram_style mkProc distributed;" *)
+//(* synthesize *)
+
+module  [CONNECTED_MODULE] mkProc( Proc );
+
+   //-----------------------------------------------------------
+   // Debug port
+   
+   ServerStub_AUDIOCORERRR server_stub <- mkServerStub_AUDIOCORERRR();   
+
+   
+   //-----------------------------------------------------------
+   // State
+
+   // Standard processor state
+   
+   Reg#(Addr)  pc    <- mkReg(32'h00001000);
+   Reg#(Epoch) epoch <- mkReg(0);
+   Reg#(Stage) stage <- mkReg(PCgen);
+   BRFile      rf    <- mkBRFile;
+
+   // Branch Prediction
+   BranchPred               bp <- mkBranchPred();
+   FIFO#(PCStat)        execpc <- mkLFIFO();
+   
+   // Pipelines
+   FIFO#(PCStat)           pcQ <-mkSizedFIFO(3);
+   SFIFO#(WBResult, Rindx) wbQ <-mkSFIFO(findwbf);
+
+   Reg#(Bit#(32)) cp0_tohost   <- mkReg(0);
+   Reg#(Bit#(32)) cp0_fromhost <- mkReg(0);
+   Reg#(Bool)     cp0_statsEn  <- mkReg(False);
+
+   // Memory request/response state
+   
+   FIFO#(InstReq)  instReqQ    <- mkBFIFO1();
+   FIFO#(InstResp) instRespQ   <- mkFIFO();
+
+   FIFO#(DataReq)  dataReqQ    <- mkBFIFO1();
+   FIFO#(DataResp) dataRespQ   <- mkFIFO();
+
+   // Audio I/O
+   FIFO#(AudioProcessorUnit) inAudioFifo <- mkFIFO;
+   FIFO#(AudioProcessorUnit) outAudioFifo <- mkFIFO;
+
+
+   // Statistics state (2010)
+//   Reg#(Stat) num_cycles <- mkReg(0);
+//   Reg#(Stat) num_inst <- mkReg(0);
+
+   //Or:
+   // Statistics state
+   STAT num_cycles <- mkStatCounter(`STATS_PROCESSOR_CYCLE_COUNT);
+   STAT num_inst <- mkStatCounter(`STATS_PROCESSOR_INST_COUNT);
+
+   //-----------------------------------------------------------
+   // Rules
+
+   (* descending_urgency = "exec, pcgen" *)
+   rule pcgen; //( stage == PCgen );
+      let pc_plus4 = pc + 4;
+
+      traceTiny("mkProc", "pc",pc);
+      traceTiny("mkProc", "pcgen","P");
+      instReqQ.enq( LoadReq{ addr:pc, tag:epoch} );
+      
+      let next_pc = bp.get(pc);
+      if (next_pc matches tagged Valid .npc) 
+	begin
+	   pcQ.enq(PCStat {qpc:pc, qnxtpc:npc, qepoch:epoch});
+	   pc <= npc;
+	end
+     else
+	 begin
+	   pcQ.enq(PCStat {qpc:pc, qnxtpc:pc_plus4, qepoch:epoch});
+	   pc <= pc_plus4;
+	 end
+      
+   endrule
+
+   rule discard (instRespQ.first() matches tagged LoadResp .ld
+					      &&& ld.tag != epoch);
+      traceTiny("mkProc", "stage", "D");
+      instRespQ.deq();
+   endrule
+
+   (* conflict_free = "exec, writeback" *)		      
+   rule exec (instRespQ.first() matches tagged LoadResp.ld
+	      &&& (ld.tag == epoch)
+	      &&& unpack(ld.data) matches .inst
+              &&& !stall(inst, wbQ));
+
+      // Some abbreviations
+      let sext = signExtend;
+      let zext = zeroExtend;
+      let sra  = signedShiftRight;
+      
+      // Get the instruction
+      
+      instRespQ.deq();
+      Instr inst 
+      = case ( instRespQ.first() ) matches
+	   tagged LoadResp  .ld : return unpack(ld.data);
+	   tagged StoreResp .st : return ?;
+	endcase;
+
+      // Get the PC info
+      let instrpc = pcQ.first().qpc;
+      let pc_plus4 = instrpc + 4;
+      
+      Bool branchTaken = False;
+      Addr newPC = pc_plus4;
+
+      // Tracing
+      traceTiny("mkProc", "exec","X");
+      traceTiny("mkProc", "exInstTiny",inst);
+      traceFull("mkProc", "exInstFull",inst);
+
+      case ( inst ) matches
+
+	 // -- Memory Ops ------------------------------------------------      
+
+	 tagged LW .it : 
+	    begin
+               Addr addr = rf.rd1(it.rbase) + sext(it.offset);
+               dataReqQ.enq( LoadReq{ addr:addr, tag:zeroExtend(it.rdst) } );
+               wbQ.enq(tagged WB_Load it.rdst);
+	    end
+
+	 tagged SW .it : 
+	    begin
+               Addr addr = rf.rd1(it.rbase) + sext(it.offset);
+               dataReqQ.enq( StoreReq{ tag:0, addr:addr, data:rf.rd2(it.rsrc) } );
+               wbQ.enq(tagged WB_Store);
+	    end
+
+	 // -- Simple Ops ------------------------------------------------      
+
+	 tagged ADDIU .it : 
+	    begin
+	       Bit#(32) result = rf.rd1(it.rsrc) + sext(it.imm);
+	       wbQ.enq(tagged WB_ALU {data:result, dest:it.rdst});
+	    end
+	 tagged SLTI  .it : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:slt( rf.rd1(it.rsrc), sext(it.imm) )});
+	 tagged SLTIU .it : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:sltu( rf.rd1(it.rsrc), sext(it.imm) ) });
+	 tagged ANDI  .it : 
+	    begin
+	       Bit#(32) zext_it_imm = zext(it.imm);
+	       wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(rf.rd1(it.rsrc) & zext_it_imm)} );
+	    end
+	 tagged ORI   .it : 
+	    begin
+	       Bit#(32) zext_it_imm = zext(it.imm);
+	       wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(rf.rd1(it.rsrc) | zext_it_imm)} );
+	    end
+	 tagged XORI  .it : 
+	    begin
+	       Bit#(32) zext_it_imm = zext(it.imm);
+	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) ^ zext_it_imm )});
+	    end
+	 tagged LUI   .it : 
+	    begin
+	       Bit#(32) zext_it_imm = zext(it.imm);
+	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(zext_it_imm << 32'd16) });
+	    end
+	 
+	 tagged SLL   .it : 
+	    begin
+	       Bit#(32) zext_it_shamt = zext(it.shamt);
+	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) << zext_it_shamt )} );
+	    end
+	 tagged SRL   .it : 
+	    begin
+	       Bit#(32) zext_it_shamt = zext(it.shamt);
+	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) >> zext_it_shamt )});
+	    end
+	 tagged SRA   .it : 
+	    begin
+	       Bit#(32) zext_it_shamt = zext(it.shamt);
+	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( rf.rd1(it.rsrc), zext_it_shamt )});
+	    end
+	 tagged SLLV  .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) << rshft(rf.rd2(it.rshamt)) )});
+	 tagged SRLV  .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) >> rshft(rf.rd2(it.rshamt)) )} );
+	 tagged SRAV  .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( rf.rd1(it.rsrc), rshft(rf.rd2(it.rshamt)) ) });
+	 tagged ADDU  .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) + rf.rd2(it.rsrc2) )} );
+	 tagged SUBU  .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) - rf.rd2(it.rsrc2) )} );
+	 tagged AND   .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) & rf.rd2(it.rsrc2) )} );
+	 tagged OR    .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) | rf.rd2(it.rsrc2) )} );
+	 tagged XOR   .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) ^ rf.rd2(it.rsrc2) )} );
+	 tagged NOR   .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(~(rf.rd1(it.rsrc1) | rf.rd2(it.rsrc2)) )} );
+	 tagged SLT   .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:slt( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) });
+	 tagged SLTU  .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sltu( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) });
+
+	 // -- Branches --------------------------------------------------
+
+	 tagged BLEZ  .it : 
+            if ( signedLE( rf.rd1(it.rsrc), 0 ) )
+	       begin
+		  newPC = pc_plus4 + (sext(it.offset) << 2);
+		  branchTaken = True;
+	       end
+
+	 tagged BGTZ  .it : 
+            if ( signedGT( rf.rd1(it.rsrc), 0 ) ) 
+               begin 
+		  newPC = pc_plus4 + (sext(it.offset) << 2);
+		  branchTaken = True;
+	       end
+
+	 tagged BLTZ  .it : 
+            if ( signedLT( rf.rd1(it.rsrc), 0 ) )
+               begin 
+		  newPC = pc_plus4 + (sext(it.offset) << 2);
+		  branchTaken = True;
+	       end
+		  
+	 tagged BGEZ  .it : 
+            if ( signedGE( rf.rd1(it.rsrc), 0 ) )
+               begin 
+		  newPC = pc_plus4 + (sext(it.offset) << 2);		  
+		  branchTaken = True;
+	       end
+
+      tagged BEQ   .it : 
+        if ( rf.rd1(it.rsrc1) == rf.rd2(it.rsrc2) )
+          begin 
+	     newPC = pc_plus4 + (sext(it.offset) << 2);
+	     branchTaken = True;
+	  end
+
+      tagged BNE   .it : 
+        if ( rf.rd1(it.rsrc1) != rf.rd2(it.rsrc2) )
+          begin 
+	     newPC = pc_plus4 + (sext(it.offset) << 2);
+	     branchTaken = True;
+	  end
+
+      // -- Jumps -----------------------------------------------------
+      
+      tagged J     .it : 
+        begin 
+	   newPC = { pc_plus4[31:28], it.target, 2'b0 };
+	   branchTaken = True;
+	end
+      
+      tagged JR    .it : 
+        begin 
+	   newPC = rf.rd1(it.rsrc);
+	   branchTaken = True;
+	end
+
+      tagged JAL   .it : 
+       begin
+          wbQ.enq(tagged WB_ALU {dest:31, data:pc_plus4 });
+          newPC = { pc_plus4[31:28], it.target, 2'b0 };		  
+	  branchTaken = True;
+       end
+
+      tagged JALR  .it : 
+       begin
+          wbQ.enq(tagged WB_ALU {dest:it.rdst, data:pc_plus4 });
+          newPC = rf.rd1(it.rsrc);
+	  branchTaken = True;
+       end
+
+      // -- Cop0 ------------------------------------------------------
+      
+      tagged MTC0  .it : 
+	 begin
+            case ( it.cop0dst )
+	       5'd10 : cp0_statsEn <= unpack(truncate(rf.rd1(it.rsrc)));
+	       5'd21 : cp0_tohost  <= truncate(rf.rd1(it.rsrc));
+	       default :
+	       $display( " RTL-ERROR : %m : Illegal MTC0 cop0dst register!" );
+	    endcase
+	    wbQ.enq(tagged WB_Host 0); //no idea wwhat this actually should be.
+	 end
+
+//this is host stuff?
+      tagged MFC0  .it :
+	 begin
+            case ( it.cop0src )
+	    // not actually an ALU instruction but don't have the format otherwise
+               5'd10 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(cp0_statsEn)) });
+               5'd20 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_fromhost });
+               5'd21 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_tohost   });
+              default : 
+                $display( " RTL-ERROR : %m : Illegal MFC0 cop0src register!" );
+            endcase
+	end
+
+      // -- Illegal ---------------------------------------------------
+
+      default : 
+        $display( " RTL-ERROR : %m : Illegal instruction !" );
+
+    endcase
+
+//evaluate branch prediction
+     Addr ppc = pcQ.first().qnxtpc; //predicted branch
+     if (ppc != newPC) //prediction wrong
+       begin
+	  epoch <= pcQ.first().qepoch + 1;
+	  bp.upd(instrpc, newPC); //update branch predictor
+	  pcQ.clear();
+	  pc <= newPC;
+       end
+     else
+	pcQ.deq();
+
+    if ( cp0_statsEn )
+      num_inst.incr();
+
+  endrule
+
+  rule writeback; // ( stage == Writeback );
+     traceTiny("mkProc", "writeback","W");
+     
+
+    // get what to do off the writeback queue
+     wbQ.deq();
+     case (wbQ.first()) matches
+	tagged WB_ALU {data:.res, dest:.rdst} : rf.wr(rdst, res);
+	tagged WB_Load .regWr : 
+	   begin
+	      dataRespQ.deq();
+	      if (dataRespQ.first() matches tagged LoadResp .ld)
+		rf.wr(truncate(ld.tag), ld.data); // no need to use Rindx from queue?  Duplicate?
+	   end
+	tagged WB_Store : dataRespQ.deq();
+	tagged WB_Host .dat : noAction;
+     endcase
+           
+  endrule
+
+  rule inc_num_cycles;
+    if ( cp0_statsEn )
+      num_cycles.incr();
+  endrule
+
+(* conservative_implicit_conditions *)
+  rule handleCPUToHost;
+   let req <- server_stub.acceptRequest_ReadCPUToHost();
+    case (req)
+     0: server_stub.sendResponse_ReadCPUToHost(cp0_tohost);
+     1: server_stub.sendResponse_ReadCPUToHost(pc);
+     2: server_stub.sendResponse_ReadCPUToHost(zeroExtend(pack(stage)));
+    endcase
+  endrule
+
+ // for now, we don't do anything.
+  rule connectAudioReqResp;
+//    $display("rlm: PROCESSOR copies a datum\n");
+    outAudioFifo.enq(inAudioFifo.first());
+    inAudioFifo.deq;
+  endrule
+
+  // Server items & rules:
+   
+   rule feedInput;
+     let command <- server_stub.acceptRequest_SendUnprocessedStream();
+     AudioProcessorControl ctrl = unpack(truncate(command.ctrl));
+     if(ctrl == EndOfFile)
+	begin
+//	  $display("lsp: PROCESSOR received EOF   ");
+          inAudioFifo.enq(tagged EndOfFile);
+       end
+     else 
+	begin
+//	  $display("lsp: PROCESSOR received Data   ");
+          inAudioFifo.enq(tagged Sample unpack(truncate(command.sample)));
+       end
+   endrule     
+  
+ 
+  //-----------------------------------------------------------
+  // Methods
+
+  interface Client imem_client;
+    interface Get request  = fifoToGet(instReqQ);
+    interface Put response = fifoToPut(instRespQ);
+  endinterface
+
+  interface Client dmem_client;
+    interface Get request  = fifoToGet(dataReqQ);
+    interface Put response = fifoToPut(dataRespQ);
+  endinterface
+
+  interface Get statsEn_get = toGet(asReg(cp0_statsEn));
+
+//  interface CPUToHost tohost;
+//    method Bit#(32) cpuToHost(int req);
+//      return (case (req)
+//       0: cp0_tohost;
+//       1: pc;
+//       2: zeroExtend(pack(stage));
+//      endcase);
+//    endmethod
+//  endinterface
+     
+  interface Get sampleOutput = fifoToGet(outAudioFifo);
+
+endmodule
+
diff -r 220c14f5963c -r f5dfbe28fa59 modules/bluespec/Pygar/core/#trace.awb#
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/modules/bluespec/Pygar/core/#trace.awb#	Fri Apr 30 09:03:10 2010 -0400
@@ -0,0 +1,10 @@
+%name Trace 
+%desc Round-robin memory arbiter 
+
+%provides mem_arb
+
+%attributes 6_375
+
+%public MemArb.bsv
+
+
diff -r 220c14f5963c -r f5dfbe28fa59 modules/bluespec/Pygar/core/ProcTrace.bsv~
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/modules/bluespec/Pygar/core/ProcTrace.bsv~	Fri Apr 30 09:03:10 2010 -0400
@@ -0,0 +1,375 @@
+import Trace::*;
+
+
+//----------------------------------------------------------------------
+// Other typedefs
+//----------------------------------------------------------------------
+
+typedef Bit#(32) Addr;
+typedef Int#(18) Stat;
+
+//----------------------------------------------------------------------
+// Basic instruction type
+//----------------------------------------------------------------------
+
+typedef Bit#(5)  Rindx;
+typedef Bit#(16) Simm;
+typedef Bit#(16) Zimm;
+typedef Bit#(8)  Epoch;
+typedef Bit#(5)  Shamt;
+typedef Bit#(26) Target;
+typedef Bit#(5)  CP0indx;
+typedef Bit#(32) Data;
+
+typedef enum
+{
+ Taken,
+ NotTaken
+}
+  Direction
+    deriving(Bits,Eq);   
+
+
+//----------------------------------------------------------------------
+// Pipeline typedefs
+//----------------------------------------------------------------------
+
+typedef union tagged
+{
+  Tuple2#(Rindx,Data) ALUWB;
+  Rindx               MemWB;
+  Tuple2#(Rindx,Data) CoWB;
+}     
+  WritebackType
+    deriving(Bits,Eq);	 
+
+////////////////////////
+// I Add Writeback queue type
+////////////
+typedef union tagged
+{
+  struct {Bit#(32) data; Rindx dest; } WB_ALU;
+  Bit#(32) WB_Host;
+  Rindx WB_Load;
+  void WB_Store;
+} 
+WBResult deriving(Eq, Bits);
+
+typedef struct{Addr qpc; Addr qnxtpc; Epoch qepoch;} PCStat deriving(Eq, Bits);
+//typedef struct{Addr qpc; Epoch qepoch;} PCStat deriving(Eq, Bits);
+
+typedef union tagged                
+{
+
+  struct { Rindx rbase; Rindx rdst;  Simm offset;  } LW;
+  struct { Rindx rbase; Rindx rsrc;  Simm offset;  } SW; 
+
+  struct { Rindx rsrc;  Rindx rdst;  Simm imm;     } ADDIU;
+  struct { Rindx rsrc;  Rindx rdst;  Simm imm;     } SLTI;
+  struct { Rindx rsrc;  Rindx rdst;  Simm imm;     } SLTIU;
+  struct { Rindx rsrc;  Rindx rdst;  Zimm imm;     } ANDI;
+  struct { Rindx rsrc;  Rindx rdst;  Zimm imm;     } ORI;
+  struct { Rindx rsrc;  Rindx rdst;  Zimm imm;     } XORI;
+  struct {              Rindx rdst;  Zimm imm;     } LUI;
+
+  struct { Rindx rsrc;  Rindx rdst;  Shamt shamt;  } SLL;
+  struct { Rindx rsrc;  Rindx rdst;  Shamt shamt;  } SRL;
+  struct { Rindx rsrc;  Rindx rdst;  Shamt shamt;  } SRA;
+  struct { Rindx rsrc;  Rindx rdst;  Rindx rshamt; } SLLV;
+  struct { Rindx rsrc;  Rindx rdst;  Rindx rshamt; } SRLV;
+  struct { Rindx rsrc;  Rindx rdst;  Rindx rshamt; } SRAV;
+  struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst;   } ADDU;
+  struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst;   } SUBU;
+  struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst;   } AND;
+  struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst;   } OR;
+  struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst;   } XOR;
+  struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst;   } NOR;
+  struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst;   } SLT;
+  struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst;   } SLTU;
+
+  struct { Target target;                          } J;
+  struct { Target target;                          } JAL;
+  struct { Rindx rsrc;                             } JR;
+  struct { Rindx rsrc;  Rindx rdst;                } JALR;
+  struct { Rindx rsrc1; Rindx rsrc2; Simm offset;  } BEQ;
+  struct { Rindx rsrc1; Rindx rsrc2; Simm offset;  } BNE;
+  struct { Rindx rsrc;  Simm offset;               } BLEZ;
+  struct { Rindx rsrc;  Simm offset;               } BGTZ;
+  struct { Rindx rsrc;  Simm offset;               } BLTZ;
+  struct { Rindx rsrc;  Simm offset;               } BGEZ;
+
+  struct { Rindx rdst;  CP0indx cop0src;           } MFC0;
+  struct { Rindx rsrc;  CP0indx cop0dst;           } MTC0; 
+
+  void                                               ILLEGAL;
+
+}
+Instr deriving(Eq);
+
+//----------------------------------------------------------------------
+// Pack and Unpack
+//----------------------------------------------------------------------
+
+Bit#(6) opFUNC  = 6'b000000;  Bit#(6) fcSLL   = 6'b000000;
+Bit#(6) opRT    = 6'b000001;  Bit#(6) fcSRL   = 6'b000010;
+Bit#(6) opRS    = 6'b010000;  Bit#(6) fcSRA   = 6'b000011;
+                              Bit#(6) fcSLLV  = 6'b000100;
+Bit#(6) opLW    = 6'b100011;  Bit#(6) fcSRLV  = 6'b000110;
+Bit#(6) opSW    = 6'b101011;  Bit#(6) fcSRAV  = 6'b000111;
+                              Bit#(6) fcADDU  = 6'b100001;
+Bit#(6) opADDIU = 6'b001001;  Bit#(6) fcSUBU  = 6'b100011;
+Bit#(6) opSLTI  = 6'b001010;  Bit#(6) fcAND   = 6'b100100;
+Bit#(6) opSLTIU = 6'b001011;  Bit#(6) fcOR    = 6'b100101;
+Bit#(6) opANDI  = 6'b001100;  Bit#(6) fcXOR   = 6'b100110;
+Bit#(6) opORI   = 6'b001101;  Bit#(6) fcNOR   = 6'b100111;
+Bit#(6) opXORI  = 6'b001110;  Bit#(6) fcSLT   = 6'b101010;
+Bit#(6) opLUI   = 6'b001111;  Bit#(6) fcSLTU  = 6'b101011;
+
+Bit#(6) opJ     = 6'b000010;
+Bit#(6) opJAL   = 6'b000011;
+Bit#(6) fcJR    = 6'b001000;
+Bit#(6) fcJALR  = 6'b001001;
+Bit#(6) opBEQ   = 6'b000100;
+Bit#(6) opBNE   = 6'b000101;
+Bit#(6) opBLEZ  = 6'b000110;
+Bit#(6) opBGTZ  = 6'b000111;
+Bit#(5) rtBLTZ  = 5'b00000;
+Bit#(5) rtBGEZ  = 5'b00001;
+
+Bit#(5) rsMFC0  = 5'b00000;
+Bit#(5) rsMTC0  = 5'b00100;
+
+instance Bits#(Instr,32);
+
+  // Pack Function
+
+  function Bit#(32) pack( Instr instr );
+
+    case ( instr ) matches
+
+      tagged LW    .it : return { opLW,    it.rbase, it.rdst,  it.offset };
+      tagged SW    .it : return { opSW,    it.rbase, it.rsrc,  it.offset };
+
+      tagged ADDIU .it : return { opADDIU, it.rsrc,  it.rdst,  it.imm                      }; 
+      tagged SLTI  .it : return { opSLTI,  it.rsrc,  it.rdst,  it.imm                      }; 
+      tagged SLTIU .it : return { opSLTIU, it.rsrc,  it.rdst,  it.imm                      }; 
+      tagged ANDI  .it : return { opANDI,  it.rsrc,  it.rdst,  it.imm                      }; 
+      tagged ORI   .it : return { opORI,   it.rsrc,  it.rdst,  it.imm                      }; 
+      tagged XORI  .it : return { opXORI,  it.rsrc,  it.rdst,  it.imm                      }; 
+      tagged LUI   .it : return { opLUI,   5'b0,     it.rdst,  it.imm                      };
+
+      tagged SLL   .it : return { opFUNC,  5'b0,     it.rsrc,  it.rdst,   it.shamt, fcSLL  }; 
+      tagged SRL   .it : return { opFUNC,  5'b0,     it.rsrc,  it.rdst,   it.shamt, fcSRL  }; 
+      tagged SRA   .it : return { opFUNC,  5'b0,     it.rsrc,  it.rdst,   it.shamt, fcSRA  }; 
+
+      tagged SLLV  .it : return { opFUNC,  it.rshamt, it.rsrc, it.rdst,   5'b0,     fcSLLV }; 
+      tagged SRLV  .it : return { opFUNC,  it.rshamt, it.rsrc, it.rdst,   5'b0,     fcSRLV }; 
+      tagged SRAV  .it : return { opFUNC,  it.rshamt, it.rsrc, it.rdst,   5'b0,     fcSRAV }; 
+
+      tagged ADDU  .it : return { opFUNC,  it.rsrc1, it.rsrc2, it.rdst,   5'b0,     fcADDU }; 
+      tagged SUBU  .it : return { opFUNC,  it.rsrc1, it.rsrc2, it.rdst,   5'b0,     fcSUBU }; 
+      tagged AND   .it : return { opFUNC,  it.rsrc1, it.rsrc2, it.rdst,   5'b0,     fcAND  }; 
+      tagged OR    .it : return { opFUNC,  it.rsrc1, it.rsrc2, it.rdst,   5'b0,     fcOR   }; 
+      tagged XOR   .it : return { opFUNC,  it.rsrc1, it.rsrc2, it.rdst,   5'b0,     fcXOR  }; 
+      tagged NOR   .it : return { opFUNC,  it.rsrc1, it.rsrc2, it.rdst,   5'b0,     fcNOR  }; 
+      tagged SLT   .it : return { opFUNC,  it.rsrc1, it.rsrc2, it.rdst,   5'b0,     fcSLT  }; 
+      tagged SLTU  .it : return { opFUNC,  it.rsrc1, it.rsrc2, it.rdst,   5'b0,     fcSLTU }; 
+
+      tagged J     .it : return { opJ,     it.target                                       }; 
+      tagged JAL   .it : return { opJAL,   it.target                                       }; 
+      tagged JR    .it : return { opFUNC,  it.rsrc,  5'b0,     5'b0,      5'b0,     fcJR   };
+      tagged JALR  .it : return { opFUNC,  it.rsrc,  5'b0,     it.rdst,   5'b0,     fcJALR };
+      tagged BEQ   .it : return { opBEQ,   it.rsrc1, it.rsrc2, it.offset                   }; 
+      tagged BNE   .it : return { opBNE,   it.rsrc1, it.rsrc2, it.offset                   }; 
+      tagged BLEZ  .it : return { opBLEZ,  it.rsrc,  5'b0,     it.offset                   }; 
+      tagged BGTZ  .it : return { opBGTZ,  it.rsrc,  5'b0,     it.offset                   }; 
+      tagged BLTZ  .it : return { opRT,    it.rsrc,  rtBLTZ,   it.offset                   }; 
+      tagged BGEZ  .it : return { opRT,    it.rsrc,  rtBGEZ,   it.offset                   }; 
+
+      tagged MFC0  .it : return { opRS,    rsMFC0,   it.rdst,  it.cop0src, 11'b0           }; 
+      tagged MTC0  .it : return { opRS,    rsMTC0,   it.rsrc,  it.cop0dst, 11'b0           };  
+
+    endcase
+
+  endfunction
+
+  // Unpack Function
+
+  function Instr unpack( Bit#(32) instrBits );
+
+    let opcode = instrBits[ 31 : 26 ];
+    let rs     = instrBits[ 25 : 21 ];
+    let rt     = instrBits[ 20 : 16 ];
+    let rd     = instrBits[ 15 : 11 ];
+    let shamt  = instrBits[ 10 :  6 ];
+    let funct  = instrBits[  5 :  0 ];
+    let imm    = instrBits[ 15 :  0 ];
+    let target = instrBits[ 25 :  0 ];
+
+    case ( opcode )
+
+      opLW        : return LW    { rbase:rs, rdst:rt,  offset:imm  };
+      opSW        : return SW    { rbase:rs, rsrc:rt,  offset:imm  };
+      opADDIU     : return ADDIU { rsrc:rs,  rdst:rt,  imm:imm     };
+      opSLTI      : return SLTI  { rsrc:rs,  rdst:rt,  imm:imm     };
+      opSLTIU     : return SLTIU { rsrc:rs,  rdst:rt,  imm:imm     };
+      opANDI      : return ANDI  { rsrc:rs,  rdst:rt,  imm:imm     };
+      opORI       : return ORI   { rsrc:rs,  rdst:rt,  imm:imm     };
+      opXORI      : return XORI  { rsrc:rs,  rdst:rt,  imm:imm     };
+      opLUI       : return LUI   {           rdst:rt,  imm:imm     };
+      opJ         : return J     { target:target                   };
+      opJAL       : return JAL   { target:target                   };
+      opBEQ       : return BEQ   { rsrc1:rs, rsrc2:rt, offset:imm  };
+      opBNE       : return BNE   { rsrc1:rs, rsrc2:rt, offset:imm  };
+      opBLEZ      : return BLEZ  { rsrc:rs,  offset:imm            };
+      opBGTZ      : return BGTZ  { rsrc:rs,  offset:imm            };
+
+      opFUNC  : 
+        case ( funct )
+          fcSLL   : return SLL   { rsrc:rt,  rdst:rd,  shamt:shamt };
+          fcSRL   : return SRL   { rsrc:rt,  rdst:rd,  shamt:shamt };
+          fcSRA   : return SRA   { rsrc:rt,  rdst:rd,  shamt:shamt };
+          fcSLLV  : return SLLV  { rsrc:rt,  rdst:rd,  rshamt:rs   };
+          fcSRLV  : return SRLV  { rsrc:rt,  rdst:rd,  rshamt:rs   };
+          fcSRAV  : return SRAV  { rsrc:rt,  rdst:rd,  rshamt:rs   };
+          fcADDU  : return ADDU  { rsrc1:rs, rsrc2:rt, rdst:rd     };
+          fcSUBU  : return SUBU  { rsrc1:rs, rsrc2:rt, rdst:rd     };
+          fcAND   : return AND   { rsrc1:rs, rsrc2:rt, rdst:rd     };
+          fcOR    : return OR    { rsrc1:rs, rsrc2:rt, rdst:rd     };
+          fcXOR   : return XOR   { rsrc1:rs, rsrc2:rt, rdst:rd     };
+          fcNOR   : return NOR   { rsrc1:rs, rsrc2:rt, rdst:rd     };
+          fcSLT   : return SLT   { rsrc1:rs, rsrc2:rt, rdst:rd     }; 
+          fcSLTU  : return SLTU  { rsrc1:rs, rsrc2:rt, rdst:rd     };
+          fcJR    : return JR    { rsrc:rs                         };
+          fcJALR  : return JALR  { rsrc:rs,  rdst:rd               };
+          default : return ILLEGAL;
+        endcase
+
+      opRT : 
+        case ( rt )
+          rtBLTZ  : return BLTZ  { rsrc:rs,  offset:imm            };
+          rtBGEZ  : return BGEZ  { rsrc:rs,  offset:imm            };
+          default : return ILLEGAL;
+        endcase
+
+      opRS : 
+        case ( rs )
+          rsMFC0  : return MFC0  { rdst:rt,  cop0src:rd            };
+          rsMTC0  : return MTC0  { rsrc:rt,  cop0dst:rd            };
+          default : return ILLEGAL;
+        endcase
+
+      default : return ILLEGAL;
+      
+    endcase
+
+  endfunction
+
+endinstance
+
+//----------------------------------------------------------------------
+// Trace
+//----------------------------------------------------------------------
+
+instance Traceable#(Instr);
+
+  function Action traceTiny( String loc, String ttag, Instr inst );
+    case ( inst ) matches
+
+      tagged LW    .it : $fdisplay(stderr,  " => %s:%s lw", loc,   ttag );
+      tagged SW    .it : $fdisplay(stderr,  " => %s:%s sw", loc,   ttag );
+
+      tagged ADDIU .it : $fdisplay(stderr,  " => %s:%s addi", loc, ttag );
+      tagged SLTI  .it : $fdisplay(stderr,  " => %s:%s sli", loc,  ttag );
+      tagged SLTIU .it : $fdisplay(stderr,  " => %s:%s sliu", loc, ttag );
+      tagged ANDI  .it : $fdisplay(stderr,  " => %s:%s andi", loc, ttag );
+      tagged ORI   .it : $fdisplay(stderr,  " => %s:%s ori", loc,  ttag );
+      tagged XORI  .it : $fdisplay(stderr,  " => %s:%s xori", loc, ttag );
+      tagged LUI   .it : $fdisplay(stderr,  " => %s:%s lui", loc,  ttag );
+                                          
+      tagged SLL   .it : $fdisplay(stderr,  " => %s:%s sll", loc,  ttag );
+      tagged SRL   .it : $fdisplay(stderr,  " => %s:%s srl", loc,  ttag );
+      tagged SRA   .it : $fdisplay(stderr,  " => %s:%s sra", loc,  ttag );
+      tagged SLLV  .it : $fdisplay(stderr,  " => %s:%s sllv", loc, ttag );
+      tagged SRLV  .it : $fdisplay(stderr,  " => %s:%s srlv", loc, ttag );
+      tagged SRAV  .it : $fdisplay(stderr,  " => %s:%s srav", loc, ttag );
+                                          
+      tagged ADDU  .it : $fdisplay(stderr,  " => %s:%s addu", loc, ttag );
+      tagged SUBU  .it : $fdisplay(stderr,  " => %s:%s subu", loc, ttag );
+      tagged AND   .it : $fdisplay(stderr,  " => %s:%s and", loc,  ttag );
+      tagged OR    .it : $fdisplay(stderr,  " => %s:%s or", loc,   ttag );
+      tagged XOR   .it : $fdisplay(stderr,  " => %s:%s xor", loc,  ttag );
+      tagged NOR   .it : $fdisplay(stderr,  " => %s:%s nor", loc,  ttag );
+      tagged SLT   .it : $fdisplay(stderr,  " => %s:%s slt", loc,  ttag );
+      tagged SLTU  .it : $fdisplay(stderr,  " => %s:%s sltu", loc, ttag );
+                                          
+      tagged J     .it : $fdisplay(stderr,  " => %s:%s j", loc,    ttag );
+      tagged JAL   .it : $fdisplay(stderr,  " => %s:%s jal", loc,  ttag );
+      tagged JR    .it : $fdisplay(stderr,  " => %s:%s jr", loc,   ttag );
+      tagged JALR  .it : $fdisplay(stderr,  " => %s:%s jalr", loc, ttag );
+      tagged BEQ   .it : $fdisplay(stderr,  " => %s:%s beq", loc,  ttag );
+      tagged BNE   .it : $fdisplay(stderr,  " => %s:%s bne", loc,  ttag );
+      tagged BLEZ  .it : $fdisplay(stderr,  " => %s:%s blez", loc, ttag );
+      tagged BGTZ  .it : $fdisplay(stderr,  " => %s:%s bgtz", loc, ttag );
+      tagged BLTZ  .it : $fdisplay(stderr,  " => %s:%s bltz", loc, ttag );
+      tagged BGEZ  .it : $fdisplay(stderr,  " => %s:%s bgez", loc, ttag );
+                                           
+      tagged MFC0  .it : $fdisplay(stderr,  " => %s:%s mfc0", loc, ttag );
+      tagged MTC0  .it : $fdisplay(stderr,  " => %s:%s mtc0", loc, ttag );
+
+      tagged ILLEGAL   : $fdisplay(stderr,  " => %s:%s ill", loc,  ttag );
+
+    endcase
+  endfunction
+
+  function Action traceFull( String loc, String ttag, Instr inst );
+    case ( inst ) matches
+
+      tagged LW    .it : $fdisplay(stderr,  " => %s:%s lw r%0d, 0x%x(r%0d)", loc, ttag, it.rdst, it.offset, it.rbase );
+      tagged SW    .it : $fdisplay(stderr,  " => %s:%s sw r%0d, 0x%x(r%0d)", loc, ttag, it.rsrc, it.offset, it.rbase );
+
+      tagged ADDIU .it : $fdisplay(stderr,  " => %s:%s addiu r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm );
+      tagged SLTI  .it : $fdisplay(stderr,  " => %s:%s slti r%0d, r%0d, 0x%x", loc,  ttag, it.rdst, it.rsrc, it.imm );
+      tagged SLTIU .it : $fdisplay(stderr,  " => %s:%s sltiu r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm );
+      tagged ANDI  .it : $fdisplay(stderr,  " => %s:%s andi r%0d, r%0d, 0x%x", loc,  ttag, it.rdst, it.rsrc, it.imm );
+      tagged ORI   .it : $fdisplay(stderr,  " => %s:%s ori r%0d, r%0d, 0x%x", loc,   ttag, it.rdst, it.rsrc, it.imm );
+      tagged XORI  .it : $fdisplay(stderr,  " => %s:%s xori r%0d, r%0d, 0x%x", loc,  ttag, it.rdst, it.rsrc, it.imm );
+      tagged LUI   .it : $fdisplay(stderr,  " => %s:%s lui r%0d, 0x%x", loc,         ttag, it.rdst, it.imm );
+                                      
+      tagged SLL   .it : $fdisplay(stderr,  " => %s:%s sll r%0d, r%0d, %0d", loc,   ttag, it.rdst, it.rsrc, it.shamt );
+      tagged SRL   .it : $fdisplay(stderr,  " => %s:%s srl r%0d, r%0d, %0d", loc,   ttag, it.rdst, it.rsrc, it.shamt );
+      tagged SRA   .it : $fdisplay(stderr,  " => %s:%s sra r%0d, r%0d, %0d", loc,   ttag, it.rdst, it.rsrc, it.shamt );
+      tagged SLLV  .it : $fdisplay(stderr,  " => %s:%s sllv r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc, it.rshamt );
+      tagged SRLV  .it : $fdisplay(stderr,  " => %s:%s srlv r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc, it.rshamt );
+      tagged SRAV  .it : $fdisplay(stderr,  " => %s:%s srav r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc, it.rshamt );
+                                      
+      tagged ADDU  .it : $fdisplay(stderr,  " => %s:%s addu r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 );
+      tagged SUBU  .it : $fdisplay(stderr,  " => %s:%s subu r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 );
+      tagged AND   .it : $fdisplay(stderr,  " => %s:%s and r%0d, r%0d, r%0d", loc,  ttag, it.rdst, it.rsrc1, it.rsrc2 );
+      tagged OR    .it : $fdisplay(stderr,  " => %s:%s or r%0d, r%0d, r%0d", loc,   ttag, it.rdst, it.rsrc1, it.rsrc2 );
+      tagged XOR   .it : $fdisplay(stderr,  " => %s:%s xor r%0d, r%0d, r%0d", loc,  ttag, it.rdst, it.rsrc1, it.rsrc2 );
+      tagged NOR   .it : $fdisplay(stderr,  " => %s:%s nor r%0d, r%0d, r%0d", loc,  ttag, it.rdst, it.rsrc1, it.rsrc2 );
+      tagged SLT   .it : $fdisplay(stderr,  " => %s:%s slt r%0d, r%0d, r%0d", loc,  ttag, it.rdst, it.rsrc1, it.rsrc2 );
+      tagged SLTU  .it : $fdisplay(stderr,  " => %s:%s sltu r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 );
+                                      
+      tagged J     .it : $fdisplay(stderr,  " => %s:%s j 0x%x", loc,    ttag, it.target );
+      tagged JAL   .it : $fdisplay(stderr,  " => %s:%s jal 0x%x", loc,  ttag, it.target );
+      tagged JR    .it : $fdisplay(stderr,  " => %s:%s jr r%0d", loc,   ttag, it.rsrc );
+      tagged JALR  .it : $fdisplay(stderr,  " => %s:%s jalr r%0d", loc, ttag, it.rsrc );
+      tagged BEQ   .it : $fdisplay(stderr,  " => %s:%s beq r%0d, r%0d, 0x%x", loc, ttag, it.rsrc1, it.rsrc2, it.offset );
+      tagged BNE   .it : $fdisplay(stderr,  " => %s:%s bne r%0d, r%0d, 0x%x", loc, ttag, it.rsrc1, it.rsrc2, it.offset );
+      tagged BLEZ  .it : $fdisplay(stderr,  " => %s:%s blez r%0d, 0x%x", loc, ttag, it.rsrc, it.offset );
+      tagged BGTZ  .it : $fdisplay(stderr,  " => %s:%s bgtz r%0d, 0x%x", loc, ttag, it.rsrc, it.offset );
+      tagged BLTZ  .it : $fdisplay(stderr,  " => %s:%s bltz r%0d, 0x%x", loc, ttag, it.rsrc, it.offset );
+      tagged BGEZ  .it : $fdisplay(stderr,  " => %s:%s bgez r%0d, 0x%x", loc, ttag, it.rsrc, it.offset );
+                                      
+      tagged MFC0  .it : $fdisplay(stderr,  " => %s:%s mfc0 r%0d, cpr%0d", loc, ttag, it.rdst, it.cop0src );
+      tagged MTC0  .it : $fdisplay(stderr,  " => %s:%s mtc0 r%0d, cpr%0d", loc, ttag, it.rsrc, it.cop0dst );
+
+      tagged ILLEGAL   : $fdisplay(stderr,  " => %s:%s illegal instruction", loc, ttag );
+
+    endcase
+  endfunction
+
+endinstance
+
diff -r 220c14f5963c -r f5dfbe28fa59 modules/bluespec/Pygar/core/ProcTypes.bsv
--- a/modules/bluespec/Pygar/core/ProcTypes.bsv	Wed Apr 28 12:01:37 2010 -0400
+++ b/modules/bluespec/Pygar/core/ProcTypes.bsv	Fri Apr 30 09:03:10 2010 -0400
@@ -1,5 +1,5 @@
+import Trace::*;
 
-import Trace::*;
 
 //----------------------------------------------------------------------
 // Other typedefs
diff -r 220c14f5963c -r f5dfbe28fa59 modules/bluespec/Pygar/core/Processor.bsv
--- a/modules/bluespec/Pygar/core/Processor.bsv	Wed Apr 28 12:01:37 2010 -0400
+++ b/modules/bluespec/Pygar/core/Processor.bsv	Fri Apr 30 09:03:10 2010 -0400
@@ -49,6 +49,7 @@
 `include "asim/rrr/remote_server_stub_AUDIOCORERRR.bsh"
 `include "asim/provides/common_services.bsh"
 `include "asim/dict/STATS_PROCESSOR.bsh"
+`include "asim/provides/processor_library.bsh"
 
 // Local includes. Look for the correspondingly named .awb files
 // workspace/labs/src/mit-6.375/modules/bluespec/mit-6.375/common/
diff -r 220c14f5963c -r f5dfbe28fa59 modules/bluespec/Pygar/core/audioCore.bsv
--- a/modules/bluespec/Pygar/core/audioCore.bsv	Wed Apr 28 12:01:37 2010 -0400
+++ b/modules/bluespec/Pygar/core/audioCore.bsv	Fri Apr 30 09:03:10 2010 -0400
@@ -62,8 +62,8 @@
 
   mkConnection( proc.statsEn_get,   icache.statsEn_put );
   mkConnection( proc.statsEn_get,   dcache.statsEn_put );
-//  mkConnection( proc.imem_client,   icache.proc_server );
-//  mkConnection( proc.dmem_client,   dcache.proc_server );
+  mkConnection( proc.imem_client,   icache.proc_server );
+  mkConnection( proc.dmem_client,   dcache.proc_server );
   mkConnection( icache.mmem_client, marb.cache0_server );
   mkConnection( dcache.mmem_client, marb.cache1_server );
 
@@ -72,8 +72,5 @@
    interface mmem_client = marb.mmem_client;
       
    interface sampleOutput = proc.sampleOutput;
-  // interface sampleOutput = proc.audioOut;
-  // interface AudioOut audio = proc.audioOut;
-      
 
 endmodule
diff -r 220c14f5963c -r f5dfbe28fa59 modules/bluespec/Pygar/core/proc_trace.awb
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/modules/bluespec/Pygar/core/proc_trace.awb	Fri Apr 30 09:03:10 2010 -0400
@@ -0,0 +1,13 @@
+%name 3-Stage Audio Processor  
+%desc 3-Stage Processor, with audio in one stage per cycle.
+
+%provides processor
+
+%attributes 6_375
+
+%public Processor.bsv ProcTypes.bsv
+%public Processor.dic
+
+
+
+
diff -r 220c14f5963c -r f5dfbe28fa59 modules/bluespec/Pygar/core/proc_types.awb
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/modules/bluespec/Pygar/core/proc_types.awb	Fri Apr 30 09:03:10 2010 -0400
@@ -0,0 +1,10 @@
+%name Round-robin Audio memory arbiter 
+%desc Round-robin memory arbiter 
+
+%provides mem_arb
+
+%attributes 6_375
+
+%public MemArb.bsv
+
+
diff -r 220c14f5963c -r f5dfbe28fa59 modules/bluespec/Pygar/core/proc_types.awb~
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/modules/bluespec/Pygar/core/proc_types.awb~	Fri Apr 30 09:03:10 2010 -0400
@@ -0,0 +1,10 @@
+%name Round-robin Audio memory arbiter 
+%desc Round-robin memory arbiter 
+
+%provides mem_arb
+
+%attributes 6_375
+
+%public MemArb.bsv
+
+
diff -r 220c14f5963c -r f5dfbe28fa59 modules/bluespec/Pygar/core/trace.awb
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/modules/bluespec/Pygar/core/trace.awb	Fri Apr 30 09:03:10 2010 -0400
@@ -0,0 +1,10 @@
+%name Trace Functions
+%desc Contains trace 
+
+%provides trace
+
+%attributes PYGAR
+
+%public Trace.bsv
+
+
diff -r 220c14f5963c -r f5dfbe28fa59 modules/bluespec/Pygar/core/trace.awb~
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/modules/bluespec/Pygar/core/trace.awb~	Fri Apr 30 09:03:10 2010 -0400
@@ -0,0 +1,10 @@
+%name Audio Core Processor Types
+%desc Contains types used in Processor including expanded trace 
+
+%provides proc_types
+
+%attributes PYGAR
+
+%public ProcTypes.bsv
+
+