Mercurial > pygar
changeset 27:e5448315b892 pygar svn.28
[svn r28] Cleaning up duplicate files.
| author | punk |
|---|---|
| date | Fri, 30 Apr 2010 09:09:59 -0400 |
| parents | f5dfbe28fa59 |
| children | 3958de09a7c1 |
| files | modules/bluespec/Pygar/core/BFIFO.bsv modules/bluespec/Pygar/core/BRegFile.bsv modules/bluespec/Pygar/core/BranchPred.bsv modules/bluespec/Pygar/core/DataCacheBlocking.bsv modules/bluespec/Pygar/core/FIRFilterPipeline.bsv modules/bluespec/Pygar/core/InstCacheBlocking.d modules/bluespec/Pygar/core/MemArb.bsv modules/bluespec/Pygar/core/MemTypes.bsv modules/bluespec/Pygar/core/ProcTrace.bsv~ modules/bluespec/Pygar/core/SFIFO.bsv modules/bluespec/Pygar/core/olaCore.bsv modules/bluespec/Pygar/core/proc_trace.awb modules/bluespec/Pygar/core/proc_types.awb modules/bluespec/Pygar/core/proc_types.awb~ |
| diffstat | 14 files changed, 0 insertions(+), 1854 deletions(-) [+] |
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1.1 --- a/modules/bluespec/Pygar/core/BFIFO.bsv Fri Apr 30 09:03:10 2010 -0400 1.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 1.3 @@ -1,222 +0,0 @@ 1.4 -import FIFO::*; 1.5 -import FIFOF::*; 1.6 -import List::*; 1.7 -import Assert::*; 1.8 - 1.9 -module mkBFIFO1( FIFO#(item_t) ) provisos ( Bits#(item_t,item_sz) ); 1.10 - 1.11 - RWire#(item_t) inputWire <- mkRWire(); 1.12 - PulseWire deqEnabled <- mkPulseWire(); 1.13 - PulseWire clearEnabled <- mkPulseWire(); 1.14 - 1.15 - Reg#(item_t) register <- mkRegU(); 1.16 - Reg#(Bool) valid <- mkReg(False); 1.17 - 1.18 - // If there is an input item on the inputWire wire and dequeue did not 1.19 - // execute this cycle then we need to store the item in the register 1.20 - 1.21 - (*fire_when_enabled*) 1.22 - rule update ( True ); 1.23 - case (inputWire.wget()) matches 1.24 - tagged Invalid: 1.25 - if (deqEnabled || clearEnabled) 1.26 - valid <= False; 1.27 - tagged Valid .x: 1.28 - begin 1.29 - register <= x; 1.30 - valid <= !(deqEnabled || clearEnabled); 1.31 - end 1.32 - endcase 1.33 - endrule 1.34 - 1.35 - // On enqueue we write the input item to the inputWire wire 1.36 - 1.37 - method Action enq( item_t item ) if ( !valid ); 1.38 - inputWire.wset(item); 1.39 - endmethod 1.40 - 1.41 - // On dequeue we always invalidate the storage register regardless 1.42 - // of whether or not the item was actually bypassed or not. We also 1.43 - // set a combinational signal so that we know not to move the item 1.44 - // into the register this cycle. 1.45 - 1.46 - method Action deq() if ( valid || isValid(inputWire.wget()) ); 1.47 - deqEnabled.send(); 1.48 - endmethod 1.49 - 1.50 - // We get the item either from the register (if register is valid) or 1.51 - // from the combinational bypasss (if the rwire is valid). 1.52 - 1.53 - method item_t first() if ( valid || isValid(inputWire.wget()) ); 1.54 - if ( valid ) 1.55 - return register; 1.56 - else 1.57 - return unJust(inputWire.wget()); 1.58 - endmethod 1.59 - 1.60 - method Action clear(); 1.61 - clearEnabled.send(); 1.62 - endmethod 1.63 - 1.64 -endmodule 1.65 - 1.66 -module mkSizedBFIFO#(Integer n) ( FIFO#(item_t) ) provisos ( Bits#(item_t,item_sz) ); 1.67 - 1.68 - RWire#(item_t) inputWire <- mkRWire(); 1.69 - PulseWire deqEnabled <- mkPulseWire(); 1.70 - PulseWire clearEnabled <- mkPulseWire(); 1.71 - 1.72 - List#(Reg#(item_t)) registers <- replicateM(n, mkRegU); 1.73 - List#(Reg#(Bool)) valids <- replicateM(n, mkReg(False)); 1.74 - 1.75 - function Nat getNextFree (List#(Reg#(Bool)) vs); 1.76 - 1.77 - Nat res = fromInteger(n - 1); 1.78 - 1.79 - for (Integer x = n - 1; x > -1; x = x - 1) 1.80 - res = !vs[x]._read() ? fromInteger(x) : res; 1.81 - 1.82 - return res; 1.83 - 1.84 - endfunction 1.85 - 1.86 - function Bool notFull(); 1.87 - 1.88 - Bool full = True; 1.89 - 1.90 - for (Integer x = 0; x < length(valids); x = x + 1) 1.91 - full = full && valids[x]._read(); 1.92 - 1.93 - return !full; 1.94 - 1.95 - endfunction 1.96 - // If there is an input item on the inputWire wire and dequeue did not 1.97 - // execute this cycle then we need to store the item in the register 1.98 - 1.99 - rule update ( True ); 1.100 - Nat next = getNextFree(valids); 1.101 - 1.102 - next = (deqEnabled) ? next - 1 : next; 1.103 - 1.104 - (valids[next]) <= isValid(inputWire.wget()); 1.105 - (registers[next]) <= validValue(inputWire.wget()); 1.106 - 1.107 - if (deqEnabled && !clearEnabled) 1.108 - begin 1.109 - 1.110 - for (Nat x = 0; x < (next - 1); x = x + 1) 1.111 - begin 1.112 - (valids[x]) <= valids[x+1]._read(); 1.113 - (registers[x]) <= registers[x+1]._read(); 1.114 - end 1.115 - 1.116 - end 1.117 - else if (clearEnabled) 1.118 - begin 1.119 - 1.120 - for (Integer x = 0; x < n; x = x + 1) 1.121 - (valids[x]) <= False; 1.122 - 1.123 - end 1.124 - endrule 1.125 - 1.126 - // On enqueue we write the input item to the inputWire wire 1.127 - 1.128 - method Action enq( item_t item ) if ( notFull ); 1.129 - inputWire.wset(item); 1.130 - endmethod 1.131 - 1.132 - // On dequeue we always invalidate the storage register regardless 1.133 - // of whether or not the item was actually bypassed or not. We also 1.134 - // set a combinational signal so that we know not to move the item 1.135 - // into the register this cycle. 1.136 - 1.137 - method Action deq() if ( valids[0]._read() || isValid(inputWire.wget()) ); 1.138 - deqEnabled.send(); 1.139 - endmethod 1.140 - 1.141 - // We get the item either from the register (if register is valid) or 1.142 - // from the combinational bypasss (if the rwire is valid). 1.143 - 1.144 - method item_t first() if ( valids[0]._read() || isValid(inputWire.wget()) ); 1.145 - if ( valids[0]._read() ) 1.146 - return registers[0]._read(); 1.147 - else 1.148 - return unJust(inputWire.wget()); 1.149 - endmethod 1.150 - 1.151 - 1.152 - method Action clear(); 1.153 - clearEnabled.send(); 1.154 - endmethod 1.155 - 1.156 -endmodule 1.157 - 1.158 - 1.159 -module mkBFIFOF1( FIFOF#(item_t) ) provisos ( Bits#(item_t,item_sz) ); 1.160 - 1.161 - RWire#(item_t) inputWire <- mkRWire(); 1.162 - RWire#(Bool) deqEnabled <- mkRWire(); 1.163 - 1.164 - Reg#(Maybe#(item_t)) register <- mkReg(Invalid); 1.165 - 1.166 - // If there is an input item on the inputWire wire and dequeue did not 1.167 - // execute this cycle then we need to store the item in the register 1.168 - 1.169 - rule noDeq ( isValid(inputWire.wget()) && !isValid(deqEnabled.wget()) ); 1.170 - register <= inputWire.wget(); 1.171 - endrule 1.172 - 1.173 - // On enqueue we write the input item to the inputWire wire 1.174 - 1.175 - method Action enq( item_t item ) if ( !isValid(register) ); 1.176 - inputWire.wset(item); 1.177 - endmethod 1.178 - 1.179 - // On dequeue we always invalidate the storage register regardless 1.180 - // of whether or not the item was actually bypassed or not. We also 1.181 - // set a combinational signal so that we know not to move the item 1.182 - // into the register this cycle. 1.183 - 1.184 - method Action deq() if ( isValid(register) || isValid(inputWire.wget()) ); 1.185 - register <= Invalid; 1.186 - deqEnabled.wset(True); 1.187 - endmethod 1.188 - 1.189 - // We get the item either from the register (if register is valid) or 1.190 - // from the combinational bypasss (if the rwire is valid). 1.191 - 1.192 - method item_t first() if ( isValid(register) || isValid(inputWire.wget()) ); 1.193 - if ( isValid(register) ) 1.194 - return unJust(register); 1.195 - else 1.196 - return unJust(inputWire.wget()); 1.197 - endmethod 1.198 - 1.199 - // FIFOF adds the following two methods 1.200 - 1.201 - method Bool notFull(); 1.202 - return !isValid(register); 1.203 - endmethod 1.204 - 1.205 - method Bool notEmpty(); 1.206 - return (isValid(register) || isValid(inputWire.wget())); 1.207 - endmethod 1.208 - 1.209 - // Not sure about the clear method ... 1.210 - 1.211 - method Action clear(); 1.212 - dynamicAssert( False, "BFIFO.clear() not implemented yet!" ); 1.213 - endmethod 1.214 - 1.215 -endmodule 1.216 - 1.217 -(* synthesize *) 1.218 -module mkBFIFO_16 (FIFO#(Bit#(16))); 1.219 - 1.220 - let f <- mkBFIFO1(); 1.221 - 1.222 - return f; 1.223 - 1.224 -endmodule 1.225 -
2.1 --- a/modules/bluespec/Pygar/core/BRegFile.bsv Fri Apr 30 09:03:10 2010 -0400 2.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 2.3 @@ -1,36 +0,0 @@ 2.4 -import RegFile::*; 2.5 -import RWire::*; 2.6 -import ProcTypes::*; 2.7 - 2.8 -//----------------------------------------------------------- 2.9 -// Register file module 2.10 -//----------------------------------------------------------- 2.11 - 2.12 -interface BRegFile #(type index_t, type data_t); 2.13 - method Action upd(index_t addr, data_t data); 2.14 - method data_t sub(index_t addr); 2.15 -endinterface 2.16 - 2.17 -module mkBRegFile(RegFile#(index_t, data_t)) 2.18 - provisos (Bits#(index_t, size_index), 2.19 - Bits#(data_t, size_data), 2.20 - Eq#(index_t), 2.21 - Bounded#(index_t) ); 2.22 - 2.23 - RegFile#(index_t, data_t) rf <- mkRegFileWCF(minBound, maxBound); 2.24 - RWire#(Tuple2#(index_t, data_t)) rw <-mkRWire(); 2.25 - 2.26 - method Action upd (index_t r, data_t d); 2.27 - rf.upd(r,d); 2.28 - rw.wset(tuple2(r,d)); 2.29 - endmethod 2.30 - 2.31 - method data_t sub (index_t r); 2.32 - case (rw.wget()) matches 2.33 - tagged Valid {.wr, .d} : 2.34 - return (wr == r) ? d : rf.sub(r); 2.35 - tagged Invalid : return rf.sub(r); 2.36 - endcase 2.37 - endmethod 2.38 - 2.39 -endmodule
3.1 --- a/modules/bluespec/Pygar/core/BranchPred.bsv Fri Apr 30 09:03:10 2010 -0400 3.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 3.3 @@ -1,41 +0,0 @@ 3.4 -import RegFile::*; 3.5 -import ProcTypes::*; 3.6 -import FIFO::*; 3.7 - 3.8 -typedef Maybe#(Addr) BrPred; 3.9 -typedef Bit#(4) BPindx; 3.10 - 3.11 -typedef struct {Addr brpc; Addr nextpc;} BrPair deriving (Bits,Eq); 3.12 - 3.13 -typedef union tagged 3.14 -{ 3.15 - BrPair Valid; 3.16 - void Invalid; 3.17 -} CBranchPath deriving(Bits, Eq); // have the cache start out invalid and add valid values. 3.18 - 3.19 -interface BranchPred; 3.20 - method BrPred get(Addr pres); //returns a maybe type that is invalid if no predition 3.21 - method Action upd(Addr pres, Addr next); 3.22 -endinterface 3.23 - 3.24 -module mkBranchPred(BranchPred); 3.25 - 3.26 - //state variables 3.27 - RegFile#(BPindx, CBranchPath) bcache <- mkRegFileFull(); // cache to hold 16 (based on BPindx) 3.28 - 3.29 - method Action upd(Addr pres, Addr next); 3.30 - BrPair brp; 3.31 - brp = BrPair {brpc:pres, nextpc:next}; 3.32 - bcache.upd(pres[5:2], tagged Valid brp); 3.33 - endmethod 3.34 - 3.35 - method BrPred get(Addr prespc); 3.36 - BPindx rd = prespc[5:2]; 3.37 - let cbp = bcache.sub(rd); 3.38 - if (cbp matches tagged Valid .bp &&& bp.brpc == prespc) //make sure that the read value was actually put there and the full address matches 3.39 - return tagged Valid bp.nextpc; 3.40 - else return Invalid; 3.41 - endmethod 3.42 - 3.43 -endmodule 3.44 -
4.1 --- a/modules/bluespec/Pygar/core/DataCacheBlocking.bsv Fri Apr 30 09:03:10 2010 -0400 4.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 4.3 @@ -1,295 +0,0 @@ 4.4 -// The MIT License 4.5 - 4.6 -// Copyright (c) 2009 Massachusetts Institute of Technology 4.7 - 4.8 -// Permission is hereby granted, free of charge, to any person obtaining a copy 4.9 -// of this software and associated documentation files (the "Software"), to deal 4.10 -// in the Software without restriction, including without limitation the rights 4.11 -// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 4.12 -// copies of the Software, and to permit persons to whom the Software is 4.13 -// furnished to do so, subject to the following conditions: 4.14 - 4.15 -// The above copyright notice and this permission notice shall be included in 4.16 -// all copies or substantial portions of the Software. 4.17 - 4.18 -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 4.19 -// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 4.20 -// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 4.21 -// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 4.22 -// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 4.23 -// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 4.24 -// THE SOFTWARE. 4.25 - 4.26 -import Connectable::*; 4.27 -import GetPut::*; 4.28 -import ClientServer::*; 4.29 -import RegFile::*; 4.30 -import FIFO::*; 4.31 -import FIFOF::*; 4.32 - 4.33 -import BFIFO::*; 4.34 -import MemTypes::*; 4.35 -import ProcTypes::*; 4.36 -import Trace::*; 4.37 - 4.38 -interface DCacheStats; 4.39 - interface Get#(Stat) num_accesses; 4.40 - interface Get#(Stat) num_misses; 4.41 - interface Get#(Stat) num_writebacks; 4.42 -endinterface 4.43 - 4.44 -interface DCache#( type req_t, type resp_t ); 4.45 - 4.46 - // Interface from processor to cache 4.47 - interface Server#(req_t,resp_t) proc_server; 4.48 - 4.49 - // Interface from cache to main memory 4.50 - interface Client#(MainMemReq,MainMemResp) mmem_client; 4.51 - 4.52 - // Interface for enabling/disabling statistics 4.53 - interface Put#(Bool) statsEn_put; 4.54 - 4.55 - // Interface for collecting statistics 4.56 - interface DCacheStats stats; 4.57 - 4.58 -endinterface 4.59 - 4.60 - 4.61 -//---------------------------------------------------------------------- 4.62 -// Cache Types 4.63 -//---------------------------------------------------------------------- 4.64 - 4.65 -typedef 10 CacheLineIndexSz; 4.66 -typedef 20 CacheLineTagSz; 4.67 -typedef 32 CacheLineSz; 4.68 - 4.69 -typedef Bit#(CacheLineIndexSz) CacheLineIndex; 4.70 -typedef Bit#(CacheLineTagSz) CacheLineTag; 4.71 -typedef Bit#(CacheLineSz) CacheLine; 4.72 - 4.73 -typedef enum 4.74 -{ 4.75 - Init, 4.76 - Access, 4.77 - RefillReq, 4.78 - RefillResp 4.79 -} 4.80 -CacheStage 4.81 -deriving (Eq,Bits); 4.82 - 4.83 -//---------------------------------------------------------------------- 4.84 -// Helper functions 4.85 -//---------------------------------------------------------------------- 4.86 - 4.87 -function Bit#(AddrSz) getAddr( DataReq req ); 4.88 - 4.89 - Bit#(AddrSz) addr = ?; 4.90 - case ( req ) matches 4.91 - tagged LoadReq .ld : addr = ld.addr; 4.92 - tagged StoreReq .st : addr = st.addr; 4.93 - endcase 4.94 - 4.95 - return addr; 4.96 - 4.97 -endfunction 4.98 - 4.99 -function CacheLineIndex getCacheLineIndex( DataReq req ); 4.100 - Bit#(AddrSz) addr = getAddr(req); 4.101 - Bit#(CacheLineIndexSz) index = truncate( addr >> 2 ); 4.102 - return index; 4.103 -endfunction 4.104 - 4.105 -function CacheLineTag getCacheLineTag( DataReq req ); 4.106 - Bit#(AddrSz) addr = getAddr(req); 4.107 - Bit#(CacheLineTagSz) tag = truncate( addr >> fromInteger(valueOf(CacheLineIndexSz)) >> 2 ); 4.108 - return tag; 4.109 -endfunction 4.110 - 4.111 -function Bit#(AddrSz) getCacheLineAddr( DataReq req ); 4.112 - Bit#(AddrSz) addr = getAddr(req); 4.113 - return ((addr >> 2) << 2); 4.114 -endfunction 4.115 - 4.116 -//---------------------------------------------------------------------- 4.117 -// Main module 4.118 -//---------------------------------------------------------------------- 4.119 - 4.120 -(* doc = "synthesis attribute ram_style mkDataCache distributed;" *) 4.121 -(* synthesize *) 4.122 -module mkDataCache( DCache#(DataReq,DataResp) ); 4.123 - 4.124 - //----------------------------------------------------------- 4.125 - // State 4.126 - 4.127 - Reg#(CacheStage) stage <- mkReg(Init); 4.128 - 4.129 - RegFile#(CacheLineIndex,Maybe#(CacheLineTag)) cacheTagRam <- mkRegFileFull(); 4.130 - RegFile#(CacheLineIndex,CacheLine) cacheDataRam <- mkRegFileFull(); 4.131 - 4.132 - FIFO#(DataReq) reqQ <- mkFIFO(); 4.133 - FIFOF#(DataResp) respQ <- mkBFIFOF1(); 4.134 - 4.135 - FIFO#(MainMemReq) mainMemReqQ <- mkBFIFO1(); 4.136 - FIFO#(MainMemResp) mainMemRespQ <- mkFIFO(); 4.137 - 4.138 - Reg#(CacheLineIndex) initCounter <- mkReg(1); 4.139 - 4.140 - // Statistics state 4.141 - 4.142 - Reg#(Bool) statsEn <- mkReg(False); 4.143 - 4.144 - Reg#(Stat) num_accesses <- mkReg(0); 4.145 - Reg#(Stat) num_misses <- mkReg(0); 4.146 - Reg#(Stat) num_writebacks <- mkReg(0); 4.147 - 4.148 - //----------------------------------------------------------- 4.149 - // Name some wires 4.150 - 4.151 - let req = reqQ.first(); 4.152 - let reqIndex = getCacheLineIndex(req); 4.153 - let reqTag = getCacheLineTag(req); 4.154 - let reqCacheLineAddr = getCacheLineAddr(req); 4.155 - 4.156 - //----------------------------------------------------------- 4.157 - // Initialize 4.158 - 4.159 - rule init ( stage == Init ); 4.160 - traceTiny("mkDataCacheBlocking", "stage","i"); 4.161 - initCounter <= initCounter + 1; 4.162 - cacheTagRam.upd(initCounter,Invalid); 4.163 - if ( initCounter == 0 ) 4.164 - stage <= Access; 4.165 - endrule 4.166 - 4.167 - //----------------------------------------------------------- 4.168 - // Access cache rule 4.169 - 4.170 - rule access ( (stage == Access) && respQ.notFull() ); 4.171 - 4.172 - // Statistics 4.173 - 4.174 - if ( statsEn ) 4.175 - num_accesses <= num_accesses + 1; 4.176 - 4.177 - 4.178 - // Get the corresponding tag from the rams 4.179 - 4.180 - Maybe#(CacheLineTag) cacheLineTag = cacheTagRam.sub(reqIndex); 4.181 - 4.182 - // Handle cache hits ... 4.183 - 4.184 - if ( isValid(cacheLineTag) && ( unJust(cacheLineTag) == reqTag ) ) 4.185 - begin 4.186 - traceTiny("mkDataCacheBlocking", "hitMiss","h"); 4.187 - reqQ.deq(); 4.188 - 4.189 - case ( req ) matches 4.190 - 4.191 - tagged LoadReq .ld : 4.192 - respQ.enq( LoadResp { tag: ld.tag, data: cacheDataRam.sub(reqIndex) } ); 4.193 - 4.194 - tagged StoreReq .st : 4.195 - begin 4.196 - respQ.enq( StoreResp { tag : st.tag } ); 4.197 - cacheDataRam.upd(reqIndex,st.data); 4.198 - end 4.199 - 4.200 - endcase 4.201 - 4.202 - end 4.203 - 4.204 - // Handle cache misses ... 4.205 - 4.206 - else 4.207 - begin 4.208 - traceTiny("mkDataCacheBlocking", "hitMiss","m"); 4.209 - if ( statsEn ) 4.210 - num_misses <= num_misses + 1; 4.211 - 4.212 - // Currently we don't use dirty bits so we always writeback the data if it is valid 4.213 - 4.214 - if ( isValid(cacheLineTag) ) 4.215 - begin 4.216 - 4.217 - if ( statsEn ) 4.218 - num_writebacks <= num_writebacks + 1; 4.219 - 4.220 - MainMemReq wbReq 4.221 - = StoreReq { tag : 0, 4.222 - addr : { unJust(cacheLineTag), reqIndex, 2'b0 }, 4.223 - data : cacheDataRam.sub(reqIndex) }; 4.224 - 4.225 - mainMemReqQ.enq(wbReq); 4.226 - stage <= RefillReq; 4.227 - end 4.228 - 4.229 - // Otherwise we can issue the refill request now 4.230 - 4.231 - else 4.232 - begin 4.233 - mainMemReqQ.enq( LoadReq { tag: 0, addr: reqCacheLineAddr } ); 4.234 - stage <= RefillResp; 4.235 - end 4.236 - 4.237 - end 4.238 - 4.239 - endrule 4.240 - 4.241 - //----------------------------------------------------------- 4.242 - // Refill request rule 4.243 - 4.244 - rule refillReq ( stage == RefillReq ); 4.245 - traceTiny("mkDataCacheBlocking", "stage","r"); 4.246 - mainMemReqQ.enq( LoadReq { tag: 0, addr: reqCacheLineAddr } ); 4.247 - stage <= RefillResp; 4.248 - endrule 4.249 - 4.250 - //----------------------------------------------------------- 4.251 - // Refill response rule 4.252 - 4.253 - rule refillResp ( stage == RefillResp ); 4.254 - traceTiny("mkDataCacheBlocking", "stage","R"); 4.255 - traceTiny("mkDataCacheBlocking", "refill",mainMemRespQ.first()); 4.256 - 4.257 - // Write the new data into the cache and update the tag 4.258 - 4.259 - mainMemRespQ.deq(); 4.260 - case ( mainMemRespQ.first() ) matches 4.261 - 4.262 - tagged LoadResp .ld : 4.263 - begin 4.264 - cacheTagRam.upd(reqIndex,Valid(reqTag)); 4.265 - cacheDataRam.upd(reqIndex,ld.data); 4.266 - end 4.267 - 4.268 - tagged StoreResp .st : 4.269 - noAction; 4.270 - 4.271 - endcase 4.272 - 4.273 - stage <= Access; 4.274 - endrule 4.275 - 4.276 - //----------------------------------------------------------- 4.277 - // Methods 4.278 - 4.279 - interface Client mmem_client; 4.280 - interface Get request = toGet(mainMemReqQ); 4.281 - interface Put response = toPut(mainMemRespQ); 4.282 - endinterface 4.283 - 4.284 - interface Server proc_server; 4.285 - interface Put request = tracePut("mkDataCacheBlocking", "reqTiny",toPut(reqQ)); 4.286 - interface Get response = traceGet("mkDataCacheBlocking", "respTiny",toGet(respQ)); 4.287 - endinterface 4.288 - 4.289 - interface Put statsEn_put = toPut(asReg(statsEn)); 4.290 - 4.291 - interface DCacheStats stats; 4.292 - interface Get num_accesses = toGet(asReg(num_accesses)); 4.293 - interface Get num_misses = toGet(asReg(num_misses)); 4.294 - interface Get num_writebacks = toGet(asReg(num_writebacks)); 4.295 - endinterface 4.296 - 4.297 -endmodule 4.298 -
5.1 --- a/modules/bluespec/Pygar/core/FIRFilterPipeline.bsv Fri Apr 30 09:03:10 2010 -0400 5.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 5.3 @@ -1,46 +0,0 @@ 5.4 -// The MIT License 5.5 - 5.6 -// Copyright (c) 2009 Massachusetts Institute of Technology 5.7 - 5.8 -// Permission is hereby granted, free of charge, to any person obtaining a copy 5.9 -// of this software and associated documentation files (the "Software"), to deal 5.10 -// in the Software without restriction, including without limitation the rights 5.11 -// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 5.12 -// copies of the Software, and to permit persons to whom the Software is 5.13 -// furnished to do so, subject to the following conditions: 5.14 - 5.15 -// The above copyright notice and this permission notice shall be included in 5.16 -// all copies or substantial portions of the Software. 5.17 - 5.18 -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 5.19 -// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 5.20 -// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 5.21 -// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 5.22 -// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 5.23 -// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 5.24 -// THE SOFTWARE. 5.25 - 5.26 -// Author: Kermin Fleming kfleming@mit.edu 5.27 - 5.28 -import Connectable::*; 5.29 -import GetPut::*; 5.30 -import ClientServer::*; 5.31 -import FIFO::*; 5.32 - 5.33 -//AWB includes 5.34 -`include "asim/provides/low_level_platform_interface.bsh" 5.35 -`include "asim/provides/soft_connections.bsh" 5.36 -`include "asim/provides/common_services.bsh" 5.37 - 5.38 -//Local includes 5.39 -`include "asim/provides/audio_processor_types.bsh" 5.40 -`include "asim/provides/audio_pipeline_types.bsh" 5.41 -`include "asim/provides/fir_filter.bsh" 5.42 - 5.43 -module [Connected_Module] mkAudioPipeline (AudioPipeline); 5.44 - FIRFilter filter <- mkFIRFilter; 5.45 - 5.46 - interface sampleInput = filter.sampleInput; 5.47 - interface sampleOutput = filter.sampleOutput; 5.48 - 5.49 -endmodule
6.1 --- a/modules/bluespec/Pygar/core/InstCacheBlocking.d Fri Apr 30 09:03:10 2010 -0400 6.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 6.3 @@ -1,269 +0,0 @@ 6.4 -// The MIT License 6.5 - 6.6 -// Copyright (c) 2009 Massachusetts Institute of Technology 6.7 - 6.8 -// Permission is hereby granted, free of charge, to any person obtaining a copy 6.9 -// of this software and associated documentation files (the "Software"), to deal 6.10 -// in the Software without restriction, including without limitation the rights 6.11 -// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 6.12 -// copies of the Software, and to permit persons to whom the Software is 6.13 -// furnished to do so, subject to the following conditions: 6.14 - 6.15 -// The above copyright notice and this permission notice shall be included in 6.16 -// all copies or substantial portions of the Software. 6.17 - 6.18 -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 6.19 -// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 6.20 -// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 6.21 -// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 6.22 -// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 6.23 -// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 6.24 -// THE SOFTWARE. 6.25 - 6.26 -import Connectable::*; 6.27 -import GetPut::*; 6.28 -import ClientServer::*; 6.29 -import RegFile::*; 6.30 -import FIFO::*; 6.31 -import FIFOF::*; 6.32 -import RWire::*; 6.33 - 6.34 -import BFIFO::*; 6.35 -import MemTypes::*; 6.36 -import ProcTypes::*; 6.37 -import Trace::*; 6.38 - 6.39 -interface ICacheStats; 6.40 - interface Get#(Stat) num_accesses; 6.41 - interface Get#(Stat) num_misses; 6.42 - interface Get#(Stat) num_evictions; 6.43 -endinterface 6.44 - 6.45 -interface ICache#( type req_t, type resp_t ); 6.46 - 6.47 - // Interface from processor to cache 6.48 - interface Server#(req_t,resp_t) proc_server; 6.49 - 6.50 - // Interface from cache to main memory 6.51 - interface Client#(MainMemReq,MainMemResp) mmem_client; 6.52 - 6.53 - // Interface for enabling/disabling statistics 6.54 - interface Put#(Bool) statsEn_put; 6.55 - 6.56 - // Interface for collecting statistics 6.57 - interface ICacheStats stats; 6.58 - 6.59 -endinterface 6.60 - 6.61 -//---------------------------------------------------------------------- 6.62 -// Cache Types 6.63 -//---------------------------------------------------------------------- 6.64 - 6.65 -typedef 10 CacheLineIndexSz; 6.66 -typedef 20 CacheLineTagSz; 6.67 -typedef 32 CacheLineSz; 6.68 - 6.69 -typedef Bit#(CacheLineIndexSz) CacheLineIndex; 6.70 -typedef Bit#(CacheLineTagSz) CacheLineTag; 6.71 -typedef Bit#(CacheLineSz) CacheLine; 6.72 - 6.73 -typedef enum 6.74 -{ 6.75 - Init, 6.76 - Access, 6.77 - Evict, 6.78 - RefillReq, 6.79 - RefillResp 6.80 -} 6.81 -CacheStage 6.82 -deriving (Eq,Bits); 6.83 - 6.84 -//---------------------------------------------------------------------- 6.85 -// Helper functions 6.86 -//---------------------------------------------------------------------- 6.87 - 6.88 -function Bit#(AddrSz) getAddr( InstReq req ); 6.89 - 6.90 - Bit#(AddrSz) addr = ?; 6.91 - case ( req ) matches 6.92 - tagged LoadReq .ld : addr = ld.addr; 6.93 - tagged StoreReq .st : addr = st.addr; 6.94 - endcase 6.95 - 6.96 - return addr; 6.97 - 6.98 -endfunction 6.99 - 6.100 -function CacheLineIndex getCacheLineIndex( InstReq req ); 6.101 - Bit#(AddrSz) addr = getAddr(req); 6.102 - Bit#(CacheLineIndexSz) index = truncate( addr >> 2 ); 6.103 - return index; 6.104 -endfunction 6.105 - 6.106 -function CacheLineTag getCacheLineTag( InstReq req ); 6.107 - Bit#(AddrSz) addr = getAddr(req); 6.108 - Bit#(CacheLineTagSz) tag = truncate( addr >> fromInteger(valueOf(CacheLineIndexSz)) >> 2 ); 6.109 - return tag; 6.110 -endfunction 6.111 - 6.112 -function Bit#(AddrSz) getCacheLineAddr( InstReq req ); 6.113 - Bit#(AddrSz) addr = getAddr(req); 6.114 - return ((addr >> 2) << 2); 6.115 -endfunction 6.116 - 6.117 -//---------------------------------------------------------------------- 6.118 -// Main module 6.119 -//---------------------------------------------------------------------- 6.120 - 6.121 -(* doc = "synthesis attribute ram_style mkInstCache distributed;" *) 6.122 -(* synthesize *) 6.123 -module mkInstCache( ICache#(InstReq,InstResp) ); 6.124 - 6.125 - //----------------------------------------------------------- 6.126 - // State 6.127 - 6.128 - Reg#(CacheStage) stage <- mkReg(Init); 6.129 - 6.130 - RegFile#(CacheLineIndex,Maybe#(CacheLineTag)) cacheTagRam <- mkRegFileFull(); 6.131 - RegFile#(CacheLineIndex,CacheLine) cacheDataRam <- mkRegFileFull(); 6.132 - 6.133 - FIFO#(InstReq) reqQ <- mkFIFO(); 6.134 - FIFOF#(InstResp) respQ <- mkBFIFOF1(); 6.135 - 6.136 - FIFO#(MainMemReq) mainMemReqQ <- mkBFIFO1(); 6.137 - FIFO#(MainMemResp) mainMemRespQ <- mkFIFO(); 6.138 - 6.139 - Reg#(CacheLineIndex) initCounter <- mkReg(1); 6.140 - 6.141 - // Statistics state 6.142 - 6.143 - Reg#(Bool) statsEn <- mkReg(False); 6.144 - 6.145 - Reg#(Stat) numAccesses <- mkReg(0); 6.146 - Reg#(Stat) numMisses <- mkReg(0); 6.147 - Reg#(Stat) numEvictions <- mkReg(0); 6.148 - 6.149 - //----------------------------------------------------------- 6.150 - // Name some wires 6.151 - 6.152 - let req = reqQ.first(); 6.153 - let reqIndex = getCacheLineIndex(req); 6.154 - let reqTag = getCacheLineTag(req); 6.155 - let reqCacheLineAddr = getCacheLineAddr(req); 6.156 - let refill = mainMemRespQ.first(); 6.157 - 6.158 - //----------------------------------------------------------- 6.159 - // Initialize 6.160 - 6.161 - rule init ( stage == Init ); 6.162 - traceTiny("mkInstCacheBlocking", "stage","i"); 6.163 - initCounter <= initCounter + 1; 6.164 - cacheTagRam.upd(initCounter,Invalid); 6.165 - if ( initCounter == 0 ) 6.166 - stage <= Access; 6.167 - endrule 6.168 - 6.169 - //----------------------------------------------------------- 6.170 - // Cache access rule 6.171 - 6.172 - rule access ( (stage == Access) && respQ.notFull() ); 6.173 - 6.174 - // Statistics 6.175 - 6.176 - if ( statsEn ) 6.177 - numAccesses <= numAccesses + 1; 6.178 - 6.179 - // Check tag and valid bit to see if this is a hit or a miss 6.180 - 6.181 - Maybe#(CacheLineTag) cacheLineTag = cacheTagRam.sub(reqIndex); 6.182 - 6.183 - // Handle cache hits ... 6.184 - 6.185 - if ( isValid(cacheLineTag) && ( unJust(cacheLineTag) == reqTag ) ) 6.186 - begin 6.187 - traceTiny("mkInstCacheBlocking", "hitMiss","h"); 6.188 - reqQ.deq(); 6.189 - 6.190 - case ( req ) matches 6.191 - 6.192 - tagged LoadReq .ld : 6.193 - respQ.enq( LoadResp { tag : ld.tag, data : cacheDataRam.sub(reqIndex) } ); 6.194 - 6.195 - tagged StoreReq .st : 6.196 - $display( " RTL-ERROR : %m : Stores are not allowed on the inst port!" ); 6.197 - 6.198 - endcase 6.199 - 6.200 - end 6.201 - 6.202 - // Handle cache misses - since lines in instruction cache are 6.203 - // never dirty we can always immediately issue a refill request 6.204 - 6.205 - else 6.206 - begin 6.207 - traceTiny("mkInstCacheBlocking", "hitMiss","m"); 6.208 - if ( statsEn ) 6.209 - numMisses <= numMisses + 1; 6.210 - if ( statsEn ) 6.211 - if ( isJust(cacheLineTag) ) 6.212 - numEvictions <= numEvictions + 1; 6.213 - 6.214 - MainMemReq rfReq 6.215 - = LoadReq { tag : 0, 6.216 - addr : reqCacheLineAddr }; 6.217 - 6.218 - mainMemReqQ.enq(rfReq); 6.219 - stage <= RefillResp; 6.220 - end 6.221 - 6.222 - endrule 6.223 - 6.224 - //----------------------------------------------------------- 6.225 - // Refill response rule 6.226 - 6.227 - rule refillResp ( stage == RefillResp ); 6.228 - traceTiny("mkInstCacheBlocking", "stage","R"); 6.229 - traceTiny("mkInstCacheBlocking", "refill",refill); 6.230 - 6.231 - // Write the new data into the cache and update the tag 6.232 - 6.233 - mainMemRespQ.deq(); 6.234 - case ( mainMemRespQ.first() ) matches 6.235 - 6.236 - tagged LoadResp .ld : 6.237 - begin 6.238 - cacheTagRam.upd(reqIndex,Valid(reqTag)); 6.239 - cacheDataRam.upd(reqIndex,ld.data); 6.240 - end 6.241 - 6.242 - tagged StoreResp .st : 6.243 - noAction; 6.244 - 6.245 - endcase 6.246 - 6.247 - stage <= Access; 6.248 - endrule 6.249 - 6.250 - //----------------------------------------------------------- 6.251 - // Methods 6.252 - 6.253 - interface Client mmem_client; 6.254 - interface Get request = fifoToGet(mainMemReqQ); 6.255 - interface Put response = fifoToPut(mainMemRespQ); 6.256 - endinterface 6.257 - 6.258 - interface Server proc_server; 6.259 - interface Put request = tracePut("mkInstCacheBlocking", "reqTiny",toPut(reqQ)); 6.260 - interface Get response = traceGet("mkInstCacheBlocking", "respTiny",toGet(respQ)); 6.261 - endinterface 6.262 - 6.263 - interface Put statsEn_put = toPut(asReg(statsEn)); 6.264 - 6.265 - interface ICacheStats stats; 6.266 - interface Get num_accesses = toGet(asReg(numAccesses)); 6.267 - interface Get num_misses = toGet(asReg(numMisses)); 6.268 - interface Get num_evictions = toGet(asReg(numEvictions)); 6.269 - endinterface 6.270 - 6.271 -endmodule 6.272 -
7.1 --- a/modules/bluespec/Pygar/core/MemArb.bsv Fri Apr 30 09:03:10 2010 -0400 7.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 7.3 @@ -1,141 +0,0 @@ 7.4 -// The MIT License 7.5 - 7.6 -// Copyright (c) 2009 Massachusetts Institute of Technology 7.7 - 7.8 -// Permission is hereby granted, free of charge, to any person obtaining a copy 7.9 -// of this software and associated documentation files (the "Software"), to deal 7.10 -// in the Software without restriction, including without limitation the rights 7.11 -// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7.12 -// copies of the Software, and to permit persons to whom the Software is 7.13 -// furnished to do so, subject to the following conditions: 7.14 - 7.15 -// The above copyright notice and this permission notice shall be included in 7.16 -// all copies or substantial portions of the Software. 7.17 - 7.18 -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 7.19 -// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 7.20 -// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 7.21 -// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 7.22 -// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 7.23 -// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 7.24 -// THE SOFTWARE. 7.25 - 7.26 -import Connectable::*; 7.27 -import GetPut::*; 7.28 -import ClientServer::*; 7.29 -import FIFOF::*; 7.30 -import FIFO::*; 7.31 - 7.32 -import BFIFO::*; 7.33 -import MemTypes::*; 7.34 -import Trace::*; 7.35 - 7.36 -interface MemArb; 7.37 - 7.38 - interface Server#(MainMemReq,MainMemResp) cache0_server; 7.39 - interface Server#(MainMemReq,MainMemResp) cache1_server; 7.40 - interface Client#(MainMemReq,MainMemResp) mmem_client; 7.41 - 7.42 -endinterface 7.43 - 7.44 -typedef enum { REQ0, REQ1 } ReqPtr deriving(Eq,Bits); 7.45 - 7.46 -(* synthesize *) 7.47 -module mkMemArb( MemArb ); 7.48 - 7.49 - //----------------------------------------------------------- 7.50 - // State 7.51 - 7.52 - FIFOF#(MainMemReq) req0Q <- mkFIFOF1(); 7.53 - FIFO#(MainMemResp) resp0Q <- mkFIFO1(); 7.54 - 7.55 - FIFOF#(MainMemReq) req1Q <- mkFIFOF1(); 7.56 - FIFO#(MainMemResp) resp1Q <- mkFIFO1(); 7.57 - 7.58 - FIFO#(MainMemReq) mreqQ <- mkFIFO1(); 7.59 - FIFO#(MainMemResp) mrespQ <- mkFIFO1(); 7.60 - 7.61 - Reg#(ReqPtr) nextReq <- mkReg(REQ0); 7.62 - 7.63 - //----------------------------------------------------------- 7.64 - // Some wires 7.65 - 7.66 - let req0avail = req0Q.notEmpty(); 7.67 - let req1avail = req1Q.notEmpty(); 7.68 - 7.69 - //----------------------------------------------------------- 7.70 - // Rules 7.71 - 7.72 - rule chooseReq0 ( req0avail && (!req1avail || (nextReq == REQ0)) ); 7.73 - traceTiny("mkMemArb", "memArb req0",req0Q.first()); 7.74 - 7.75 - // Rewrite tag field if this is a load ... 7.76 - MainMemReq mreq 7.77 - = case ( req0Q.first() ) matches 7.78 - tagged LoadReq .ld : return LoadReq { tag:0, addr:ld.addr }; 7.79 - tagged StoreReq .st : return req0Q.first(); 7.80 - endcase; 7.81 - 7.82 - // Send out the request 7.83 - mreqQ.enq(mreq); 7.84 - nextReq <= REQ1; 7.85 - req0Q.deq(); 7.86 - 7.87 - endrule 7.88 - 7.89 - rule chooseReq1 ( req1avail && (!req0avail || (nextReq == REQ1)) ); 7.90 - traceTiny("mkMemArb", "memArb req1",req1Q.first); 7.91 - 7.92 - // Rewrite tag field if this is a load ... 7.93 - MainMemReq mreq 7.94 - = case ( req1Q.first() ) matches 7.95 - tagged LoadReq .ld : return LoadReq { tag:1, addr:ld.addr }; 7.96 - tagged StoreReq .st : return req1Q.first(); 7.97 - endcase; 7.98 - 7.99 - // Send out the request 7.100 - mreqQ.enq(mreq); 7.101 - nextReq <= REQ0; 7.102 - req1Q.deq(); 7.103 - 7.104 - endrule 7.105 - 7.106 - rule returnResp; 7.107 - traceTiny("mkMemArb", "resp",mrespQ.first()); 7.108 - 7.109 - // Use tag to figure out where to send response 7.110 - mrespQ.deq(); 7.111 - let tag 7.112 - = case ( mrespQ.first() ) matches 7.113 - tagged LoadResp .ld : return ld.tag; 7.114 - tagged StoreResp .st : return st.tag; 7.115 - endcase; 7.116 - 7.117 - if ( tag == 0 ) 7.118 - resp0Q.enq(mrespQ.first()); 7.119 - else 7.120 - resp1Q.enq(mrespQ.first()); 7.121 - 7.122 - endrule 7.123 - 7.124 - //----------------------------------------------------------- 7.125 - // Methods 7.126 - 7.127 - interface Server cache0_server; 7.128 - interface Put request = toPut(req0Q); 7.129 - interface Get response = toGet(resp0Q); 7.130 - endinterface 7.131 - 7.132 - interface Server cache1_server; 7.133 - interface Put request = toPut(req1Q); 7.134 - interface Get response = toGet(resp1Q); 7.135 - endinterface 7.136 - 7.137 - interface Client mmem_client; 7.138 - interface Get request = toGet(mreqQ); 7.139 - interface Put response = toPut(mrespQ); 7.140 - endinterface 7.141 - 7.142 -endmodule 7.143 - 7.144 -
8.1 --- a/modules/bluespec/Pygar/core/MemTypes.bsv Fri Apr 30 09:03:10 2010 -0400 8.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 8.3 @@ -1,93 +0,0 @@ 8.4 - 8.5 -import Trace::*; 8.6 - 8.7 -//---------------------------------------------------------------------- 8.8 -// Basic memory requests and responses 8.9 -//---------------------------------------------------------------------- 8.10 - 8.11 -typedef union tagged 8.12 -{ 8.13 - struct { Bit#(addrSz) addr; Bit#(tagSz) tag; } LoadReq; 8.14 - struct { Bit#(addrSz) addr; Bit#(tagSz) tag; Bit#(dataSz) data; } StoreReq; 8.15 -} 8.16 -MemReq#( type addrSz, type tagSz, type dataSz ) 8.17 -deriving(Eq,Bits); 8.18 - 8.19 -typedef union tagged 8.20 -{ 8.21 - struct { Bit#(tagSz) tag; Bit#(dataSz) data; } LoadResp; 8.22 - struct { Bit#(tagSz) tag; } StoreResp; 8.23 -} 8.24 -MemResp#( type tagSz, type dataSz ) 8.25 -deriving(Eq,Bits); 8.26 - 8.27 -//---------------------------------------------------------------------- 8.28 -// Specialized req/resp for inst/data/host 8.29 -//---------------------------------------------------------------------- 8.30 - 8.31 -typedef 32 AddrSz; 8.32 -typedef 08 TagSz; 8.33 -typedef 32 DataSz; 8.34 -typedef 32 InstSz; 8.35 -typedef 32 HostDataSz; 8.36 - 8.37 -typedef MemReq#(AddrSz,TagSz,0) InstReq; 8.38 -typedef MemResp#(TagSz,InstSz) InstResp; 8.39 - 8.40 -typedef MemReq#(AddrSz,TagSz,DataSz) DataReq; 8.41 -typedef MemResp#(TagSz,DataSz) DataResp; 8.42 - 8.43 -typedef MemReq#(AddrSz,TagSz,HostDataSz) HostReq; 8.44 -typedef MemResp#(TagSz,HostDataSz) HostResp; 8.45 - 8.46 -//---------------------------------------------------------------------- 8.47 -// Specialized req/resp for main memory 8.48 -//---------------------------------------------------------------------- 8.49 - 8.50 -typedef 32 MainMemAddrSz; 8.51 -typedef 08 MainMemTagSz; 8.52 -typedef 32 MainMemDataSz; 8.53 - 8.54 -typedef MemReq#(MainMemAddrSz,MainMemTagSz,MainMemDataSz) MainMemReq; 8.55 -typedef MemResp#(MainMemTagSz,MainMemDataSz) MainMemResp; 8.56 - 8.57 -//---------------------------------------------------------------------- 8.58 -// Tracing Functions 8.59 -//---------------------------------------------------------------------- 8.60 - 8.61 -instance Traceable#(MemReq#(a,b,c)); 8.62 - 8.63 - function Action traceTiny( String loc, String ttag, MemReq#(a,b,c) req ); 8.64 - case ( req ) matches 8.65 - tagged LoadReq .ld : $fdisplay(stderr, " => %s:%s l%2x", loc, ttag, ld.tag ); 8.66 - tagged StoreReq .st : $fdisplay(stderr, " => %s:%s s%2x", loc, ttag, st.tag ); 8.67 - endcase 8.68 - endfunction 8.69 - 8.70 - function Action traceFull( String loc, String ttag, MemReq#(a,b,c) req ); 8.71 - case ( req ) matches 8.72 - tagged LoadReq .ld : $fdisplay(stderr, " => %s:%s Ld { addr=%x, tag=%x }", loc, ttag, ld.addr, ld.tag ); 8.73 - tagged StoreReq .st : $fdisplay(stderr, " => %s:%s St { addr=%x, tag=%x, data=%x }", loc, ttag, st.addr, st.tag, st.data ); 8.74 - endcase 8.75 - endfunction 8.76 - 8.77 -endinstance 8.78 - 8.79 -instance Traceable#(MemResp#(a,b)); 8.80 - 8.81 - function Action traceTiny( String loc, String ttag, MemResp#(a,b) resp ); 8.82 - case ( resp ) matches 8.83 - tagged LoadResp .ld : $fdisplay(stderr, " => %s:%s l%2x", loc, ttag, ld.tag ); 8.84 - tagged StoreResp .st : $fdisplay(stderr, " => %s:%s s%2x", loc, ttag, st.tag ); 8.85 - endcase 8.86 - endfunction 8.87 - 8.88 - function Action traceFull( String loc, String ttag, MemResp#(a,b) resp ); 8.89 - case ( resp ) matches 8.90 - tagged LoadResp .ld : $fdisplay(stderr, " => %s:%s Ld { tag=%x, data=%x }", loc, ttag, ld.tag, ld.data ); 8.91 - tagged StoreResp .st : $fdisplay(stderr, " => %s:%s St { tag=%x }", loc, ttag, st.tag ); 8.92 - endcase 8.93 - endfunction 8.94 - 8.95 -endinstance 8.96 -
9.1 --- a/modules/bluespec/Pygar/core/ProcTrace.bsv~ Fri Apr 30 09:03:10 2010 -0400 9.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 9.3 @@ -1,375 +0,0 @@ 9.4 -import Trace::*; 9.5 - 9.6 - 9.7 -//---------------------------------------------------------------------- 9.8 -// Other typedefs 9.9 -//---------------------------------------------------------------------- 9.10 - 9.11 -typedef Bit#(32) Addr; 9.12 -typedef Int#(18) Stat; 9.13 - 9.14 -//---------------------------------------------------------------------- 9.15 -// Basic instruction type 9.16 -//---------------------------------------------------------------------- 9.17 - 9.18 -typedef Bit#(5) Rindx; 9.19 -typedef Bit#(16) Simm; 9.20 -typedef Bit#(16) Zimm; 9.21 -typedef Bit#(8) Epoch; 9.22 -typedef Bit#(5) Shamt; 9.23 -typedef Bit#(26) Target; 9.24 -typedef Bit#(5) CP0indx; 9.25 -typedef Bit#(32) Data; 9.26 - 9.27 -typedef enum 9.28 -{ 9.29 - Taken, 9.30 - NotTaken 9.31 -} 9.32 - Direction 9.33 - deriving(Bits,Eq); 9.34 - 9.35 - 9.36 -//---------------------------------------------------------------------- 9.37 -// Pipeline typedefs 9.38 -//---------------------------------------------------------------------- 9.39 - 9.40 -typedef union tagged 9.41 -{ 9.42 - Tuple2#(Rindx,Data) ALUWB; 9.43 - Rindx MemWB; 9.44 - Tuple2#(Rindx,Data) CoWB; 9.45 -} 9.46 - WritebackType 9.47 - deriving(Bits,Eq); 9.48 - 9.49 -//////////////////////// 9.50 -// I Add Writeback queue type 9.51 -//////////// 9.52 -typedef union tagged 9.53 -{ 9.54 - struct {Bit#(32) data; Rindx dest; } WB_ALU; 9.55 - Bit#(32) WB_Host; 9.56 - Rindx WB_Load; 9.57 - void WB_Store; 9.58 -} 9.59 -WBResult deriving(Eq, Bits); 9.60 - 9.61 -typedef struct{Addr qpc; Addr qnxtpc; Epoch qepoch;} PCStat deriving(Eq, Bits); 9.62 -//typedef struct{Addr qpc; Epoch qepoch;} PCStat deriving(Eq, Bits); 9.63 - 9.64 -typedef union tagged 9.65 -{ 9.66 - 9.67 - struct { Rindx rbase; Rindx rdst; Simm offset; } LW; 9.68 - struct { Rindx rbase; Rindx rsrc; Simm offset; } SW; 9.69 - 9.70 - struct { Rindx rsrc; Rindx rdst; Simm imm; } ADDIU; 9.71 - struct { Rindx rsrc; Rindx rdst; Simm imm; } SLTI; 9.72 - struct { Rindx rsrc; Rindx rdst; Simm imm; } SLTIU; 9.73 - struct { Rindx rsrc; Rindx rdst; Zimm imm; } ANDI; 9.74 - struct { Rindx rsrc; Rindx rdst; Zimm imm; } ORI; 9.75 - struct { Rindx rsrc; Rindx rdst; Zimm imm; } XORI; 9.76 - struct { Rindx rdst; Zimm imm; } LUI; 9.77 - 9.78 - struct { Rindx rsrc; Rindx rdst; Shamt shamt; } SLL; 9.79 - struct { Rindx rsrc; Rindx rdst; Shamt shamt; } SRL; 9.80 - struct { Rindx rsrc; Rindx rdst; Shamt shamt; } SRA; 9.81 - struct { Rindx rsrc; Rindx rdst; Rindx rshamt; } SLLV; 9.82 - struct { Rindx rsrc; Rindx rdst; Rindx rshamt; } SRLV; 9.83 - struct { Rindx rsrc; Rindx rdst; Rindx rshamt; } SRAV; 9.84 - struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } ADDU; 9.85 - struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } SUBU; 9.86 - struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } AND; 9.87 - struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } OR; 9.88 - struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } XOR; 9.89 - struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } NOR; 9.90 - struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } SLT; 9.91 - struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } SLTU; 9.92 - 9.93 - struct { Target target; } J; 9.94 - struct { Target target; } JAL; 9.95 - struct { Rindx rsrc; } JR; 9.96 - struct { Rindx rsrc; Rindx rdst; } JALR; 9.97 - struct { Rindx rsrc1; Rindx rsrc2; Simm offset; } BEQ; 9.98 - struct { Rindx rsrc1; Rindx rsrc2; Simm offset; } BNE; 9.99 - struct { Rindx rsrc; Simm offset; } BLEZ; 9.100 - struct { Rindx rsrc; Simm offset; } BGTZ; 9.101 - struct { Rindx rsrc; Simm offset; } BLTZ; 9.102 - struct { Rindx rsrc; Simm offset; } BGEZ; 9.103 - 9.104 - struct { Rindx rdst; CP0indx cop0src; } MFC0; 9.105 - struct { Rindx rsrc; CP0indx cop0dst; } MTC0; 9.106 - 9.107 - void ILLEGAL; 9.108 - 9.109 -} 9.110 -Instr deriving(Eq); 9.111 - 9.112 -//---------------------------------------------------------------------- 9.113 -// Pack and Unpack 9.114 -//---------------------------------------------------------------------- 9.115 - 9.116 -Bit#(6) opFUNC = 6'b000000; Bit#(6) fcSLL = 6'b000000; 9.117 -Bit#(6) opRT = 6'b000001; Bit#(6) fcSRL = 6'b000010; 9.118 -Bit#(6) opRS = 6'b010000; Bit#(6) fcSRA = 6'b000011; 9.119 - Bit#(6) fcSLLV = 6'b000100; 9.120 -Bit#(6) opLW = 6'b100011; Bit#(6) fcSRLV = 6'b000110; 9.121 -Bit#(6) opSW = 6'b101011; Bit#(6) fcSRAV = 6'b000111; 9.122 - Bit#(6) fcADDU = 6'b100001; 9.123 -Bit#(6) opADDIU = 6'b001001; Bit#(6) fcSUBU = 6'b100011; 9.124 -Bit#(6) opSLTI = 6'b001010; Bit#(6) fcAND = 6'b100100; 9.125 -Bit#(6) opSLTIU = 6'b001011; Bit#(6) fcOR = 6'b100101; 9.126 -Bit#(6) opANDI = 6'b001100; Bit#(6) fcXOR = 6'b100110; 9.127 -Bit#(6) opORI = 6'b001101; Bit#(6) fcNOR = 6'b100111; 9.128 -Bit#(6) opXORI = 6'b001110; Bit#(6) fcSLT = 6'b101010; 9.129 -Bit#(6) opLUI = 6'b001111; Bit#(6) fcSLTU = 6'b101011; 9.130 - 9.131 -Bit#(6) opJ = 6'b000010; 9.132 -Bit#(6) opJAL = 6'b000011; 9.133 -Bit#(6) fcJR = 6'b001000; 9.134 -Bit#(6) fcJALR = 6'b001001; 9.135 -Bit#(6) opBEQ = 6'b000100; 9.136 -Bit#(6) opBNE = 6'b000101; 9.137 -Bit#(6) opBLEZ = 6'b000110; 9.138 -Bit#(6) opBGTZ = 6'b000111; 9.139 -Bit#(5) rtBLTZ = 5'b00000; 9.140 -Bit#(5) rtBGEZ = 5'b00001; 9.141 - 9.142 -Bit#(5) rsMFC0 = 5'b00000; 9.143 -Bit#(5) rsMTC0 = 5'b00100; 9.144 - 9.145 -instance Bits#(Instr,32); 9.146 - 9.147 - // Pack Function 9.148 - 9.149 - function Bit#(32) pack( Instr instr ); 9.150 - 9.151 - case ( instr ) matches 9.152 - 9.153 - tagged LW .it : return { opLW, it.rbase, it.rdst, it.offset }; 9.154 - tagged SW .it : return { opSW, it.rbase, it.rsrc, it.offset }; 9.155 - 9.156 - tagged ADDIU .it : return { opADDIU, it.rsrc, it.rdst, it.imm }; 9.157 - tagged SLTI .it : return { opSLTI, it.rsrc, it.rdst, it.imm }; 9.158 - tagged SLTIU .it : return { opSLTIU, it.rsrc, it.rdst, it.imm }; 9.159 - tagged ANDI .it : return { opANDI, it.rsrc, it.rdst, it.imm }; 9.160 - tagged ORI .it : return { opORI, it.rsrc, it.rdst, it.imm }; 9.161 - tagged XORI .it : return { opXORI, it.rsrc, it.rdst, it.imm }; 9.162 - tagged LUI .it : return { opLUI, 5'b0, it.rdst, it.imm }; 9.163 - 9.164 - tagged SLL .it : return { opFUNC, 5'b0, it.rsrc, it.rdst, it.shamt, fcSLL }; 9.165 - tagged SRL .it : return { opFUNC, 5'b0, it.rsrc, it.rdst, it.shamt, fcSRL }; 9.166 - tagged SRA .it : return { opFUNC, 5'b0, it.rsrc, it.rdst, it.shamt, fcSRA }; 9.167 - 9.168 - tagged SLLV .it : return { opFUNC, it.rshamt, it.rsrc, it.rdst, 5'b0, fcSLLV }; 9.169 - tagged SRLV .it : return { opFUNC, it.rshamt, it.rsrc, it.rdst, 5'b0, fcSRLV }; 9.170 - tagged SRAV .it : return { opFUNC, it.rshamt, it.rsrc, it.rdst, 5'b0, fcSRAV }; 9.171 - 9.172 - tagged ADDU .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcADDU }; 9.173 - tagged SUBU .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcSUBU }; 9.174 - tagged AND .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcAND }; 9.175 - tagged OR .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcOR }; 9.176 - tagged XOR .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcXOR }; 9.177 - tagged NOR .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcNOR }; 9.178 - tagged SLT .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcSLT }; 9.179 - tagged SLTU .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcSLTU }; 9.180 - 9.181 - tagged J .it : return { opJ, it.target }; 9.182 - tagged JAL .it : return { opJAL, it.target }; 9.183 - tagged JR .it : return { opFUNC, it.rsrc, 5'b0, 5'b0, 5'b0, fcJR }; 9.184 - tagged JALR .it : return { opFUNC, it.rsrc, 5'b0, it.rdst, 5'b0, fcJALR }; 9.185 - tagged BEQ .it : return { opBEQ, it.rsrc1, it.rsrc2, it.offset }; 9.186 - tagged BNE .it : return { opBNE, it.rsrc1, it.rsrc2, it.offset }; 9.187 - tagged BLEZ .it : return { opBLEZ, it.rsrc, 5'b0, it.offset }; 9.188 - tagged BGTZ .it : return { opBGTZ, it.rsrc, 5'b0, it.offset }; 9.189 - tagged BLTZ .it : return { opRT, it.rsrc, rtBLTZ, it.offset }; 9.190 - tagged BGEZ .it : return { opRT, it.rsrc, rtBGEZ, it.offset }; 9.191 - 9.192 - tagged MFC0 .it : return { opRS, rsMFC0, it.rdst, it.cop0src, 11'b0 }; 9.193 - tagged MTC0 .it : return { opRS, rsMTC0, it.rsrc, it.cop0dst, 11'b0 }; 9.194 - 9.195 - endcase 9.196 - 9.197 - endfunction 9.198 - 9.199 - // Unpack Function 9.200 - 9.201 - function Instr unpack( Bit#(32) instrBits ); 9.202 - 9.203 - let opcode = instrBits[ 31 : 26 ]; 9.204 - let rs = instrBits[ 25 : 21 ]; 9.205 - let rt = instrBits[ 20 : 16 ]; 9.206 - let rd = instrBits[ 15 : 11 ]; 9.207 - let shamt = instrBits[ 10 : 6 ]; 9.208 - let funct = instrBits[ 5 : 0 ]; 9.209 - let imm = instrBits[ 15 : 0 ]; 9.210 - let target = instrBits[ 25 : 0 ]; 9.211 - 9.212 - case ( opcode ) 9.213 - 9.214 - opLW : return LW { rbase:rs, rdst:rt, offset:imm }; 9.215 - opSW : return SW { rbase:rs, rsrc:rt, offset:imm }; 9.216 - opADDIU : return ADDIU { rsrc:rs, rdst:rt, imm:imm }; 9.217 - opSLTI : return SLTI { rsrc:rs, rdst:rt, imm:imm }; 9.218 - opSLTIU : return SLTIU { rsrc:rs, rdst:rt, imm:imm }; 9.219 - opANDI : return ANDI { rsrc:rs, rdst:rt, imm:imm }; 9.220 - opORI : return ORI { rsrc:rs, rdst:rt, imm:imm }; 9.221 - opXORI : return XORI { rsrc:rs, rdst:rt, imm:imm }; 9.222 - opLUI : return LUI { rdst:rt, imm:imm }; 9.223 - opJ : return J { target:target }; 9.224 - opJAL : return JAL { target:target }; 9.225 - opBEQ : return BEQ { rsrc1:rs, rsrc2:rt, offset:imm }; 9.226 - opBNE : return BNE { rsrc1:rs, rsrc2:rt, offset:imm }; 9.227 - opBLEZ : return BLEZ { rsrc:rs, offset:imm }; 9.228 - opBGTZ : return BGTZ { rsrc:rs, offset:imm }; 9.229 - 9.230 - opFUNC : 9.231 - case ( funct ) 9.232 - fcSLL : return SLL { rsrc:rt, rdst:rd, shamt:shamt }; 9.233 - fcSRL : return SRL { rsrc:rt, rdst:rd, shamt:shamt }; 9.234 - fcSRA : return SRA { rsrc:rt, rdst:rd, shamt:shamt }; 9.235 - fcSLLV : return SLLV { rsrc:rt, rdst:rd, rshamt:rs }; 9.236 - fcSRLV : return SRLV { rsrc:rt, rdst:rd, rshamt:rs }; 9.237 - fcSRAV : return SRAV { rsrc:rt, rdst:rd, rshamt:rs }; 9.238 - fcADDU : return ADDU { rsrc1:rs, rsrc2:rt, rdst:rd }; 9.239 - fcSUBU : return SUBU { rsrc1:rs, rsrc2:rt, rdst:rd }; 9.240 - fcAND : return AND { rsrc1:rs, rsrc2:rt, rdst:rd }; 9.241 - fcOR : return OR { rsrc1:rs, rsrc2:rt, rdst:rd }; 9.242 - fcXOR : return XOR { rsrc1:rs, rsrc2:rt, rdst:rd }; 9.243 - fcNOR : return NOR { rsrc1:rs, rsrc2:rt, rdst:rd }; 9.244 - fcSLT : return SLT { rsrc1:rs, rsrc2:rt, rdst:rd }; 9.245 - fcSLTU : return SLTU { rsrc1:rs, rsrc2:rt, rdst:rd }; 9.246 - fcJR : return JR { rsrc:rs }; 9.247 - fcJALR : return JALR { rsrc:rs, rdst:rd }; 9.248 - default : return ILLEGAL; 9.249 - endcase 9.250 - 9.251 - opRT : 9.252 - case ( rt ) 9.253 - rtBLTZ : return BLTZ { rsrc:rs, offset:imm }; 9.254 - rtBGEZ : return BGEZ { rsrc:rs, offset:imm }; 9.255 - default : return ILLEGAL; 9.256 - endcase 9.257 - 9.258 - opRS : 9.259 - case ( rs ) 9.260 - rsMFC0 : return MFC0 { rdst:rt, cop0src:rd }; 9.261 - rsMTC0 : return MTC0 { rsrc:rt, cop0dst:rd }; 9.262 - default : return ILLEGAL; 9.263 - endcase 9.264 - 9.265 - default : return ILLEGAL; 9.266 - 9.267 - endcase 9.268 - 9.269 - endfunction 9.270 - 9.271 -endinstance 9.272 - 9.273 -//---------------------------------------------------------------------- 9.274 -// Trace 9.275 -//---------------------------------------------------------------------- 9.276 - 9.277 -instance Traceable#(Instr); 9.278 - 9.279 - function Action traceTiny( String loc, String ttag, Instr inst ); 9.280 - case ( inst ) matches 9.281 - 9.282 - tagged LW .it : $fdisplay(stderr, " => %s:%s lw", loc, ttag ); 9.283 - tagged SW .it : $fdisplay(stderr, " => %s:%s sw", loc, ttag ); 9.284 - 9.285 - tagged ADDIU .it : $fdisplay(stderr, " => %s:%s addi", loc, ttag ); 9.286 - tagged SLTI .it : $fdisplay(stderr, " => %s:%s sli", loc, ttag ); 9.287 - tagged SLTIU .it : $fdisplay(stderr, " => %s:%s sliu", loc, ttag ); 9.288 - tagged ANDI .it : $fdisplay(stderr, " => %s:%s andi", loc, ttag ); 9.289 - tagged ORI .it : $fdisplay(stderr, " => %s:%s ori", loc, ttag ); 9.290 - tagged XORI .it : $fdisplay(stderr, " => %s:%s xori", loc, ttag ); 9.291 - tagged LUI .it : $fdisplay(stderr, " => %s:%s lui", loc, ttag ); 9.292 - 9.293 - tagged SLL .it : $fdisplay(stderr, " => %s:%s sll", loc, ttag ); 9.294 - tagged SRL .it : $fdisplay(stderr, " => %s:%s srl", loc, ttag ); 9.295 - tagged SRA .it : $fdisplay(stderr, " => %s:%s sra", loc, ttag ); 9.296 - tagged SLLV .it : $fdisplay(stderr, " => %s:%s sllv", loc, ttag ); 9.297 - tagged SRLV .it : $fdisplay(stderr, " => %s:%s srlv", loc, ttag ); 9.298 - tagged SRAV .it : $fdisplay(stderr, " => %s:%s srav", loc, ttag ); 9.299 - 9.300 - tagged ADDU .it : $fdisplay(stderr, " => %s:%s addu", loc, ttag ); 9.301 - tagged SUBU .it : $fdisplay(stderr, " => %s:%s subu", loc, ttag ); 9.302 - tagged AND .it : $fdisplay(stderr, " => %s:%s and", loc, ttag ); 9.303 - tagged OR .it : $fdisplay(stderr, " => %s:%s or", loc, ttag ); 9.304 - tagged XOR .it : $fdisplay(stderr, " => %s:%s xor", loc, ttag ); 9.305 - tagged NOR .it : $fdisplay(stderr, " => %s:%s nor", loc, ttag ); 9.306 - tagged SLT .it : $fdisplay(stderr, " => %s:%s slt", loc, ttag ); 9.307 - tagged SLTU .it : $fdisplay(stderr, " => %s:%s sltu", loc, ttag ); 9.308 - 9.309 - tagged J .it : $fdisplay(stderr, " => %s:%s j", loc, ttag ); 9.310 - tagged JAL .it : $fdisplay(stderr, " => %s:%s jal", loc, ttag ); 9.311 - tagged JR .it : $fdisplay(stderr, " => %s:%s jr", loc, ttag ); 9.312 - tagged JALR .it : $fdisplay(stderr, " => %s:%s jalr", loc, ttag ); 9.313 - tagged BEQ .it : $fdisplay(stderr, " => %s:%s beq", loc, ttag ); 9.314 - tagged BNE .it : $fdisplay(stderr, " => %s:%s bne", loc, ttag ); 9.315 - tagged BLEZ .it : $fdisplay(stderr, " => %s:%s blez", loc, ttag ); 9.316 - tagged BGTZ .it : $fdisplay(stderr, " => %s:%s bgtz", loc, ttag ); 9.317 - tagged BLTZ .it : $fdisplay(stderr, " => %s:%s bltz", loc, ttag ); 9.318 - tagged BGEZ .it : $fdisplay(stderr, " => %s:%s bgez", loc, ttag ); 9.319 - 9.320 - tagged MFC0 .it : $fdisplay(stderr, " => %s:%s mfc0", loc, ttag ); 9.321 - tagged MTC0 .it : $fdisplay(stderr, " => %s:%s mtc0", loc, ttag ); 9.322 - 9.323 - tagged ILLEGAL : $fdisplay(stderr, " => %s:%s ill", loc, ttag ); 9.324 - 9.325 - endcase 9.326 - endfunction 9.327 - 9.328 - function Action traceFull( String loc, String ttag, Instr inst ); 9.329 - case ( inst ) matches 9.330 - 9.331 - tagged LW .it : $fdisplay(stderr, " => %s:%s lw r%0d, 0x%x(r%0d)", loc, ttag, it.rdst, it.offset, it.rbase ); 9.332 - tagged SW .it : $fdisplay(stderr, " => %s:%s sw r%0d, 0x%x(r%0d)", loc, ttag, it.rsrc, it.offset, it.rbase ); 9.333 - 9.334 - tagged ADDIU .it : $fdisplay(stderr, " => %s:%s addiu r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); 9.335 - tagged SLTI .it : $fdisplay(stderr, " => %s:%s slti r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); 9.336 - tagged SLTIU .it : $fdisplay(stderr, " => %s:%s sltiu r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); 9.337 - tagged ANDI .it : $fdisplay(stderr, " => %s:%s andi r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); 9.338 - tagged ORI .it : $fdisplay(stderr, " => %s:%s ori r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); 9.339 - tagged XORI .it : $fdisplay(stderr, " => %s:%s xori r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); 9.340 - tagged LUI .it : $fdisplay(stderr, " => %s:%s lui r%0d, 0x%x", loc, ttag, it.rdst, it.imm ); 9.341 - 9.342 - tagged SLL .it : $fdisplay(stderr, " => %s:%s sll r%0d, r%0d, %0d", loc, ttag, it.rdst, it.rsrc, it.shamt ); 9.343 - tagged SRL .it : $fdisplay(stderr, " => %s:%s srl r%0d, r%0d, %0d", loc, ttag, it.rdst, it.rsrc, it.shamt ); 9.344 - tagged SRA .it : $fdisplay(stderr, " => %s:%s sra r%0d, r%0d, %0d", loc, ttag, it.rdst, it.rsrc, it.shamt ); 9.345 - tagged SLLV .it : $fdisplay(stderr, " => %s:%s sllv r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc, it.rshamt ); 9.346 - tagged SRLV .it : $fdisplay(stderr, " => %s:%s srlv r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc, it.rshamt ); 9.347 - tagged SRAV .it : $fdisplay(stderr, " => %s:%s srav r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc, it.rshamt ); 9.348 - 9.349 - tagged ADDU .it : $fdisplay(stderr, " => %s:%s addu r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); 9.350 - tagged SUBU .it : $fdisplay(stderr, " => %s:%s subu r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); 9.351 - tagged AND .it : $fdisplay(stderr, " => %s:%s and r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); 9.352 - tagged OR .it : $fdisplay(stderr, " => %s:%s or r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); 9.353 - tagged XOR .it : $fdisplay(stderr, " => %s:%s xor r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); 9.354 - tagged NOR .it : $fdisplay(stderr, " => %s:%s nor r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); 9.355 - tagged SLT .it : $fdisplay(stderr, " => %s:%s slt r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); 9.356 - tagged SLTU .it : $fdisplay(stderr, " => %s:%s sltu r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); 9.357 - 9.358 - tagged J .it : $fdisplay(stderr, " => %s:%s j 0x%x", loc, ttag, it.target ); 9.359 - tagged JAL .it : $fdisplay(stderr, " => %s:%s jal 0x%x", loc, ttag, it.target ); 9.360 - tagged JR .it : $fdisplay(stderr, " => %s:%s jr r%0d", loc, ttag, it.rsrc ); 9.361 - tagged JALR .it : $fdisplay(stderr, " => %s:%s jalr r%0d", loc, ttag, it.rsrc ); 9.362 - tagged BEQ .it : $fdisplay(stderr, " => %s:%s beq r%0d, r%0d, 0x%x", loc, ttag, it.rsrc1, it.rsrc2, it.offset ); 9.363 - tagged BNE .it : $fdisplay(stderr, " => %s:%s bne r%0d, r%0d, 0x%x", loc, ttag, it.rsrc1, it.rsrc2, it.offset ); 9.364 - tagged BLEZ .it : $fdisplay(stderr, " => %s:%s blez r%0d, 0x%x", loc, ttag, it.rsrc, it.offset ); 9.365 - tagged BGTZ .it : $fdisplay(stderr, " => %s:%s bgtz r%0d, 0x%x", loc, ttag, it.rsrc, it.offset ); 9.366 - tagged BLTZ .it : $fdisplay(stderr, " => %s:%s bltz r%0d, 0x%x", loc, ttag, it.rsrc, it.offset ); 9.367 - tagged BGEZ .it : $fdisplay(stderr, " => %s:%s bgez r%0d, 0x%x", loc, ttag, it.rsrc, it.offset ); 9.368 - 9.369 - tagged MFC0 .it : $fdisplay(stderr, " => %s:%s mfc0 r%0d, cpr%0d", loc, ttag, it.rdst, it.cop0src ); 9.370 - tagged MTC0 .it : $fdisplay(stderr, " => %s:%s mtc0 r%0d, cpr%0d", loc, ttag, it.rsrc, it.cop0dst ); 9.371 - 9.372 - tagged ILLEGAL : $fdisplay(stderr, " => %s:%s illegal instruction", loc, ttag ); 9.373 - 9.374 - endcase 9.375 - endfunction 9.376 - 9.377 -endinstance 9.378 -
10.1 --- a/modules/bluespec/Pygar/core/SFIFO.bsv Fri Apr 30 09:03:10 2010 -0400 10.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 10.3 @@ -1,213 +0,0 @@ 10.4 - 10.5 -import FIFO::*; 10.6 -import ConfigReg::*; 10.7 -import RWire::*; 10.8 - 10.9 -import List::*; 10.10 -import Monad::*; 10.11 - 10.12 -interface SFIFO#(type alpha_T, type search_T); 10.13 - method Action enq(alpha_T x); 10.14 - method Action deq(); 10.15 - method alpha_T first(); 10.16 - method Action clear(); 10.17 - method Bool find(search_T x); 10.18 - method Bool find2(search_T x); 10.19 - 10.20 -endinterface 10.21 - 10.22 -module mkSFIFO#(function Bool searchfunc(search_T s, alpha_T x)) (SFIFO#(alpha_T, search_T)) 10.23 - provisos 10.24 - (Bits#(alpha_T,asz)); 10.25 - 10.26 - Reg#(alpha_T) f0 <- mkConfigRegU(); 10.27 - Reg#(alpha_T) f1 <- mkConfigRegU(); 10.28 - 10.29 - Reg#(Bool) vf0 <- mkConfigReg(False); 10.30 - Reg#(Bool) vf1 <- mkConfigReg(False); 10.31 - 10.32 - PulseWire edge1 <- mkPulseWire(); 10.33 - 10.34 - method Action enq(alpha_T x) if (!(vf0 && vf1)); 10.35 - if (edge1 || !vf0)//empty or we're dequeueing 10.36 - begin 10.37 - vf0 <= True; //True 10.38 - vf1 <= False; 10.39 - f0 <= x; 10.40 - end 10.41 - else // !vf1 10.42 - begin 10.43 - vf1 <= True; 10.44 - f1 <= x; 10.45 - end 10.46 - endmethod 10.47 - 10.48 - method Action deq() if (vf0); 10.49 - edge1.send(); 10.50 - vf0 <= vf1; 10.51 - f0 <= f1; 10.52 - vf1 <= False; 10.53 - endmethod 10.54 - 10.55 - method alpha_T first() if(vf0); 10.56 - return (f0); 10.57 - endmethod 10.58 - 10.59 - method Action clear(); 10.60 - vf0 <= False; 10.61 - vf1 <= False; 10.62 - endmethod 10.63 - 10.64 - method Bool find(search_T sv); 10.65 - Bool nvf0 = edge1 ? False: vf0; 10.66 - Bool nvf1 = vf1; 10.67 - 10.68 - return (nvf0 && searchfunc(sv, f0) || 10.69 - nvf1 && searchfunc(sv, f1)); 10.70 - endmethod 10.71 - 10.72 - method Bool find2(search_T sv); 10.73 - Bool nvf0 = edge1 ? False: vf0; 10.74 - Bool nvf1 = vf1; 10.75 - 10.76 - return (nvf0 && searchfunc(sv, f0) || 10.77 - nvf1 && searchfunc(sv, f1)); 10.78 - endmethod 10.79 - 10.80 -endmodule 10.81 - 10.82 -module mkSFIFO1#(function Bool searchfunc(search_T s, alpha_T x)) (SFIFO#(alpha_T, search_T)) 10.83 - provisos 10.84 - (Bits#(alpha_T,asz), Eq#(alpha_T)); 10.85 - 10.86 - Reg#(alpha_T) f0 <- mkConfigRegU; 10.87 - 10.88 - Reg#(Bool) vf0 <- mkConfigReg(False); 10.89 - 10.90 - PulseWire edge1 <- mkPulseWire(); 10.91 - 10.92 - method Action enq(alpha_T x) if (!vf0); 10.93 - vf0 <= True; //True 10.94 - f0 <= x; 10.95 - endmethod 10.96 - 10.97 - method Action deq() if (vf0); 10.98 - edge1.send(); 10.99 - vf0 <= False; 10.100 - endmethod 10.101 - 10.102 - method alpha_T first() if(vf0); 10.103 - return (f0); 10.104 - endmethod 10.105 - 10.106 - method Action clear(); 10.107 - vf0 <= False; 10.108 - endmethod 10.109 - 10.110 - method Bool find(search_T sv); 10.111 - Bool nvf0 = edge1 ? False: vf0; 10.112 - 10.113 - return (nvf0 && searchfunc(sv, f0)); 10.114 - endmethod 10.115 - 10.116 - method Bool find2(search_T sv); 10.117 - Bool nvf0 = edge1 ? False: vf0; 10.118 - return (nvf0 && searchfunc(sv, f0)); 10.119 - endmethod 10.120 - 10.121 -endmodule 10.122 - 10.123 -module mkSizedSFIFOInternal#(Integer n, 10.124 - function Bool searchfunc1(search_T s, alpha_T x), 10.125 - function Bool searchfunc2(search_T s, alpha_T x)) (SFIFO#(alpha_T, search_T)) 10.126 - 10.127 - provisos ( Bits#(alpha_T,alpha_SZ) ); 10.128 - 10.129 - List#(Reg#(alpha_T)) registers <- replicateM(n, mkRegU); 10.130 - List#(Reg#(Bool)) valids <- replicateM(n, mkReg(False)); 10.131 - 10.132 - function Nat getNextFree (List#(Reg#(Bool)) vs); 10.133 - 10.134 - Nat res = fromInteger(n - 1); 10.135 - 10.136 - for (Integer x = n - 1; x > -1; x = x - 1) 10.137 - res = !vs[x]._read() ? fromInteger(x) : res; 10.138 - 10.139 - return res; 10.140 - 10.141 - endfunction 10.142 - 10.143 - function Bool notFull(); 10.144 - 10.145 - Bool full = True; 10.146 - 10.147 - for (Integer x = 0; x < n; x = x + 1) 10.148 - full = full && valids[x]._read(); 10.149 - 10.150 - return !full; 10.151 - 10.152 - endfunction 10.153 - 10.154 - method Action enq( alpha_T item ) if ( notFull() ); 10.155 - 10.156 - Nat k = getNextFree(valids); 10.157 - select(valids, k)._write(True); 10.158 - select(registers, k)._write(item); 10.159 - 10.160 - endmethod 10.161 - 10.162 - method Action deq() if ( valids[0]._read() ); 10.163 - 10.164 - for (Integer x = 0; x < (n-1); x = x + 1) 10.165 - begin 10.166 - 10.167 - (registers[x]) <= registers[x + 1]._read(); 10.168 - (valids[x]) <= valids[x + 1]._read(); 10.169 - 10.170 - end 10.171 - (valids[n-1]) <= False; 10.172 - endmethod 10.173 - 10.174 - method alpha_T first() if ( valids[0]._read() ); 10.175 - return registers[0]._read(); 10.176 - endmethod 10.177 - 10.178 - method Bool find(search_T sv); 10.179 - Bool res = False; 10.180 - 10.181 - for (Integer x = 0; x < n; x = x + 1) 10.182 - if ( valids[x]._read() && searchfunc1(sv, registers[x]._read()) ) 10.183 - res = True; 10.184 - 10.185 - return res; 10.186 - 10.187 - endmethod 10.188 - 10.189 - method Bool find2(search_T sv); 10.190 - Bool res = False; 10.191 - 10.192 - for (Integer x = 0; x < n; x = x + 1) 10.193 - if ( valids[x]._read() && searchfunc2(sv, registers[x]._read()) ) 10.194 - res = True; 10.195 - 10.196 - return res; 10.197 - 10.198 - endmethod 10.199 - 10.200 - method Action clear(); 10.201 - 10.202 - for (Integer x = 0; x < n; x = x + 1) 10.203 - (valids[x]) <= False; 10.204 - 10.205 - endmethod 10.206 - 10.207 -endmodule 10.208 - 10.209 -module mkSizedSFIFO#(Integer n, function Bool searchfunc(search_T s, alpha_T x)) (SFIFO#(alpha_T, search_T)) 10.210 - provisos 10.211 - (Bits#(alpha_T,asz)); 10.212 - 10.213 - let foo <- mkSizedSFIFOInternal(n, searchfunc, searchfunc); 10.214 - return foo; 10.215 - 10.216 -endmodule
11.1 --- a/modules/bluespec/Pygar/core/olaCore.bsv Fri Apr 30 09:03:10 2010 -0400 11.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 11.3 @@ -1,90 +0,0 @@ 11.4 -// The MIT License 11.5 - 11.6 -// Copyright (c) 2009 Massachusetts Institute of Technology 11.7 - 11.8 -// Permission is hereby granted, free of charge, to any person obtaining a copy 11.9 -// of this software and associated documentation files (the "Software"), to deal 11.10 -// in the Software without restriction, including without limitation the rights 11.11 -// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11.12 -// copies of the Software, and to permit persons to whom the Software is 11.13 -// furnished to do so, subject to the following conditions: 11.14 - 11.15 -// The above copyright notice and this permission notice shall be included in 11.16 -// all copies or substantial portions of the Software. 11.17 - 11.18 -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 11.19 -// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 11.20 -// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 11.21 -// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 11.22 -// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 11.23 -// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 11.24 -// THE SOFTWARE. 11.25 - 11.26 -import Connectable::*; 11.27 -import GetPut::*; 11.28 -import ClientServer::*; 11.29 - 11.30 -import DataCacheBlocking::*; 11.31 -import InstCacheBlocking::*; 11.32 -import Processor::*; 11.33 -import MemArb::*; 11.34 -import MemTypes::*; 11.35 - 11.36 -`include "asim/provides/data_cache.bsh" 11.37 -`include "asim/provides/instruction_cache.bsh" 11.38 -`include "asim/provides/processor_library.bsh" 11.39 - 11.40 -//interface CoreStats; 11.41 -// interface DCacheStats dcache; 11.42 - //interface ICacheStats icache; 11.43 - //interface ProcStats proc; 11.44 -//endinterface 11.45 - 11.46 -interface Core; 11.47 - 11.48 - // Interface from core to main memory 11.49 - interface Client#(MainMemReq,MainMemResp) mmem_client; 11.50 - 11.51 - // Statistics 11.52 -// interface CoreStats stats; 11.53 - 11.54 - // CPU to Host 11.55 - interface CPUToHost tohost; 11.56 - 11.57 - // Interface to Audio Pipeline 11.58 - interface Audio audio; 11.59 - 11.60 -endinterface 11.61 - 11.62 -(* synthesize *) 11.63 -module mkCore(Core); 11.64 - 11.65 - // Instantiate the modules 11.66 - Proc proc <- mkProc(); 11.67 - ICache#(InstReq,InstResp) icache <- mkInstCache(); 11.68 - DCache#(DataReq,DataResp) dcache <- mkDataCache(); 11.69 - MemArb marb <- mkMemArb(); 11.70 - 11.71 - // Internal connections 11.72 - mkConnection( proc.statsEn_get, icache.statsEn_put ); 11.73 - mkConnection( proc.statsEn_get, dcache.statsEn_put ); 11.74 - mkConnection( proc.imem_client, icache.proc_server ); 11.75 - mkConnection( proc.dmem_client, dcache.proc_server ); 11.76 - mkConnection( icache.mmem_client, marb.cache0_server ); 11.77 - mkConnection( dcache.mmem_client, marb.cache1_server ); 11.78 - 11.79 - // Methods 11.80 - interface mmem_client = marb.mmem_client; 11.81 - 11.82 -// interface CoreStats stats; 11.83 -// interface dcache = dcache.stats; 11.84 -// interface icache = icache.stats; 11.85 -// interface proc = proc.stats; 11.86 -// endinterface 11.87 - 11.88 - interface CPUToHost tohost = proc.tohost; 11.89 - 11.90 - interface Audio audio = proc.audio; 11.91 - 11.92 -endmodule 11.93 -
12.1 --- a/modules/bluespec/Pygar/core/proc_trace.awb Fri Apr 30 09:03:10 2010 -0400 12.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 12.3 @@ -1,13 +0,0 @@ 12.4 -%name 3-Stage Audio Processor 12.5 -%desc 3-Stage Processor, with audio in one stage per cycle. 12.6 - 12.7 -%provides processor 12.8 - 12.9 -%attributes 6_375 12.10 - 12.11 -%public Processor.bsv ProcTypes.bsv 12.12 -%public Processor.dic 12.13 - 12.14 - 12.15 - 12.16 -
13.1 --- a/modules/bluespec/Pygar/core/proc_types.awb Fri Apr 30 09:03:10 2010 -0400 13.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 13.3 @@ -1,10 +0,0 @@ 13.4 -%name Round-robin Audio memory arbiter 13.5 -%desc Round-robin memory arbiter 13.6 - 13.7 -%provides mem_arb 13.8 - 13.9 -%attributes 6_375 13.10 - 13.11 -%public MemArb.bsv 13.12 - 13.13 -
14.1 --- a/modules/bluespec/Pygar/core/proc_types.awb~ Fri Apr 30 09:03:10 2010 -0400 14.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 14.3 @@ -1,10 +0,0 @@ 14.4 -%name Round-robin Audio memory arbiter 14.5 -%desc Round-robin memory arbiter 14.6 - 14.7 -%provides mem_arb 14.8 - 14.9 -%attributes 6_375 14.10 - 14.11 -%public MemArb.bsv 14.12 - 14.13 -