# HG changeset patch # User punk # Date 1272632999 14400 # Node ID e5448315b892221f0585707c43ef372ecf20d5b0 # Parent f5dfbe28fa5949d27fb23d9ee92ed121b939b446 [svn r28] Cleaning up duplicate files. diff -r f5dfbe28fa59 -r e5448315b892 modules/bluespec/Pygar/core/BFIFO.bsv --- a/modules/bluespec/Pygar/core/BFIFO.bsv Fri Apr 30 09:03:10 2010 -0400 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,222 +0,0 @@ -import FIFO::*; -import FIFOF::*; -import List::*; -import Assert::*; - -module mkBFIFO1( FIFO#(item_t) ) provisos ( Bits#(item_t,item_sz) ); - - RWire#(item_t) inputWire <- mkRWire(); - PulseWire deqEnabled <- mkPulseWire(); - PulseWire clearEnabled <- mkPulseWire(); - - Reg#(item_t) register <- mkRegU(); - Reg#(Bool) valid <- mkReg(False); - - // If there is an input item on the inputWire wire and dequeue did not - // execute this cycle then we need to store the item in the register - - (*fire_when_enabled*) - rule update ( True ); - case (inputWire.wget()) matches - tagged Invalid: - if (deqEnabled || clearEnabled) - valid <= False; - tagged Valid .x: - begin - register <= x; - valid <= !(deqEnabled || clearEnabled); - end - endcase - endrule - - // On enqueue we write the input item to the inputWire wire - - method Action enq( item_t item ) if ( !valid ); - inputWire.wset(item); - endmethod - - // On dequeue we always invalidate the storage register regardless - // of whether or not the item was actually bypassed or not. We also - // set a combinational signal so that we know not to move the item - // into the register this cycle. - - method Action deq() if ( valid || isValid(inputWire.wget()) ); - deqEnabled.send(); - endmethod - - // We get the item either from the register (if register is valid) or - // from the combinational bypasss (if the rwire is valid). - - method item_t first() if ( valid || isValid(inputWire.wget()) ); - if ( valid ) - return register; - else - return unJust(inputWire.wget()); - endmethod - - method Action clear(); - clearEnabled.send(); - endmethod - -endmodule - -module mkSizedBFIFO#(Integer n) ( FIFO#(item_t) ) provisos ( Bits#(item_t,item_sz) ); - - RWire#(item_t) inputWire <- mkRWire(); - PulseWire deqEnabled <- mkPulseWire(); - PulseWire clearEnabled <- mkPulseWire(); - - List#(Reg#(item_t)) registers <- replicateM(n, mkRegU); - List#(Reg#(Bool)) valids <- replicateM(n, mkReg(False)); - - function Nat getNextFree (List#(Reg#(Bool)) vs); - - Nat res = fromInteger(n - 1); - - for (Integer x = n - 1; x > -1; x = x - 1) - res = !vs[x]._read() ? fromInteger(x) : res; - - return res; - - endfunction - - function Bool notFull(); - - Bool full = True; - - for (Integer x = 0; x < length(valids); x = x + 1) - full = full && valids[x]._read(); - - return !full; - - endfunction - // If there is an input item on the inputWire wire and dequeue did not - // execute this cycle then we need to store the item in the register - - rule update ( True ); - Nat next = getNextFree(valids); - - next = (deqEnabled) ? next - 1 : next; - - (valids[next]) <= isValid(inputWire.wget()); - (registers[next]) <= validValue(inputWire.wget()); - - if (deqEnabled && !clearEnabled) - begin - - for (Nat x = 0; x < (next - 1); x = x + 1) - begin - (valids[x]) <= valids[x+1]._read(); - (registers[x]) <= registers[x+1]._read(); - end - - end - else if (clearEnabled) - begin - - for (Integer x = 0; x < n; x = x + 1) - (valids[x]) <= False; - - end - endrule - - // On enqueue we write the input item to the inputWire wire - - method Action enq( item_t item ) if ( notFull ); - inputWire.wset(item); - endmethod - - // On dequeue we always invalidate the storage register regardless - // of whether or not the item was actually bypassed or not. We also - // set a combinational signal so that we know not to move the item - // into the register this cycle. - - method Action deq() if ( valids[0]._read() || isValid(inputWire.wget()) ); - deqEnabled.send(); - endmethod - - // We get the item either from the register (if register is valid) or - // from the combinational bypasss (if the rwire is valid). - - method item_t first() if ( valids[0]._read() || isValid(inputWire.wget()) ); - if ( valids[0]._read() ) - return registers[0]._read(); - else - return unJust(inputWire.wget()); - endmethod - - - method Action clear(); - clearEnabled.send(); - endmethod - -endmodule - - -module mkBFIFOF1( FIFOF#(item_t) ) provisos ( Bits#(item_t,item_sz) ); - - RWire#(item_t) inputWire <- mkRWire(); - RWire#(Bool) deqEnabled <- mkRWire(); - - Reg#(Maybe#(item_t)) register <- mkReg(Invalid); - - // If there is an input item on the inputWire wire and dequeue did not - // execute this cycle then we need to store the item in the register - - rule noDeq ( isValid(inputWire.wget()) && !isValid(deqEnabled.wget()) ); - register <= inputWire.wget(); - endrule - - // On enqueue we write the input item to the inputWire wire - - method Action enq( item_t item ) if ( !isValid(register) ); - inputWire.wset(item); - endmethod - - // On dequeue we always invalidate the storage register regardless - // of whether or not the item was actually bypassed or not. We also - // set a combinational signal so that we know not to move the item - // into the register this cycle. - - method Action deq() if ( isValid(register) || isValid(inputWire.wget()) ); - register <= Invalid; - deqEnabled.wset(True); - endmethod - - // We get the item either from the register (if register is valid) or - // from the combinational bypasss (if the rwire is valid). - - method item_t first() if ( isValid(register) || isValid(inputWire.wget()) ); - if ( isValid(register) ) - return unJust(register); - else - return unJust(inputWire.wget()); - endmethod - - // FIFOF adds the following two methods - - method Bool notFull(); - return !isValid(register); - endmethod - - method Bool notEmpty(); - return (isValid(register) || isValid(inputWire.wget())); - endmethod - - // Not sure about the clear method ... - - method Action clear(); - dynamicAssert( False, "BFIFO.clear() not implemented yet!" ); - endmethod - -endmodule - -(* synthesize *) -module mkBFIFO_16 (FIFO#(Bit#(16))); - - let f <- mkBFIFO1(); - - return f; - -endmodule - diff -r f5dfbe28fa59 -r e5448315b892 modules/bluespec/Pygar/core/BRegFile.bsv --- a/modules/bluespec/Pygar/core/BRegFile.bsv Fri Apr 30 09:03:10 2010 -0400 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,36 +0,0 @@ -import RegFile::*; -import RWire::*; -import ProcTypes::*; - -//----------------------------------------------------------- -// Register file module -//----------------------------------------------------------- - -interface BRegFile #(type index_t, type data_t); - method Action upd(index_t addr, data_t data); - method data_t sub(index_t addr); -endinterface - -module mkBRegFile(RegFile#(index_t, data_t)) - provisos (Bits#(index_t, size_index), - Bits#(data_t, size_data), - Eq#(index_t), - Bounded#(index_t) ); - - RegFile#(index_t, data_t) rf <- mkRegFileWCF(minBound, maxBound); - RWire#(Tuple2#(index_t, data_t)) rw <-mkRWire(); - - method Action upd (index_t r, data_t d); - rf.upd(r,d); - rw.wset(tuple2(r,d)); - endmethod - - method data_t sub (index_t r); - case (rw.wget()) matches - tagged Valid {.wr, .d} : - return (wr == r) ? d : rf.sub(r); - tagged Invalid : return rf.sub(r); - endcase - endmethod - -endmodule diff -r f5dfbe28fa59 -r e5448315b892 modules/bluespec/Pygar/core/BranchPred.bsv --- a/modules/bluespec/Pygar/core/BranchPred.bsv Fri Apr 30 09:03:10 2010 -0400 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,41 +0,0 @@ -import RegFile::*; -import ProcTypes::*; -import FIFO::*; - -typedef Maybe#(Addr) BrPred; -typedef Bit#(4) BPindx; - -typedef struct {Addr brpc; Addr nextpc;} BrPair deriving (Bits,Eq); - -typedef union tagged -{ - BrPair Valid; - void Invalid; -} CBranchPath deriving(Bits, Eq); // have the cache start out invalid and add valid values. - -interface BranchPred; - method BrPred get(Addr pres); //returns a maybe type that is invalid if no predition - method Action upd(Addr pres, Addr next); -endinterface - -module mkBranchPred(BranchPred); - - //state variables - RegFile#(BPindx, CBranchPath) bcache <- mkRegFileFull(); // cache to hold 16 (based on BPindx) - - method Action upd(Addr pres, Addr next); - BrPair brp; - brp = BrPair {brpc:pres, nextpc:next}; - bcache.upd(pres[5:2], tagged Valid brp); - endmethod - - method BrPred get(Addr prespc); - BPindx rd = prespc[5:2]; - let cbp = bcache.sub(rd); - if (cbp matches tagged Valid .bp &&& bp.brpc == prespc) //make sure that the read value was actually put there and the full address matches - return tagged Valid bp.nextpc; - else return Invalid; - endmethod - -endmodule - diff -r f5dfbe28fa59 -r e5448315b892 modules/bluespec/Pygar/core/DataCacheBlocking.bsv --- a/modules/bluespec/Pygar/core/DataCacheBlocking.bsv Fri Apr 30 09:03:10 2010 -0400 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,295 +0,0 @@ -// The MIT License - -// Copyright (c) 2009 Massachusetts Institute of Technology - -// Permission is hereby granted, free of charge, to any person obtaining a copy -// of this software and associated documentation files (the "Software"), to deal -// in the Software without restriction, including without limitation the rights -// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -// copies of the Software, and to permit persons to whom the Software is -// furnished to do so, subject to the following conditions: - -// The above copyright notice and this permission notice shall be included in -// all copies or substantial portions of the Software. - -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -// THE SOFTWARE. - -import Connectable::*; -import GetPut::*; -import ClientServer::*; -import RegFile::*; -import FIFO::*; -import FIFOF::*; - -import BFIFO::*; -import MemTypes::*; -import ProcTypes::*; -import Trace::*; - -interface DCacheStats; - interface Get#(Stat) num_accesses; - interface Get#(Stat) num_misses; - interface Get#(Stat) num_writebacks; -endinterface - -interface DCache#( type req_t, type resp_t ); - - // Interface from processor to cache - interface Server#(req_t,resp_t) proc_server; - - // Interface from cache to main memory - interface Client#(MainMemReq,MainMemResp) mmem_client; - - // Interface for enabling/disabling statistics - interface Put#(Bool) statsEn_put; - - // Interface for collecting statistics - interface DCacheStats stats; - -endinterface - - -//---------------------------------------------------------------------- -// Cache Types -//---------------------------------------------------------------------- - -typedef 10 CacheLineIndexSz; -typedef 20 CacheLineTagSz; -typedef 32 CacheLineSz; - -typedef Bit#(CacheLineIndexSz) CacheLineIndex; -typedef Bit#(CacheLineTagSz) CacheLineTag; -typedef Bit#(CacheLineSz) CacheLine; - -typedef enum -{ - Init, - Access, - RefillReq, - RefillResp -} -CacheStage -deriving (Eq,Bits); - -//---------------------------------------------------------------------- -// Helper functions -//---------------------------------------------------------------------- - -function Bit#(AddrSz) getAddr( DataReq req ); - - Bit#(AddrSz) addr = ?; - case ( req ) matches - tagged LoadReq .ld : addr = ld.addr; - tagged StoreReq .st : addr = st.addr; - endcase - - return addr; - -endfunction - -function CacheLineIndex getCacheLineIndex( DataReq req ); - Bit#(AddrSz) addr = getAddr(req); - Bit#(CacheLineIndexSz) index = truncate( addr >> 2 ); - return index; -endfunction - -function CacheLineTag getCacheLineTag( DataReq req ); - Bit#(AddrSz) addr = getAddr(req); - Bit#(CacheLineTagSz) tag = truncate( addr >> fromInteger(valueOf(CacheLineIndexSz)) >> 2 ); - return tag; -endfunction - -function Bit#(AddrSz) getCacheLineAddr( DataReq req ); - Bit#(AddrSz) addr = getAddr(req); - return ((addr >> 2) << 2); -endfunction - -//---------------------------------------------------------------------- -// Main module -//---------------------------------------------------------------------- - -(* doc = "synthesis attribute ram_style mkDataCache distributed;" *) -(* synthesize *) -module mkDataCache( DCache#(DataReq,DataResp) ); - - //----------------------------------------------------------- - // State - - Reg#(CacheStage) stage <- mkReg(Init); - - RegFile#(CacheLineIndex,Maybe#(CacheLineTag)) cacheTagRam <- mkRegFileFull(); - RegFile#(CacheLineIndex,CacheLine) cacheDataRam <- mkRegFileFull(); - - FIFO#(DataReq) reqQ <- mkFIFO(); - FIFOF#(DataResp) respQ <- mkBFIFOF1(); - - FIFO#(MainMemReq) mainMemReqQ <- mkBFIFO1(); - FIFO#(MainMemResp) mainMemRespQ <- mkFIFO(); - - Reg#(CacheLineIndex) initCounter <- mkReg(1); - - // Statistics state - - Reg#(Bool) statsEn <- mkReg(False); - - Reg#(Stat) num_accesses <- mkReg(0); - Reg#(Stat) num_misses <- mkReg(0); - Reg#(Stat) num_writebacks <- mkReg(0); - - //----------------------------------------------------------- - // Name some wires - - let req = reqQ.first(); - let reqIndex = getCacheLineIndex(req); - let reqTag = getCacheLineTag(req); - let reqCacheLineAddr = getCacheLineAddr(req); - - //----------------------------------------------------------- - // Initialize - - rule init ( stage == Init ); - traceTiny("mkDataCacheBlocking", "stage","i"); - initCounter <= initCounter + 1; - cacheTagRam.upd(initCounter,Invalid); - if ( initCounter == 0 ) - stage <= Access; - endrule - - //----------------------------------------------------------- - // Access cache rule - - rule access ( (stage == Access) && respQ.notFull() ); - - // Statistics - - if ( statsEn ) - num_accesses <= num_accesses + 1; - - - // Get the corresponding tag from the rams - - Maybe#(CacheLineTag) cacheLineTag = cacheTagRam.sub(reqIndex); - - // Handle cache hits ... - - if ( isValid(cacheLineTag) && ( unJust(cacheLineTag) == reqTag ) ) - begin - traceTiny("mkDataCacheBlocking", "hitMiss","h"); - reqQ.deq(); - - case ( req ) matches - - tagged LoadReq .ld : - respQ.enq( LoadResp { tag: ld.tag, data: cacheDataRam.sub(reqIndex) } ); - - tagged StoreReq .st : - begin - respQ.enq( StoreResp { tag : st.tag } ); - cacheDataRam.upd(reqIndex,st.data); - end - - endcase - - end - - // Handle cache misses ... - - else - begin - traceTiny("mkDataCacheBlocking", "hitMiss","m"); - if ( statsEn ) - num_misses <= num_misses + 1; - - // Currently we don't use dirty bits so we always writeback the data if it is valid - - if ( isValid(cacheLineTag) ) - begin - - if ( statsEn ) - num_writebacks <= num_writebacks + 1; - - MainMemReq wbReq - = StoreReq { tag : 0, - addr : { unJust(cacheLineTag), reqIndex, 2'b0 }, - data : cacheDataRam.sub(reqIndex) }; - - mainMemReqQ.enq(wbReq); - stage <= RefillReq; - end - - // Otherwise we can issue the refill request now - - else - begin - mainMemReqQ.enq( LoadReq { tag: 0, addr: reqCacheLineAddr } ); - stage <= RefillResp; - end - - end - - endrule - - //----------------------------------------------------------- - // Refill request rule - - rule refillReq ( stage == RefillReq ); - traceTiny("mkDataCacheBlocking", "stage","r"); - mainMemReqQ.enq( LoadReq { tag: 0, addr: reqCacheLineAddr } ); - stage <= RefillResp; - endrule - - //----------------------------------------------------------- - // Refill response rule - - rule refillResp ( stage == RefillResp ); - traceTiny("mkDataCacheBlocking", "stage","R"); - traceTiny("mkDataCacheBlocking", "refill",mainMemRespQ.first()); - - // Write the new data into the cache and update the tag - - mainMemRespQ.deq(); - case ( mainMemRespQ.first() ) matches - - tagged LoadResp .ld : - begin - cacheTagRam.upd(reqIndex,Valid(reqTag)); - cacheDataRam.upd(reqIndex,ld.data); - end - - tagged StoreResp .st : - noAction; - - endcase - - stage <= Access; - endrule - - //----------------------------------------------------------- - // Methods - - interface Client mmem_client; - interface Get request = toGet(mainMemReqQ); - interface Put response = toPut(mainMemRespQ); - endinterface - - interface Server proc_server; - interface Put request = tracePut("mkDataCacheBlocking", "reqTiny",toPut(reqQ)); - interface Get response = traceGet("mkDataCacheBlocking", "respTiny",toGet(respQ)); - endinterface - - interface Put statsEn_put = toPut(asReg(statsEn)); - - interface DCacheStats stats; - interface Get num_accesses = toGet(asReg(num_accesses)); - interface Get num_misses = toGet(asReg(num_misses)); - interface Get num_writebacks = toGet(asReg(num_writebacks)); - endinterface - -endmodule - diff -r f5dfbe28fa59 -r e5448315b892 modules/bluespec/Pygar/core/FIRFilterPipeline.bsv --- a/modules/bluespec/Pygar/core/FIRFilterPipeline.bsv Fri Apr 30 09:03:10 2010 -0400 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,46 +0,0 @@ -// The MIT License - -// Copyright (c) 2009 Massachusetts Institute of Technology - -// Permission is hereby granted, free of charge, to any person obtaining a copy -// of this software and associated documentation files (the "Software"), to deal -// in the Software without restriction, including without limitation the rights -// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -// copies of the Software, and to permit persons to whom the Software is -// furnished to do so, subject to the following conditions: - -// The above copyright notice and this permission notice shall be included in -// all copies or substantial portions of the Software. - -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -// THE SOFTWARE. - -// Author: Kermin Fleming kfleming@mit.edu - -import Connectable::*; -import GetPut::*; -import ClientServer::*; -import FIFO::*; - -//AWB includes -`include "asim/provides/low_level_platform_interface.bsh" -`include "asim/provides/soft_connections.bsh" -`include "asim/provides/common_services.bsh" - -//Local includes -`include "asim/provides/audio_processor_types.bsh" -`include "asim/provides/audio_pipeline_types.bsh" -`include "asim/provides/fir_filter.bsh" - -module [Connected_Module] mkAudioPipeline (AudioPipeline); - FIRFilter filter <- mkFIRFilter; - - interface sampleInput = filter.sampleInput; - interface sampleOutput = filter.sampleOutput; - -endmodule diff -r f5dfbe28fa59 -r e5448315b892 modules/bluespec/Pygar/core/InstCacheBlocking.d --- a/modules/bluespec/Pygar/core/InstCacheBlocking.d Fri Apr 30 09:03:10 2010 -0400 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,269 +0,0 @@ -// The MIT License - -// Copyright (c) 2009 Massachusetts Institute of Technology - -// Permission is hereby granted, free of charge, to any person obtaining a copy -// of this software and associated documentation files (the "Software"), to deal -// in the Software without restriction, including without limitation the rights -// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -// copies of the Software, and to permit persons to whom the Software is -// furnished to do so, subject to the following conditions: - -// The above copyright notice and this permission notice shall be included in -// all copies or substantial portions of the Software. - -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -// THE SOFTWARE. - -import Connectable::*; -import GetPut::*; -import ClientServer::*; -import RegFile::*; -import FIFO::*; -import FIFOF::*; -import RWire::*; - -import BFIFO::*; -import MemTypes::*; -import ProcTypes::*; -import Trace::*; - -interface ICacheStats; - interface Get#(Stat) num_accesses; - interface Get#(Stat) num_misses; - interface Get#(Stat) num_evictions; -endinterface - -interface ICache#( type req_t, type resp_t ); - - // Interface from processor to cache - interface Server#(req_t,resp_t) proc_server; - - // Interface from cache to main memory - interface Client#(MainMemReq,MainMemResp) mmem_client; - - // Interface for enabling/disabling statistics - interface Put#(Bool) statsEn_put; - - // Interface for collecting statistics - interface ICacheStats stats; - -endinterface - -//---------------------------------------------------------------------- -// Cache Types -//---------------------------------------------------------------------- - -typedef 10 CacheLineIndexSz; -typedef 20 CacheLineTagSz; -typedef 32 CacheLineSz; - -typedef Bit#(CacheLineIndexSz) CacheLineIndex; -typedef Bit#(CacheLineTagSz) CacheLineTag; -typedef Bit#(CacheLineSz) CacheLine; - -typedef enum -{ - Init, - Access, - Evict, - RefillReq, - RefillResp -} -CacheStage -deriving (Eq,Bits); - -//---------------------------------------------------------------------- -// Helper functions -//---------------------------------------------------------------------- - -function Bit#(AddrSz) getAddr( InstReq req ); - - Bit#(AddrSz) addr = ?; - case ( req ) matches - tagged LoadReq .ld : addr = ld.addr; - tagged StoreReq .st : addr = st.addr; - endcase - - return addr; - -endfunction - -function CacheLineIndex getCacheLineIndex( InstReq req ); - Bit#(AddrSz) addr = getAddr(req); - Bit#(CacheLineIndexSz) index = truncate( addr >> 2 ); - return index; -endfunction - -function CacheLineTag getCacheLineTag( InstReq req ); - Bit#(AddrSz) addr = getAddr(req); - Bit#(CacheLineTagSz) tag = truncate( addr >> fromInteger(valueOf(CacheLineIndexSz)) >> 2 ); - return tag; -endfunction - -function Bit#(AddrSz) getCacheLineAddr( InstReq req ); - Bit#(AddrSz) addr = getAddr(req); - return ((addr >> 2) << 2); -endfunction - -//---------------------------------------------------------------------- -// Main module -//---------------------------------------------------------------------- - -(* doc = "synthesis attribute ram_style mkInstCache distributed;" *) -(* synthesize *) -module mkInstCache( ICache#(InstReq,InstResp) ); - - //----------------------------------------------------------- - // State - - Reg#(CacheStage) stage <- mkReg(Init); - - RegFile#(CacheLineIndex,Maybe#(CacheLineTag)) cacheTagRam <- mkRegFileFull(); - RegFile#(CacheLineIndex,CacheLine) cacheDataRam <- mkRegFileFull(); - - FIFO#(InstReq) reqQ <- mkFIFO(); - FIFOF#(InstResp) respQ <- mkBFIFOF1(); - - FIFO#(MainMemReq) mainMemReqQ <- mkBFIFO1(); - FIFO#(MainMemResp) mainMemRespQ <- mkFIFO(); - - Reg#(CacheLineIndex) initCounter <- mkReg(1); - - // Statistics state - - Reg#(Bool) statsEn <- mkReg(False); - - Reg#(Stat) numAccesses <- mkReg(0); - Reg#(Stat) numMisses <- mkReg(0); - Reg#(Stat) numEvictions <- mkReg(0); - - //----------------------------------------------------------- - // Name some wires - - let req = reqQ.first(); - let reqIndex = getCacheLineIndex(req); - let reqTag = getCacheLineTag(req); - let reqCacheLineAddr = getCacheLineAddr(req); - let refill = mainMemRespQ.first(); - - //----------------------------------------------------------- - // Initialize - - rule init ( stage == Init ); - traceTiny("mkInstCacheBlocking", "stage","i"); - initCounter <= initCounter + 1; - cacheTagRam.upd(initCounter,Invalid); - if ( initCounter == 0 ) - stage <= Access; - endrule - - //----------------------------------------------------------- - // Cache access rule - - rule access ( (stage == Access) && respQ.notFull() ); - - // Statistics - - if ( statsEn ) - numAccesses <= numAccesses + 1; - - // Check tag and valid bit to see if this is a hit or a miss - - Maybe#(CacheLineTag) cacheLineTag = cacheTagRam.sub(reqIndex); - - // Handle cache hits ... - - if ( isValid(cacheLineTag) && ( unJust(cacheLineTag) == reqTag ) ) - begin - traceTiny("mkInstCacheBlocking", "hitMiss","h"); - reqQ.deq(); - - case ( req ) matches - - tagged LoadReq .ld : - respQ.enq( LoadResp { tag : ld.tag, data : cacheDataRam.sub(reqIndex) } ); - - tagged StoreReq .st : - $display( " RTL-ERROR : %m : Stores are not allowed on the inst port!" ); - - endcase - - end - - // Handle cache misses - since lines in instruction cache are - // never dirty we can always immediately issue a refill request - - else - begin - traceTiny("mkInstCacheBlocking", "hitMiss","m"); - if ( statsEn ) - numMisses <= numMisses + 1; - if ( statsEn ) - if ( isJust(cacheLineTag) ) - numEvictions <= numEvictions + 1; - - MainMemReq rfReq - = LoadReq { tag : 0, - addr : reqCacheLineAddr }; - - mainMemReqQ.enq(rfReq); - stage <= RefillResp; - end - - endrule - - //----------------------------------------------------------- - // Refill response rule - - rule refillResp ( stage == RefillResp ); - traceTiny("mkInstCacheBlocking", "stage","R"); - traceTiny("mkInstCacheBlocking", "refill",refill); - - // Write the new data into the cache and update the tag - - mainMemRespQ.deq(); - case ( mainMemRespQ.first() ) matches - - tagged LoadResp .ld : - begin - cacheTagRam.upd(reqIndex,Valid(reqTag)); - cacheDataRam.upd(reqIndex,ld.data); - end - - tagged StoreResp .st : - noAction; - - endcase - - stage <= Access; - endrule - - //----------------------------------------------------------- - // Methods - - interface Client mmem_client; - interface Get request = fifoToGet(mainMemReqQ); - interface Put response = fifoToPut(mainMemRespQ); - endinterface - - interface Server proc_server; - interface Put request = tracePut("mkInstCacheBlocking", "reqTiny",toPut(reqQ)); - interface Get response = traceGet("mkInstCacheBlocking", "respTiny",toGet(respQ)); - endinterface - - interface Put statsEn_put = toPut(asReg(statsEn)); - - interface ICacheStats stats; - interface Get num_accesses = toGet(asReg(numAccesses)); - interface Get num_misses = toGet(asReg(numMisses)); - interface Get num_evictions = toGet(asReg(numEvictions)); - endinterface - -endmodule - diff -r f5dfbe28fa59 -r e5448315b892 modules/bluespec/Pygar/core/MemArb.bsv --- a/modules/bluespec/Pygar/core/MemArb.bsv Fri Apr 30 09:03:10 2010 -0400 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,141 +0,0 @@ -// The MIT License - -// Copyright (c) 2009 Massachusetts Institute of Technology - -// Permission is hereby granted, free of charge, to any person obtaining a copy -// of this software and associated documentation files (the "Software"), to deal -// in the Software without restriction, including without limitation the rights -// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -// copies of the Software, and to permit persons to whom the Software is -// furnished to do so, subject to the following conditions: - -// The above copyright notice and this permission notice shall be included in -// all copies or substantial portions of the Software. - -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -// THE SOFTWARE. - -import Connectable::*; -import GetPut::*; -import ClientServer::*; -import FIFOF::*; -import FIFO::*; - -import BFIFO::*; -import MemTypes::*; -import Trace::*; - -interface MemArb; - - interface Server#(MainMemReq,MainMemResp) cache0_server; - interface Server#(MainMemReq,MainMemResp) cache1_server; - interface Client#(MainMemReq,MainMemResp) mmem_client; - -endinterface - -typedef enum { REQ0, REQ1 } ReqPtr deriving(Eq,Bits); - -(* synthesize *) -module mkMemArb( MemArb ); - - //----------------------------------------------------------- - // State - - FIFOF#(MainMemReq) req0Q <- mkFIFOF1(); - FIFO#(MainMemResp) resp0Q <- mkFIFO1(); - - FIFOF#(MainMemReq) req1Q <- mkFIFOF1(); - FIFO#(MainMemResp) resp1Q <- mkFIFO1(); - - FIFO#(MainMemReq) mreqQ <- mkFIFO1(); - FIFO#(MainMemResp) mrespQ <- mkFIFO1(); - - Reg#(ReqPtr) nextReq <- mkReg(REQ0); - - //----------------------------------------------------------- - // Some wires - - let req0avail = req0Q.notEmpty(); - let req1avail = req1Q.notEmpty(); - - //----------------------------------------------------------- - // Rules - - rule chooseReq0 ( req0avail && (!req1avail || (nextReq == REQ0)) ); - traceTiny("mkMemArb", "memArb req0",req0Q.first()); - - // Rewrite tag field if this is a load ... - MainMemReq mreq - = case ( req0Q.first() ) matches - tagged LoadReq .ld : return LoadReq { tag:0, addr:ld.addr }; - tagged StoreReq .st : return req0Q.first(); - endcase; - - // Send out the request - mreqQ.enq(mreq); - nextReq <= REQ1; - req0Q.deq(); - - endrule - - rule chooseReq1 ( req1avail && (!req0avail || (nextReq == REQ1)) ); - traceTiny("mkMemArb", "memArb req1",req1Q.first); - - // Rewrite tag field if this is a load ... - MainMemReq mreq - = case ( req1Q.first() ) matches - tagged LoadReq .ld : return LoadReq { tag:1, addr:ld.addr }; - tagged StoreReq .st : return req1Q.first(); - endcase; - - // Send out the request - mreqQ.enq(mreq); - nextReq <= REQ0; - req1Q.deq(); - - endrule - - rule returnResp; - traceTiny("mkMemArb", "resp",mrespQ.first()); - - // Use tag to figure out where to send response - mrespQ.deq(); - let tag - = case ( mrespQ.first() ) matches - tagged LoadResp .ld : return ld.tag; - tagged StoreResp .st : return st.tag; - endcase; - - if ( tag == 0 ) - resp0Q.enq(mrespQ.first()); - else - resp1Q.enq(mrespQ.first()); - - endrule - - //----------------------------------------------------------- - // Methods - - interface Server cache0_server; - interface Put request = toPut(req0Q); - interface Get response = toGet(resp0Q); - endinterface - - interface Server cache1_server; - interface Put request = toPut(req1Q); - interface Get response = toGet(resp1Q); - endinterface - - interface Client mmem_client; - interface Get request = toGet(mreqQ); - interface Put response = toPut(mrespQ); - endinterface - -endmodule - - diff -r f5dfbe28fa59 -r e5448315b892 modules/bluespec/Pygar/core/MemTypes.bsv --- a/modules/bluespec/Pygar/core/MemTypes.bsv Fri Apr 30 09:03:10 2010 -0400 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,93 +0,0 @@ - -import Trace::*; - -//---------------------------------------------------------------------- -// Basic memory requests and responses -//---------------------------------------------------------------------- - -typedef union tagged -{ - struct { Bit#(addrSz) addr; Bit#(tagSz) tag; } LoadReq; - struct { Bit#(addrSz) addr; Bit#(tagSz) tag; Bit#(dataSz) data; } StoreReq; -} -MemReq#( type addrSz, type tagSz, type dataSz ) -deriving(Eq,Bits); - -typedef union tagged -{ - struct { Bit#(tagSz) tag; Bit#(dataSz) data; } LoadResp; - struct { Bit#(tagSz) tag; } StoreResp; -} -MemResp#( type tagSz, type dataSz ) -deriving(Eq,Bits); - -//---------------------------------------------------------------------- -// Specialized req/resp for inst/data/host -//---------------------------------------------------------------------- - -typedef 32 AddrSz; -typedef 08 TagSz; -typedef 32 DataSz; -typedef 32 InstSz; -typedef 32 HostDataSz; - -typedef MemReq#(AddrSz,TagSz,0) InstReq; -typedef MemResp#(TagSz,InstSz) InstResp; - -typedef MemReq#(AddrSz,TagSz,DataSz) DataReq; -typedef MemResp#(TagSz,DataSz) DataResp; - -typedef MemReq#(AddrSz,TagSz,HostDataSz) HostReq; -typedef MemResp#(TagSz,HostDataSz) HostResp; - -//---------------------------------------------------------------------- -// Specialized req/resp for main memory -//---------------------------------------------------------------------- - -typedef 32 MainMemAddrSz; -typedef 08 MainMemTagSz; -typedef 32 MainMemDataSz; - -typedef MemReq#(MainMemAddrSz,MainMemTagSz,MainMemDataSz) MainMemReq; -typedef MemResp#(MainMemTagSz,MainMemDataSz) MainMemResp; - -//---------------------------------------------------------------------- -// Tracing Functions -//---------------------------------------------------------------------- - -instance Traceable#(MemReq#(a,b,c)); - - function Action traceTiny( String loc, String ttag, MemReq#(a,b,c) req ); - case ( req ) matches - tagged LoadReq .ld : $fdisplay(stderr, " => %s:%s l%2x", loc, ttag, ld.tag ); - tagged StoreReq .st : $fdisplay(stderr, " => %s:%s s%2x", loc, ttag, st.tag ); - endcase - endfunction - - function Action traceFull( String loc, String ttag, MemReq#(a,b,c) req ); - case ( req ) matches - tagged LoadReq .ld : $fdisplay(stderr, " => %s:%s Ld { addr=%x, tag=%x }", loc, ttag, ld.addr, ld.tag ); - tagged StoreReq .st : $fdisplay(stderr, " => %s:%s St { addr=%x, tag=%x, data=%x }", loc, ttag, st.addr, st.tag, st.data ); - endcase - endfunction - -endinstance - -instance Traceable#(MemResp#(a,b)); - - function Action traceTiny( String loc, String ttag, MemResp#(a,b) resp ); - case ( resp ) matches - tagged LoadResp .ld : $fdisplay(stderr, " => %s:%s l%2x", loc, ttag, ld.tag ); - tagged StoreResp .st : $fdisplay(stderr, " => %s:%s s%2x", loc, ttag, st.tag ); - endcase - endfunction - - function Action traceFull( String loc, String ttag, MemResp#(a,b) resp ); - case ( resp ) matches - tagged LoadResp .ld : $fdisplay(stderr, " => %s:%s Ld { tag=%x, data=%x }", loc, ttag, ld.tag, ld.data ); - tagged StoreResp .st : $fdisplay(stderr, " => %s:%s St { tag=%x }", loc, ttag, st.tag ); - endcase - endfunction - -endinstance - diff -r f5dfbe28fa59 -r e5448315b892 modules/bluespec/Pygar/core/ProcTrace.bsv~ --- a/modules/bluespec/Pygar/core/ProcTrace.bsv~ Fri Apr 30 09:03:10 2010 -0400 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,375 +0,0 @@ -import Trace::*; - - -//---------------------------------------------------------------------- -// Other typedefs -//---------------------------------------------------------------------- - -typedef Bit#(32) Addr; -typedef Int#(18) Stat; - -//---------------------------------------------------------------------- -// Basic instruction type -//---------------------------------------------------------------------- - -typedef Bit#(5) Rindx; -typedef Bit#(16) Simm; -typedef Bit#(16) Zimm; -typedef Bit#(8) Epoch; -typedef Bit#(5) Shamt; -typedef Bit#(26) Target; -typedef Bit#(5) CP0indx; -typedef Bit#(32) Data; - -typedef enum -{ - Taken, - NotTaken -} - Direction - deriving(Bits,Eq); - - -//---------------------------------------------------------------------- -// Pipeline typedefs -//---------------------------------------------------------------------- - -typedef union tagged -{ - Tuple2#(Rindx,Data) ALUWB; - Rindx MemWB; - Tuple2#(Rindx,Data) CoWB; -} - WritebackType - deriving(Bits,Eq); - -//////////////////////// -// I Add Writeback queue type -//////////// -typedef union tagged -{ - struct {Bit#(32) data; Rindx dest; } WB_ALU; - Bit#(32) WB_Host; - Rindx WB_Load; - void WB_Store; -} -WBResult deriving(Eq, Bits); - -typedef struct{Addr qpc; Addr qnxtpc; Epoch qepoch;} PCStat deriving(Eq, Bits); -//typedef struct{Addr qpc; Epoch qepoch;} PCStat deriving(Eq, Bits); - -typedef union tagged -{ - - struct { Rindx rbase; Rindx rdst; Simm offset; } LW; - struct { Rindx rbase; Rindx rsrc; Simm offset; } SW; - - struct { Rindx rsrc; Rindx rdst; Simm imm; } ADDIU; - struct { Rindx rsrc; Rindx rdst; Simm imm; } SLTI; - struct { Rindx rsrc; Rindx rdst; Simm imm; } SLTIU; - struct { Rindx rsrc; Rindx rdst; Zimm imm; } ANDI; - struct { Rindx rsrc; Rindx rdst; Zimm imm; } ORI; - struct { Rindx rsrc; Rindx rdst; Zimm imm; } XORI; - struct { Rindx rdst; Zimm imm; } LUI; - - struct { Rindx rsrc; Rindx rdst; Shamt shamt; } SLL; - struct { Rindx rsrc; Rindx rdst; Shamt shamt; } SRL; - struct { Rindx rsrc; Rindx rdst; Shamt shamt; } SRA; - struct { Rindx rsrc; Rindx rdst; Rindx rshamt; } SLLV; - struct { Rindx rsrc; Rindx rdst; Rindx rshamt; } SRLV; - struct { Rindx rsrc; Rindx rdst; Rindx rshamt; } SRAV; - struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } ADDU; - struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } SUBU; - struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } AND; - struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } OR; - struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } XOR; - struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } NOR; - struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } SLT; - struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } SLTU; - - struct { Target target; } J; - struct { Target target; } JAL; - struct { Rindx rsrc; } JR; - struct { Rindx rsrc; Rindx rdst; } JALR; - struct { Rindx rsrc1; Rindx rsrc2; Simm offset; } BEQ; - struct { Rindx rsrc1; Rindx rsrc2; Simm offset; } BNE; - struct { Rindx rsrc; Simm offset; } BLEZ; - struct { Rindx rsrc; Simm offset; } BGTZ; - struct { Rindx rsrc; Simm offset; } BLTZ; - struct { Rindx rsrc; Simm offset; } BGEZ; - - struct { Rindx rdst; CP0indx cop0src; } MFC0; - struct { Rindx rsrc; CP0indx cop0dst; } MTC0; - - void ILLEGAL; - -} -Instr deriving(Eq); - -//---------------------------------------------------------------------- -// Pack and Unpack -//---------------------------------------------------------------------- - -Bit#(6) opFUNC = 6'b000000; Bit#(6) fcSLL = 6'b000000; -Bit#(6) opRT = 6'b000001; Bit#(6) fcSRL = 6'b000010; -Bit#(6) opRS = 6'b010000; Bit#(6) fcSRA = 6'b000011; - Bit#(6) fcSLLV = 6'b000100; -Bit#(6) opLW = 6'b100011; Bit#(6) fcSRLV = 6'b000110; -Bit#(6) opSW = 6'b101011; Bit#(6) fcSRAV = 6'b000111; - Bit#(6) fcADDU = 6'b100001; -Bit#(6) opADDIU = 6'b001001; Bit#(6) fcSUBU = 6'b100011; -Bit#(6) opSLTI = 6'b001010; Bit#(6) fcAND = 6'b100100; -Bit#(6) opSLTIU = 6'b001011; Bit#(6) fcOR = 6'b100101; -Bit#(6) opANDI = 6'b001100; Bit#(6) fcXOR = 6'b100110; -Bit#(6) opORI = 6'b001101; Bit#(6) fcNOR = 6'b100111; -Bit#(6) opXORI = 6'b001110; Bit#(6) fcSLT = 6'b101010; -Bit#(6) opLUI = 6'b001111; Bit#(6) fcSLTU = 6'b101011; - -Bit#(6) opJ = 6'b000010; -Bit#(6) opJAL = 6'b000011; -Bit#(6) fcJR = 6'b001000; -Bit#(6) fcJALR = 6'b001001; -Bit#(6) opBEQ = 6'b000100; -Bit#(6) opBNE = 6'b000101; -Bit#(6) opBLEZ = 6'b000110; -Bit#(6) opBGTZ = 6'b000111; -Bit#(5) rtBLTZ = 5'b00000; -Bit#(5) rtBGEZ = 5'b00001; - -Bit#(5) rsMFC0 = 5'b00000; -Bit#(5) rsMTC0 = 5'b00100; - -instance Bits#(Instr,32); - - // Pack Function - - function Bit#(32) pack( Instr instr ); - - case ( instr ) matches - - tagged LW .it : return { opLW, it.rbase, it.rdst, it.offset }; - tagged SW .it : return { opSW, it.rbase, it.rsrc, it.offset }; - - tagged ADDIU .it : return { opADDIU, it.rsrc, it.rdst, it.imm }; - tagged SLTI .it : return { opSLTI, it.rsrc, it.rdst, it.imm }; - tagged SLTIU .it : return { opSLTIU, it.rsrc, it.rdst, it.imm }; - tagged ANDI .it : return { opANDI, it.rsrc, it.rdst, it.imm }; - tagged ORI .it : return { opORI, it.rsrc, it.rdst, it.imm }; - tagged XORI .it : return { opXORI, it.rsrc, it.rdst, it.imm }; - tagged LUI .it : return { opLUI, 5'b0, it.rdst, it.imm }; - - tagged SLL .it : return { opFUNC, 5'b0, it.rsrc, it.rdst, it.shamt, fcSLL }; - tagged SRL .it : return { opFUNC, 5'b0, it.rsrc, it.rdst, it.shamt, fcSRL }; - tagged SRA .it : return { opFUNC, 5'b0, it.rsrc, it.rdst, it.shamt, fcSRA }; - - tagged SLLV .it : return { opFUNC, it.rshamt, it.rsrc, it.rdst, 5'b0, fcSLLV }; - tagged SRLV .it : return { opFUNC, it.rshamt, it.rsrc, it.rdst, 5'b0, fcSRLV }; - tagged SRAV .it : return { opFUNC, it.rshamt, it.rsrc, it.rdst, 5'b0, fcSRAV }; - - tagged ADDU .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcADDU }; - tagged SUBU .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcSUBU }; - tagged AND .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcAND }; - tagged OR .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcOR }; - tagged XOR .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcXOR }; - tagged NOR .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcNOR }; - tagged SLT .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcSLT }; - tagged SLTU .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcSLTU }; - - tagged J .it : return { opJ, it.target }; - tagged JAL .it : return { opJAL, it.target }; - tagged JR .it : return { opFUNC, it.rsrc, 5'b0, 5'b0, 5'b0, fcJR }; - tagged JALR .it : return { opFUNC, it.rsrc, 5'b0, it.rdst, 5'b0, fcJALR }; - tagged BEQ .it : return { opBEQ, it.rsrc1, it.rsrc2, it.offset }; - tagged BNE .it : return { opBNE, it.rsrc1, it.rsrc2, it.offset }; - tagged BLEZ .it : return { opBLEZ, it.rsrc, 5'b0, it.offset }; - tagged BGTZ .it : return { opBGTZ, it.rsrc, 5'b0, it.offset }; - tagged BLTZ .it : return { opRT, it.rsrc, rtBLTZ, it.offset }; - tagged BGEZ .it : return { opRT, it.rsrc, rtBGEZ, it.offset }; - - tagged MFC0 .it : return { opRS, rsMFC0, it.rdst, it.cop0src, 11'b0 }; - tagged MTC0 .it : return { opRS, rsMTC0, it.rsrc, it.cop0dst, 11'b0 }; - - endcase - - endfunction - - // Unpack Function - - function Instr unpack( Bit#(32) instrBits ); - - let opcode = instrBits[ 31 : 26 ]; - let rs = instrBits[ 25 : 21 ]; - let rt = instrBits[ 20 : 16 ]; - let rd = instrBits[ 15 : 11 ]; - let shamt = instrBits[ 10 : 6 ]; - let funct = instrBits[ 5 : 0 ]; - let imm = instrBits[ 15 : 0 ]; - let target = instrBits[ 25 : 0 ]; - - case ( opcode ) - - opLW : return LW { rbase:rs, rdst:rt, offset:imm }; - opSW : return SW { rbase:rs, rsrc:rt, offset:imm }; - opADDIU : return ADDIU { rsrc:rs, rdst:rt, imm:imm }; - opSLTI : return SLTI { rsrc:rs, rdst:rt, imm:imm }; - opSLTIU : return SLTIU { rsrc:rs, rdst:rt, imm:imm }; - opANDI : return ANDI { rsrc:rs, rdst:rt, imm:imm }; - opORI : return ORI { rsrc:rs, rdst:rt, imm:imm }; - opXORI : return XORI { rsrc:rs, rdst:rt, imm:imm }; - opLUI : return LUI { rdst:rt, imm:imm }; - opJ : return J { target:target }; - opJAL : return JAL { target:target }; - opBEQ : return BEQ { rsrc1:rs, rsrc2:rt, offset:imm }; - opBNE : return BNE { rsrc1:rs, rsrc2:rt, offset:imm }; - opBLEZ : return BLEZ { rsrc:rs, offset:imm }; - opBGTZ : return BGTZ { rsrc:rs, offset:imm }; - - opFUNC : - case ( funct ) - fcSLL : return SLL { rsrc:rt, rdst:rd, shamt:shamt }; - fcSRL : return SRL { rsrc:rt, rdst:rd, shamt:shamt }; - fcSRA : return SRA { rsrc:rt, rdst:rd, shamt:shamt }; - fcSLLV : return SLLV { rsrc:rt, rdst:rd, rshamt:rs }; - fcSRLV : return SRLV { rsrc:rt, rdst:rd, rshamt:rs }; - fcSRAV : return SRAV { rsrc:rt, rdst:rd, rshamt:rs }; - fcADDU : return ADDU { rsrc1:rs, rsrc2:rt, rdst:rd }; - fcSUBU : return SUBU { rsrc1:rs, rsrc2:rt, rdst:rd }; - fcAND : return AND { rsrc1:rs, rsrc2:rt, rdst:rd }; - fcOR : return OR { rsrc1:rs, rsrc2:rt, rdst:rd }; - fcXOR : return XOR { rsrc1:rs, rsrc2:rt, rdst:rd }; - fcNOR : return NOR { rsrc1:rs, rsrc2:rt, rdst:rd }; - fcSLT : return SLT { rsrc1:rs, rsrc2:rt, rdst:rd }; - fcSLTU : return SLTU { rsrc1:rs, rsrc2:rt, rdst:rd }; - fcJR : return JR { rsrc:rs }; - fcJALR : return JALR { rsrc:rs, rdst:rd }; - default : return ILLEGAL; - endcase - - opRT : - case ( rt ) - rtBLTZ : return BLTZ { rsrc:rs, offset:imm }; - rtBGEZ : return BGEZ { rsrc:rs, offset:imm }; - default : return ILLEGAL; - endcase - - opRS : - case ( rs ) - rsMFC0 : return MFC0 { rdst:rt, cop0src:rd }; - rsMTC0 : return MTC0 { rsrc:rt, cop0dst:rd }; - default : return ILLEGAL; - endcase - - default : return ILLEGAL; - - endcase - - endfunction - -endinstance - -//---------------------------------------------------------------------- -// Trace -//---------------------------------------------------------------------- - -instance Traceable#(Instr); - - function Action traceTiny( String loc, String ttag, Instr inst ); - case ( inst ) matches - - tagged LW .it : $fdisplay(stderr, " => %s:%s lw", loc, ttag ); - tagged SW .it : $fdisplay(stderr, " => %s:%s sw", loc, ttag ); - - tagged ADDIU .it : $fdisplay(stderr, " => %s:%s addi", loc, ttag ); - tagged SLTI .it : $fdisplay(stderr, " => %s:%s sli", loc, ttag ); - tagged SLTIU .it : $fdisplay(stderr, " => %s:%s sliu", loc, ttag ); - tagged ANDI .it : $fdisplay(stderr, " => %s:%s andi", loc, ttag ); - tagged ORI .it : $fdisplay(stderr, " => %s:%s ori", loc, ttag ); - tagged XORI .it : $fdisplay(stderr, " => %s:%s xori", loc, ttag ); - tagged LUI .it : $fdisplay(stderr, " => %s:%s lui", loc, ttag ); - - tagged SLL .it : $fdisplay(stderr, " => %s:%s sll", loc, ttag ); - tagged SRL .it : $fdisplay(stderr, " => %s:%s srl", loc, ttag ); - tagged SRA .it : $fdisplay(stderr, " => %s:%s sra", loc, ttag ); - tagged SLLV .it : $fdisplay(stderr, " => %s:%s sllv", loc, ttag ); - tagged SRLV .it : $fdisplay(stderr, " => %s:%s srlv", loc, ttag ); - tagged SRAV .it : $fdisplay(stderr, " => %s:%s srav", loc, ttag ); - - tagged ADDU .it : $fdisplay(stderr, " => %s:%s addu", loc, ttag ); - tagged SUBU .it : $fdisplay(stderr, " => %s:%s subu", loc, ttag ); - tagged AND .it : $fdisplay(stderr, " => %s:%s and", loc, ttag ); - tagged OR .it : $fdisplay(stderr, " => %s:%s or", loc, ttag ); - tagged XOR .it : $fdisplay(stderr, " => %s:%s xor", loc, ttag ); - tagged NOR .it : $fdisplay(stderr, " => %s:%s nor", loc, ttag ); - tagged SLT .it : $fdisplay(stderr, " => %s:%s slt", loc, ttag ); - tagged SLTU .it : $fdisplay(stderr, " => %s:%s sltu", loc, ttag ); - - tagged J .it : $fdisplay(stderr, " => %s:%s j", loc, ttag ); - tagged JAL .it : $fdisplay(stderr, " => %s:%s jal", loc, ttag ); - tagged JR .it : $fdisplay(stderr, " => %s:%s jr", loc, ttag ); - tagged JALR .it : $fdisplay(stderr, " => %s:%s jalr", loc, ttag ); - tagged BEQ .it : $fdisplay(stderr, " => %s:%s beq", loc, ttag ); - tagged BNE .it : $fdisplay(stderr, " => %s:%s bne", loc, ttag ); - tagged BLEZ .it : $fdisplay(stderr, " => %s:%s blez", loc, ttag ); - tagged BGTZ .it : $fdisplay(stderr, " => %s:%s bgtz", loc, ttag ); - tagged BLTZ .it : $fdisplay(stderr, " => %s:%s bltz", loc, ttag ); - tagged BGEZ .it : $fdisplay(stderr, " => %s:%s bgez", loc, ttag ); - - tagged MFC0 .it : $fdisplay(stderr, " => %s:%s mfc0", loc, ttag ); - tagged MTC0 .it : $fdisplay(stderr, " => %s:%s mtc0", loc, ttag ); - - tagged ILLEGAL : $fdisplay(stderr, " => %s:%s ill", loc, ttag ); - - endcase - endfunction - - function Action traceFull( String loc, String ttag, Instr inst ); - case ( inst ) matches - - tagged LW .it : $fdisplay(stderr, " => %s:%s lw r%0d, 0x%x(r%0d)", loc, ttag, it.rdst, it.offset, it.rbase ); - tagged SW .it : $fdisplay(stderr, " => %s:%s sw r%0d, 0x%x(r%0d)", loc, ttag, it.rsrc, it.offset, it.rbase ); - - tagged ADDIU .it : $fdisplay(stderr, " => %s:%s addiu r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); - tagged SLTI .it : $fdisplay(stderr, " => %s:%s slti r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); - tagged SLTIU .it : $fdisplay(stderr, " => %s:%s sltiu r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); - tagged ANDI .it : $fdisplay(stderr, " => %s:%s andi r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); - tagged ORI .it : $fdisplay(stderr, " => %s:%s ori r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); - tagged XORI .it : $fdisplay(stderr, " => %s:%s xori r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); - tagged LUI .it : $fdisplay(stderr, " => %s:%s lui r%0d, 0x%x", loc, ttag, it.rdst, it.imm ); - - tagged SLL .it : $fdisplay(stderr, " => %s:%s sll r%0d, r%0d, %0d", loc, ttag, it.rdst, it.rsrc, it.shamt ); - tagged SRL .it : $fdisplay(stderr, " => %s:%s srl r%0d, r%0d, %0d", loc, ttag, it.rdst, it.rsrc, it.shamt ); - tagged SRA .it : $fdisplay(stderr, " => %s:%s sra r%0d, r%0d, %0d", loc, ttag, it.rdst, it.rsrc, it.shamt ); - tagged SLLV .it : $fdisplay(stderr, " => %s:%s sllv r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc, it.rshamt ); - tagged SRLV .it : $fdisplay(stderr, " => %s:%s srlv r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc, it.rshamt ); - tagged SRAV .it : $fdisplay(stderr, " => %s:%s srav r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc, it.rshamt ); - - tagged ADDU .it : $fdisplay(stderr, " => %s:%s addu r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); - tagged SUBU .it : $fdisplay(stderr, " => %s:%s subu r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); - tagged AND .it : $fdisplay(stderr, " => %s:%s and r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); - tagged OR .it : $fdisplay(stderr, " => %s:%s or r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); - tagged XOR .it : $fdisplay(stderr, " => %s:%s xor r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); - tagged NOR .it : $fdisplay(stderr, " => %s:%s nor r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); - tagged SLT .it : $fdisplay(stderr, " => %s:%s slt r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); - tagged SLTU .it : $fdisplay(stderr, " => %s:%s sltu r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); - - tagged J .it : $fdisplay(stderr, " => %s:%s j 0x%x", loc, ttag, it.target ); - tagged JAL .it : $fdisplay(stderr, " => %s:%s jal 0x%x", loc, ttag, it.target ); - tagged JR .it : $fdisplay(stderr, " => %s:%s jr r%0d", loc, ttag, it.rsrc ); - tagged JALR .it : $fdisplay(stderr, " => %s:%s jalr r%0d", loc, ttag, it.rsrc ); - tagged BEQ .it : $fdisplay(stderr, " => %s:%s beq r%0d, r%0d, 0x%x", loc, ttag, it.rsrc1, it.rsrc2, it.offset ); - tagged BNE .it : $fdisplay(stderr, " => %s:%s bne r%0d, r%0d, 0x%x", loc, ttag, it.rsrc1, it.rsrc2, it.offset ); - tagged BLEZ .it : $fdisplay(stderr, " => %s:%s blez r%0d, 0x%x", loc, ttag, it.rsrc, it.offset ); - tagged BGTZ .it : $fdisplay(stderr, " => %s:%s bgtz r%0d, 0x%x", loc, ttag, it.rsrc, it.offset ); - tagged BLTZ .it : $fdisplay(stderr, " => %s:%s bltz r%0d, 0x%x", loc, ttag, it.rsrc, it.offset ); - tagged BGEZ .it : $fdisplay(stderr, " => %s:%s bgez r%0d, 0x%x", loc, ttag, it.rsrc, it.offset ); - - tagged MFC0 .it : $fdisplay(stderr, " => %s:%s mfc0 r%0d, cpr%0d", loc, ttag, it.rdst, it.cop0src ); - tagged MTC0 .it : $fdisplay(stderr, " => %s:%s mtc0 r%0d, cpr%0d", loc, ttag, it.rsrc, it.cop0dst ); - - tagged ILLEGAL : $fdisplay(stderr, " => %s:%s illegal instruction", loc, ttag ); - - endcase - endfunction - -endinstance - diff -r f5dfbe28fa59 -r e5448315b892 modules/bluespec/Pygar/core/SFIFO.bsv --- a/modules/bluespec/Pygar/core/SFIFO.bsv Fri Apr 30 09:03:10 2010 -0400 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,213 +0,0 @@ - -import FIFO::*; -import ConfigReg::*; -import RWire::*; - -import List::*; -import Monad::*; - -interface SFIFO#(type alpha_T, type search_T); - method Action enq(alpha_T x); - method Action deq(); - method alpha_T first(); - method Action clear(); - method Bool find(search_T x); - method Bool find2(search_T x); - -endinterface - -module mkSFIFO#(function Bool searchfunc(search_T s, alpha_T x)) (SFIFO#(alpha_T, search_T)) - provisos - (Bits#(alpha_T,asz)); - - Reg#(alpha_T) f0 <- mkConfigRegU(); - Reg#(alpha_T) f1 <- mkConfigRegU(); - - Reg#(Bool) vf0 <- mkConfigReg(False); - Reg#(Bool) vf1 <- mkConfigReg(False); - - PulseWire edge1 <- mkPulseWire(); - - method Action enq(alpha_T x) if (!(vf0 && vf1)); - if (edge1 || !vf0)//empty or we're dequeueing - begin - vf0 <= True; //True - vf1 <= False; - f0 <= x; - end - else // !vf1 - begin - vf1 <= True; - f1 <= x; - end - endmethod - - method Action deq() if (vf0); - edge1.send(); - vf0 <= vf1; - f0 <= f1; - vf1 <= False; - endmethod - - method alpha_T first() if(vf0); - return (f0); - endmethod - - method Action clear(); - vf0 <= False; - vf1 <= False; - endmethod - - method Bool find(search_T sv); - Bool nvf0 = edge1 ? False: vf0; - Bool nvf1 = vf1; - - return (nvf0 && searchfunc(sv, f0) || - nvf1 && searchfunc(sv, f1)); - endmethod - - method Bool find2(search_T sv); - Bool nvf0 = edge1 ? False: vf0; - Bool nvf1 = vf1; - - return (nvf0 && searchfunc(sv, f0) || - nvf1 && searchfunc(sv, f1)); - endmethod - -endmodule - -module mkSFIFO1#(function Bool searchfunc(search_T s, alpha_T x)) (SFIFO#(alpha_T, search_T)) - provisos - (Bits#(alpha_T,asz), Eq#(alpha_T)); - - Reg#(alpha_T) f0 <- mkConfigRegU; - - Reg#(Bool) vf0 <- mkConfigReg(False); - - PulseWire edge1 <- mkPulseWire(); - - method Action enq(alpha_T x) if (!vf0); - vf0 <= True; //True - f0 <= x; - endmethod - - method Action deq() if (vf0); - edge1.send(); - vf0 <= False; - endmethod - - method alpha_T first() if(vf0); - return (f0); - endmethod - - method Action clear(); - vf0 <= False; - endmethod - - method Bool find(search_T sv); - Bool nvf0 = edge1 ? False: vf0; - - return (nvf0 && searchfunc(sv, f0)); - endmethod - - method Bool find2(search_T sv); - Bool nvf0 = edge1 ? False: vf0; - return (nvf0 && searchfunc(sv, f0)); - endmethod - -endmodule - -module mkSizedSFIFOInternal#(Integer n, - function Bool searchfunc1(search_T s, alpha_T x), - function Bool searchfunc2(search_T s, alpha_T x)) (SFIFO#(alpha_T, search_T)) - - provisos ( Bits#(alpha_T,alpha_SZ) ); - - List#(Reg#(alpha_T)) registers <- replicateM(n, mkRegU); - List#(Reg#(Bool)) valids <- replicateM(n, mkReg(False)); - - function Nat getNextFree (List#(Reg#(Bool)) vs); - - Nat res = fromInteger(n - 1); - - for (Integer x = n - 1; x > -1; x = x - 1) - res = !vs[x]._read() ? fromInteger(x) : res; - - return res; - - endfunction - - function Bool notFull(); - - Bool full = True; - - for (Integer x = 0; x < n; x = x + 1) - full = full && valids[x]._read(); - - return !full; - - endfunction - - method Action enq( alpha_T item ) if ( notFull() ); - - Nat k = getNextFree(valids); - select(valids, k)._write(True); - select(registers, k)._write(item); - - endmethod - - method Action deq() if ( valids[0]._read() ); - - for (Integer x = 0; x < (n-1); x = x + 1) - begin - - (registers[x]) <= registers[x + 1]._read(); - (valids[x]) <= valids[x + 1]._read(); - - end - (valids[n-1]) <= False; - endmethod - - method alpha_T first() if ( valids[0]._read() ); - return registers[0]._read(); - endmethod - - method Bool find(search_T sv); - Bool res = False; - - for (Integer x = 0; x < n; x = x + 1) - if ( valids[x]._read() && searchfunc1(sv, registers[x]._read()) ) - res = True; - - return res; - - endmethod - - method Bool find2(search_T sv); - Bool res = False; - - for (Integer x = 0; x < n; x = x + 1) - if ( valids[x]._read() && searchfunc2(sv, registers[x]._read()) ) - res = True; - - return res; - - endmethod - - method Action clear(); - - for (Integer x = 0; x < n; x = x + 1) - (valids[x]) <= False; - - endmethod - -endmodule - -module mkSizedSFIFO#(Integer n, function Bool searchfunc(search_T s, alpha_T x)) (SFIFO#(alpha_T, search_T)) - provisos - (Bits#(alpha_T,asz)); - - let foo <- mkSizedSFIFOInternal(n, searchfunc, searchfunc); - return foo; - -endmodule diff -r f5dfbe28fa59 -r e5448315b892 modules/bluespec/Pygar/core/olaCore.bsv --- a/modules/bluespec/Pygar/core/olaCore.bsv Fri Apr 30 09:03:10 2010 -0400 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,90 +0,0 @@ -// The MIT License - -// Copyright (c) 2009 Massachusetts Institute of Technology - -// Permission is hereby granted, free of charge, to any person obtaining a copy -// of this software and associated documentation files (the "Software"), to deal -// in the Software without restriction, including without limitation the rights -// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -// copies of the Software, and to permit persons to whom the Software is -// furnished to do so, subject to the following conditions: - -// The above copyright notice and this permission notice shall be included in -// all copies or substantial portions of the Software. - -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -// THE SOFTWARE. - -import Connectable::*; -import GetPut::*; -import ClientServer::*; - -import DataCacheBlocking::*; -import InstCacheBlocking::*; -import Processor::*; -import MemArb::*; -import MemTypes::*; - -`include "asim/provides/data_cache.bsh" -`include "asim/provides/instruction_cache.bsh" -`include "asim/provides/processor_library.bsh" - -//interface CoreStats; -// interface DCacheStats dcache; - //interface ICacheStats icache; - //interface ProcStats proc; -//endinterface - -interface Core; - - // Interface from core to main memory - interface Client#(MainMemReq,MainMemResp) mmem_client; - - // Statistics -// interface CoreStats stats; - - // CPU to Host - interface CPUToHost tohost; - - // Interface to Audio Pipeline - interface Audio audio; - -endinterface - -(* synthesize *) -module mkCore(Core); - - // Instantiate the modules - Proc proc <- mkProc(); - ICache#(InstReq,InstResp) icache <- mkInstCache(); - DCache#(DataReq,DataResp) dcache <- mkDataCache(); - MemArb marb <- mkMemArb(); - - // Internal connections - mkConnection( proc.statsEn_get, icache.statsEn_put ); - mkConnection( proc.statsEn_get, dcache.statsEn_put ); - mkConnection( proc.imem_client, icache.proc_server ); - mkConnection( proc.dmem_client, dcache.proc_server ); - mkConnection( icache.mmem_client, marb.cache0_server ); - mkConnection( dcache.mmem_client, marb.cache1_server ); - - // Methods - interface mmem_client = marb.mmem_client; - -// interface CoreStats stats; -// interface dcache = dcache.stats; -// interface icache = icache.stats; -// interface proc = proc.stats; -// endinterface - - interface CPUToHost tohost = proc.tohost; - - interface Audio audio = proc.audio; - -endmodule - diff -r f5dfbe28fa59 -r e5448315b892 modules/bluespec/Pygar/core/proc_trace.awb --- a/modules/bluespec/Pygar/core/proc_trace.awb Fri Apr 30 09:03:10 2010 -0400 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,13 +0,0 @@ -%name 3-Stage Audio Processor -%desc 3-Stage Processor, with audio in one stage per cycle. - -%provides processor - -%attributes 6_375 - -%public Processor.bsv ProcTypes.bsv -%public Processor.dic - - - - diff -r f5dfbe28fa59 -r e5448315b892 modules/bluespec/Pygar/core/proc_types.awb --- a/modules/bluespec/Pygar/core/proc_types.awb Fri Apr 30 09:03:10 2010 -0400 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,10 +0,0 @@ -%name Round-robin Audio memory arbiter -%desc Round-robin memory arbiter - -%provides mem_arb - -%attributes 6_375 - -%public MemArb.bsv - - diff -r f5dfbe28fa59 -r e5448315b892 modules/bluespec/Pygar/core/proc_types.awb~ --- a/modules/bluespec/Pygar/core/proc_types.awb~ Fri Apr 30 09:03:10 2010 -0400 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,10 +0,0 @@ -%name Round-robin Audio memory arbiter -%desc Round-robin memory arbiter - -%provides mem_arb - -%attributes 6_375 - -%public MemArb.bsv - -