Mercurial > pygar
changeset 48:a139cc07b773 pygar svn.49
[svn r49] moved memory into core
author | punk |
---|---|
date | Wed, 05 May 2010 13:42:07 -0400 |
parents | 97d1959f7c5c |
children | 61f6267cb3db |
files | modules/bluespec/Pygar/core/audioCore.bsv modules/bluespec/Pygar/core/audioCorePipeline.bsv |
diffstat | 2 files changed, 40 insertions(+), 38 deletions(-) [+] |
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1.1 --- a/modules/bluespec/Pygar/core/audioCore.bsv Wed May 05 13:23:58 2010 -0400 1.2 +++ b/modules/bluespec/Pygar/core/audioCore.bsv Wed May 05 13:42:07 2010 -0400 1.3 @@ -26,6 +26,7 @@ 1.4 import Processor::*; 1.5 import MemArb::*; 1.6 import MemTypes::*; 1.7 +import FIFO::*; 1.8 1.9 //AWB includes 1.10 `include "asim/provides/low_level_platform_interface.bsh" 1.11 @@ -40,11 +41,13 @@ 1.12 `include "asim/provides/processor.bsh" 1.13 `include "asim/provides/audio_pipe_types.bsh" 1.14 1.15 +// Scratchpad includes 1.16 +`include "asim/provides/scratchpad_memory.bsh" 1.17 +`include "asim/provides/mem_services.bsh" 1.18 +`include "asim/dict/VDEV_SCRATCH.bsh" 1.19 + 1.20 interface Core; 1.21 1.22 - // Interface from core to main memory 1.23 - interface Client#(MainMemReq,MainMemResp) mmem_client; 1.24 - 1.25 interface Get#(AudioProcessorUnit) sampleOutput; 1.26 interface Put#(AudioProcessorUnit) sampleInput; 1.27 1.28 @@ -53,6 +56,7 @@ 1.29 endinterface 1.30 1.31 module [CONNECTED_MODULE] mkCore( Core ); 1.32 + 1.33 1.34 // Instantiate the modules 1.35 1.36 @@ -60,7 +64,11 @@ 1.37 ICache#(InstReq,InstResp) icache <- mkInstCache(); 1.38 DCache#(DataReq,DataResp) dcache <- mkDataCache(); 1.39 MemArb marb <- mkMemArb(); 1.40 + MEMORY_IFC#(Bit#(18), Bit#(32)) memory <- mkScratchpad(`VDEV_SCRATCH_MEMORY, SCRATCHPAD_CACHED); //Services Memory items 1.41 1.42 + // Make this big enough so that several outstanding requests may be supported 1.43 + FIFO#(Bit#(MainMemTagSz)) tags <- mkSizedFIFO(8); 1.44 + 1.45 // Internal connections 1.46 1.47 mkConnection( proc.statsEn_get, icache.statsEn_put ); 1.48 @@ -70,10 +78,33 @@ 1.49 mkConnection( icache.mmem_client, marb.cache0_server ); 1.50 mkConnection( dcache.mmem_client, marb.cache1_server ); 1.51 1.52 + // Memory Access 1.53 + rule sendMemReq; 1.54 + let coreReq <- marb.mmem_client.request.get; 1.55 + case (coreReq) matches 1.56 + tagged LoadReq .load: begin 1.57 +// $display("PIPE Load Addr Req %h", load.addr); 1.58 + //Allocate ROB space 1.59 + memory.readReq(truncate(load.addr>>2)); 1.60 + tags.enq(load.tag); 1.61 + end 1.62 + tagged StoreReq .store: begin 1.63 +// $display("PIPE Write Addr Req %h", store.addr); 1.64 + memory.write(truncate(store.addr>>2),store.data); 1.65 + end 1.66 + endcase 1.67 + endrule 1.68 + 1.69 + rule receiveMemResp; 1.70 + let memResp <- memory.readRsp(); 1.71 + tags.deq; 1.72 + marb.mmem_client.response.put(tagged LoadResp {data:memResp, 1.73 + tag: tags.first}); 1.74 +// $display("PIPE Receive MemReq %x", memResp); 1.75 + endrule 1.76 + 1.77 // Methods 1.78 - 1.79 - interface mmem_client = marb.mmem_client; 1.80 - 1.81 + 1.82 interface sampleOutput = proc.sampleOutput; 1.83 interface sampleInput = proc.sampleInput; 1.84
2.1 --- a/modules/bluespec/Pygar/core/audioCorePipeline.bsv Wed May 05 13:23:58 2010 -0400 2.2 +++ b/modules/bluespec/Pygar/core/audioCorePipeline.bsv Wed May 05 13:42:07 2010 -0400 2.3 @@ -40,9 +40,6 @@ 2.4 `include "asim/provides/mixer.bsh" 2.5 `include "asim/provides/processor_library.bsh" 2.6 `include "asim/provides/fpga_components.bsh" 2.7 -`include "asim/provides/scratchpad_memory.bsh" 2.8 -`include "asim/provides/mem_services.bsh" 2.9 -`include "asim/dict/VDEV_SCRATCH.bsh" 2.10 2.11 `include "asim/rrr/remote_client_stub_AUDIOCORERRR.bsh" 2.12 `include "asim/rrr/remote_server_stub_AUDIOCORERRR.bsh" 2.13 @@ -61,12 +58,10 @@ 2.14 //External memory 2.15 // I'm not comfortable assuming that the memory subsystem is in order 2.16 // So I'll insert a completion buffer here. 2.17 - MEMORY_IFC#(Bit#(18), Bit#(32)) memory <- mkScratchpad(`VDEV_SCRATCH_MEMORY, SCRATCHPAD_CACHED); //Services Memory items 2.18 2.19 // Services Samples 2.20 ClientStub_AUDIOCORERRR client_stub <- mkClientStub_AUDIOCORERRR(); 2.21 - // Make this big enough so that several outstanding requests may be supported 2.22 - FIFO#(Bit#(MainMemTagSz)) tags <- mkSizedFIFO(8); 2.23 + 2.24 2.25 //----------------------------------------------------------- 2.26 // Debug port 2.27 @@ -80,31 +75,7 @@ 2.28 $fdisplay(stderr, " => Cycle = %d", cycle); 2.29 endrule 2.30 2.31 - rule sendMemReq; 2.32 - let coreReq <- core.mmem_client.request.get; 2.33 - case (coreReq) matches 2.34 - tagged LoadReq .load: begin 2.35 -// $display("PIPE Load Addr Req %h", load.addr); 2.36 - //Allocate ROB space 2.37 - memory.readReq(truncate(load.addr>>2)); 2.38 - tags.enq(load.tag); 2.39 - end 2.40 - tagged StoreReq .store: begin 2.41 -// $display("PIPE Write Addr Req %h", store.addr); 2.42 - memory.write(truncate(store.addr>>2),store.data); 2.43 - end 2.44 - endcase 2.45 - endrule 2.46 - 2.47 - rule receiveMemResp; 2.48 - let memResp <- memory.readRsp(); 2.49 - tags.deq; 2.50 - core.mmem_client.response.put(tagged LoadResp {data:memResp, 2.51 - tag: tags.first}); 2.52 -// $display("PIPE Receive MemReq %x", memResp); 2.53 - endrule 2.54 - 2.55 - rule feedOutput; 2.56 + rule feedOutput; 2.57 let pipelineData <- core.sampleOutput.get(); 2.58 AudioProcessorControl endOfFileTag = EndOfFile; 2.59 AudioProcessorControl sampleTag = Data; 2.60 @@ -131,7 +102,7 @@ 2.61 AudioProcessorControl ctrl = unpack(truncate(command.ctrl)); 2.62 2.63 Bit#(32) test = unpack(truncate(command.channel)); 2.64 - $display("rlm: %x", test); 2.65 +// $display("rlm: %x", test); 2.66 2.67 2.68 if(ctrl == EndOfFile)