# HG changeset patch
# User punk
# Date 1273081327 14400
# Node ID a139cc07b773cbaf07b0ab83586c95f21aed47ed
# Parent  97d1959f7c5ca020c5becc8d64d74f732f22b7fc
[svn r49] moved memory into core

diff -r 97d1959f7c5c -r a139cc07b773 modules/bluespec/Pygar/core/audioCore.bsv
--- a/modules/bluespec/Pygar/core/audioCore.bsv	Wed May 05 13:23:58 2010 -0400
+++ b/modules/bluespec/Pygar/core/audioCore.bsv	Wed May 05 13:42:07 2010 -0400
@@ -26,6 +26,7 @@
 import Processor::*;
 import MemArb::*;
 import MemTypes::*;
+import FIFO::*;
 
 //AWB includes
 `include "asim/provides/low_level_platform_interface.bsh"
@@ -40,11 +41,13 @@
 `include "asim/provides/processor.bsh"
 `include "asim/provides/audio_pipe_types.bsh"
 
+// Scratchpad includes
+`include "asim/provides/scratchpad_memory.bsh"
+`include "asim/provides/mem_services.bsh"
+`include "asim/dict/VDEV_SCRATCH.bsh"
+
 interface Core;
 
-  // Interface from core to main memory
-   interface Client#(MainMemReq,MainMemResp) mmem_client;
-
    interface Get#(AudioProcessorUnit) sampleOutput;
    interface Put#(AudioProcessorUnit) sampleInput;
 	 
@@ -53,6 +56,7 @@
 endinterface
 
 module   [CONNECTED_MODULE]  mkCore( Core );
+   
 
   // Instantiate the modules
 
@@ -60,7 +64,11 @@
   ICache#(InstReq,InstResp) icache <- mkInstCache();
   DCache#(DataReq,DataResp) dcache <- mkDataCache();
   MemArb marb <- mkMemArb();
+  MEMORY_IFC#(Bit#(18), Bit#(32)) memory <- mkScratchpad(`VDEV_SCRATCH_MEMORY, SCRATCHPAD_CACHED);   //Services Memory items
 
+  // Make this big enough so that several outstanding requests may be supported
+  FIFO#(Bit#(MainMemTagSz)) tags <- mkSizedFIFO(8);
+   
   // Internal connections
 
   mkConnection( proc.statsEn_get,   icache.statsEn_put );
@@ -70,10 +78,33 @@
   mkConnection( icache.mmem_client, marb.cache0_server );
   mkConnection( dcache.mmem_client, marb.cache1_server );
 
+  // Memory Access
+  rule sendMemReq;
+    let coreReq <- marb.mmem_client.request.get;
+    case (coreReq) matches 
+      tagged LoadReq .load: begin
+//	                      $display("PIPE Load Addr Req %h", load.addr); 
+                              //Allocate ROB space
+                              memory.readReq(truncate(load.addr>>2));
+                              tags.enq(load.tag);
+                            end
+      tagged StoreReq .store: begin
+//	  	              $display("PIPE Write Addr Req %h", store.addr); 
+	                      memory.write(truncate(store.addr>>2),store.data);
+                              end
+    endcase
+  endrule
+  
+  rule receiveMemResp;
+    let memResp <- memory.readRsp();
+    tags.deq;
+    marb.mmem_client.response.put(tagged LoadResp {data:memResp,
+                                                   tag: tags.first});
+//   	                $display("PIPE Receive MemReq %x", memResp); 
+  endrule
+
   // Methods
-
-   interface mmem_client = marb.mmem_client;
-      
+     
    interface sampleOutput = proc.sampleOutput;
    interface sampleInput = proc.sampleInput;
 
diff -r 97d1959f7c5c -r a139cc07b773 modules/bluespec/Pygar/core/audioCorePipeline.bsv
--- a/modules/bluespec/Pygar/core/audioCorePipeline.bsv	Wed May 05 13:23:58 2010 -0400
+++ b/modules/bluespec/Pygar/core/audioCorePipeline.bsv	Wed May 05 13:42:07 2010 -0400
@@ -40,9 +40,6 @@
 `include "asim/provides/mixer.bsh"
 `include "asim/provides/processor_library.bsh"
 `include "asim/provides/fpga_components.bsh"
-`include "asim/provides/scratchpad_memory.bsh"
-`include "asim/provides/mem_services.bsh"
-`include "asim/dict/VDEV_SCRATCH.bsh"
 
 `include "asim/rrr/remote_client_stub_AUDIOCORERRR.bsh"
 `include "asim/rrr/remote_server_stub_AUDIOCORERRR.bsh"
@@ -61,12 +58,10 @@
   //External memory 
   // I'm not comfortable assuming that the memory subsystem is in order  
   // So I'll insert a completion buffer here.
-  MEMORY_IFC#(Bit#(18), Bit#(32)) memory <- mkScratchpad(`VDEV_SCRATCH_MEMORY, SCRATCHPAD_CACHED);   //Services Memory items
 
   // Services Samples 
   ClientStub_AUDIOCORERRR client_stub <- mkClientStub_AUDIOCORERRR();   
-  // Make this big enough so that several outstanding requests may be supported
-  FIFO#(Bit#(MainMemTagSz)) tags <- mkSizedFIFO(8);
+  
 
    //-----------------------------------------------------------
    // Debug port
@@ -80,31 +75,7 @@
     $fdisplay(stderr, " => Cycle = %d", cycle);
   endrule
 
-  rule sendMemReq;
-    let coreReq <- core.mmem_client.request.get;
-    case (coreReq) matches 
-      tagged LoadReq .load: begin
-//	                      $display("PIPE Load Addr Req %h", load.addr); 
-                              //Allocate ROB space
-                              memory.readReq(truncate(load.addr>>2));
-                              tags.enq(load.tag);
-                            end
-       tagged StoreReq .store: begin
-//	  	              $display("PIPE Write Addr Req %h", store.addr); 
-	                      memory.write(truncate(store.addr>>2),store.data);
-                              end
-    endcase
-  endrule
-  
-  rule receiveMemResp;
-    let memResp <- memory.readRsp();
-    tags.deq;
-    core.mmem_client.response.put(tagged LoadResp {data:memResp,
-                                                   tag: tags.first});
-//   	                $display("PIPE Receive MemReq %x", memResp); 
-  endrule
-
-   rule feedOutput;
+  rule feedOutput;
      let pipelineData <- core.sampleOutput.get();
      AudioProcessorControl endOfFileTag = EndOfFile;
      AudioProcessorControl sampleTag = Data;
@@ -131,7 +102,7 @@
      AudioProcessorControl ctrl = unpack(truncate(command.ctrl));
 
       Bit#(32) test = unpack(truncate(command.channel));
-      $display("rlm: %x", test);
+//      $display("rlm: %x", test);
 	   
 
       if(ctrl == EndOfFile)