1.1 --- a/modules/bluespec/Pygar/core/Processor.bsv	Wed May 05 13:42:07 2010 -0400
     1.2 +++ b/modules/bluespec/Pygar/core/Processor.bsv	Wed May 05 14:40:48 2010 -0400
     1.3 @@ -262,8 +262,10 @@
     1.4  
     1.5     //Or:
     1.6     // Statistics state
     1.7 -   STAT num_cycles <- mkStatCounter(`STATS_PROCESSOR_CYCLE_COUNT);
     1.8 -   STAT num_inst <- mkStatCounter(`STATS_PROCESSOR_INST_COUNT);
     1.9 +  
    1.10 +   //rlm: removing these to avoid their broken stupidness.
    1.11 +   //STAT num_cycles <- mkStatCounter(`STATS_PROCESSOR_CYCLE_COUNT);
    1.12 +   //STAT num_inst <- mkStatCounter(`STATS_PROCESSOR_INST_COUNT);
    1.13  
    1.14     //-----------------------------------------------------------
    1.15     // Rules
    1.16 @@ -535,9 +537,9 @@
    1.17         end
    1.18       else
    1.19  	pcQ.deq();
    1.20 -
    1.21 -    if ( cp0_statsEn )
    1.22 -      num_inst.incr();
    1.23 +   //rlm: removing
    1.24 +   // if ( cp0_statsEn )
    1.25 +   //   num_inst.incr();
    1.26  
    1.27    endrule
    1.28  
    1.29 @@ -561,10 +563,11 @@
    1.30             
    1.31    endrule
    1.32  
    1.33 -  rule inc_num_cycles;
    1.34 -    if ( cp0_statsEn )
    1.35 -      num_cycles.incr();
    1.36 -  endrule
    1.37 +//rlm remove
    1.38 + // rule inc_num_cycles;
    1.39 + //   if ( cp0_statsEn )
    1.40 + //     num_cycles.incr();
    1.41 + // endrule
    1.42  
    1.43  /*
    1.44   // for now, we don't do anything.

     2.1 --- a/modules/bluespec/Pygar/lab4/DataCacheBlocking.bsv	Wed May 05 13:42:07 2010 -0400
     2.2 +++ b/modules/bluespec/Pygar/lab4/DataCacheBlocking.bsv	Wed May 05 14:40:48 2010 -0400
     2.3 @@ -130,10 +130,10 @@
     2.4    // Statistics state
     2.5  
     2.6    Reg#(Bool)     statsEn        <- mkReg(False);
     2.7 -
     2.8 -  STAT num_accesses <- mkStatCounter(`STATS_DATA_CACHE_NUM_ACCESSES);
     2.9 -  STAT num_misses <- mkStatCounter(`STATS_DATA_CACHE_NUM_MISSES);
    2.10 -  STAT num_writebacks <- mkStatCounter(`STATS_DATA_CACHE_NUM_WRITEBACKS);
    2.11 +   //rlm: 
    2.12 +  //STAT num_accesses <- mkStatCounter(`STATS_DATA_CACHE_NUM_ACCESSES);
    2.13 +  //STAT num_misses <- mkStatCounter(`STATS_DATA_CACHE_NUM_MISSES);
    2.14 +  //STAT num_writebacks <- mkStatCounter(`STATS_DATA_CACHE_NUM_WRITEBACKS);
    2.15  
    2.16    //-----------------------------------------------------------
    2.17    // Name some wires
    2.18 @@ -160,9 +160,9 @@
    2.19    rule access ( (stage == Access) && respQ.notFull() );
    2.20  
    2.21      // Statistics
    2.22 -
    2.23 -    if ( statsEn )
    2.24 -       num_accesses.incr();
    2.25 +     //rlm: 
    2.26 +    //if ( statsEn )
    2.27 +      // num_accesses.incr();
    2.28   
    2.29  
    2.30      // Get the corresponding tag from the rams
    2.31 @@ -196,16 +196,17 @@
    2.32      else 
    2.33        begin
    2.34          traceTiny("mkDataCacheBlocking", "hitMiss","m");
    2.35 -        if ( statsEn )
    2.36 -          num_misses.incr();
    2.37 +         //rlm: 
    2.38 +	 //if ( statsEn )
    2.39 +         // num_misses.incr();
    2.40  
    2.41          // Currently we don't use dirty bits so we always writeback the data if it is valid
    2.42  
    2.43          if ( isValid(cacheLineTag) )
    2.44           begin
    2.45 -
    2.46 -           if ( statsEn )
    2.47 -             num_writebacks.incr();
    2.48 +	    //rlm: 
    2.49 +          // if ( statsEn )
    2.50 +            // num_writebacks.incr();
    2.51  
    2.52  	   MainMemReq wbReq 
    2.53  	    = StoreReq { tag  : 0, 

     3.1 --- a/modules/bluespec/Pygar/lab4/InstCacheBlocking.bsv	Wed May 05 13:42:07 2010 -0400
     3.2 +++ b/modules/bluespec/Pygar/lab4/InstCacheBlocking.bsv	Wed May 05 14:40:48 2010 -0400
     3.3 @@ -132,9 +132,10 @@
     3.4  
     3.5    Reg#(Bool)     statsEn        <- mkReg(False);
     3.6  
     3.7 -  STAT num_accesses <- mkStatCounter(`STATS_INST_CACHE_NUM_ACCESSES);
     3.8 -  STAT num_misses <- mkStatCounter(`STATS_INST_CACHE_NUM_MISSES);
     3.9 -  STAT num_evictions <- mkStatCounter(`STATS_INST_CACHE_NUM_EVICTIONS);
    3.10 +   //rlm: 
    3.11 +  //STAT num_accesses <- mkStatCounter(`STATS_INST_CACHE_NUM_ACCESSES);
    3.12 +  //STAT num_misses <- mkStatCounter(`STATS_INST_CACHE_NUM_MISSES);
    3.13 +  //STAT num_evictions <- mkStatCounter(`STATS_INST_CACHE_NUM_EVICTIONS);
    3.14  
    3.15    //-----------------------------------------------------------
    3.16    // Name some wires
    3.17 @@ -162,9 +163,9 @@
    3.18    rule access ( (stage == Access) && respQ.notFull() );
    3.19  
    3.20      // Statistics
    3.21 -
    3.22 -    if ( statsEn )
    3.23 -      num_accesses.incr();
    3.24 +     //rlm: 
    3.25 +   // if ( statsEn )
    3.26 +     // num_accesses.incr();
    3.27    
    3.28      // Check tag and valid bit to see if this is a hit or a miss
    3.29  
    3.30 @@ -195,11 +196,12 @@
    3.31      else 
    3.32       begin
    3.33         traceTiny("mkInstCacheBlocking", "hitMiss","m");
    3.34 -       if ( statsEn )
    3.35 -         num_misses.incr();
    3.36 -       if ( statsEn )
    3.37 -         if ( isJust(cacheLineTag) )
    3.38 -	   num_evictions.incr();	
    3.39 +       //rlm:
    3.40 +	//if ( statsEn )
    3.41 +         //num_misses.incr();
    3.42 +       //if ( statsEn )
    3.43 +         //if ( isJust(cacheLineTag) )
    3.44 +	   //num_evictions.incr();	
    3.45  
    3.46         MainMemReq rfReq
    3.47          = LoadReq { tag  : 0,