# HG changeset patch
# User rlm
# Date 1273084848 14400
# Node ID 61f6267cb3dbdfaac10459756584c8240436a7b3
# Parent  a139cc07b773cbaf07b0ab83586c95f21aed47ed
[svn r50] removed problematic stats stuff

diff -r a139cc07b773 -r 61f6267cb3db modules/bluespec/Pygar/core/Processor.bsv
--- a/modules/bluespec/Pygar/core/Processor.bsv	Wed May 05 13:42:07 2010 -0400
+++ b/modules/bluespec/Pygar/core/Processor.bsv	Wed May 05 14:40:48 2010 -0400
@@ -262,8 +262,10 @@
 
    //Or:
    // Statistics state
-   STAT num_cycles <- mkStatCounter(`STATS_PROCESSOR_CYCLE_COUNT);
-   STAT num_inst <- mkStatCounter(`STATS_PROCESSOR_INST_COUNT);
+  
+   //rlm: removing these to avoid their broken stupidness.
+   //STAT num_cycles <- mkStatCounter(`STATS_PROCESSOR_CYCLE_COUNT);
+   //STAT num_inst <- mkStatCounter(`STATS_PROCESSOR_INST_COUNT);
 
    //-----------------------------------------------------------
    // Rules
@@ -535,9 +537,9 @@
        end
      else
 	pcQ.deq();
-
-    if ( cp0_statsEn )
-      num_inst.incr();
+   //rlm: removing
+   // if ( cp0_statsEn )
+   //   num_inst.incr();
 
   endrule
 
@@ -561,10 +563,11 @@
            
   endrule
 
-  rule inc_num_cycles;
-    if ( cp0_statsEn )
-      num_cycles.incr();
-  endrule
+//rlm remove
+ // rule inc_num_cycles;
+ //   if ( cp0_statsEn )
+ //     num_cycles.incr();
+ // endrule
 
 /*
  // for now, we don't do anything.
diff -r a139cc07b773 -r 61f6267cb3db modules/bluespec/Pygar/lab4/DataCacheBlocking.bsv
--- a/modules/bluespec/Pygar/lab4/DataCacheBlocking.bsv	Wed May 05 13:42:07 2010 -0400
+++ b/modules/bluespec/Pygar/lab4/DataCacheBlocking.bsv	Wed May 05 14:40:48 2010 -0400
@@ -130,10 +130,10 @@
   // Statistics state
 
   Reg#(Bool)     statsEn        <- mkReg(False);
-
-  STAT num_accesses <- mkStatCounter(`STATS_DATA_CACHE_NUM_ACCESSES);
-  STAT num_misses <- mkStatCounter(`STATS_DATA_CACHE_NUM_MISSES);
-  STAT num_writebacks <- mkStatCounter(`STATS_DATA_CACHE_NUM_WRITEBACKS);
+   //rlm: 
+  //STAT num_accesses <- mkStatCounter(`STATS_DATA_CACHE_NUM_ACCESSES);
+  //STAT num_misses <- mkStatCounter(`STATS_DATA_CACHE_NUM_MISSES);
+  //STAT num_writebacks <- mkStatCounter(`STATS_DATA_CACHE_NUM_WRITEBACKS);
 
   //-----------------------------------------------------------
   // Name some wires
@@ -160,9 +160,9 @@
   rule access ( (stage == Access) && respQ.notFull() );
 
     // Statistics
-
-    if ( statsEn )
-       num_accesses.incr();
+     //rlm: 
+    //if ( statsEn )
+      // num_accesses.incr();
  
 
     // Get the corresponding tag from the rams
@@ -196,16 +196,17 @@
     else 
       begin
         traceTiny("mkDataCacheBlocking", "hitMiss","m");
-        if ( statsEn )
-          num_misses.incr();
+         //rlm: 
+	 //if ( statsEn )
+         // num_misses.incr();
 
         // Currently we don't use dirty bits so we always writeback the data if it is valid
 
         if ( isValid(cacheLineTag) )
          begin
-
-           if ( statsEn )
-             num_writebacks.incr();
+	    //rlm: 
+          // if ( statsEn )
+            // num_writebacks.incr();
 
 	   MainMemReq wbReq 
 	    = StoreReq { tag  : 0, 
diff -r a139cc07b773 -r 61f6267cb3db modules/bluespec/Pygar/lab4/InstCacheBlocking.bsv
--- a/modules/bluespec/Pygar/lab4/InstCacheBlocking.bsv	Wed May 05 13:42:07 2010 -0400
+++ b/modules/bluespec/Pygar/lab4/InstCacheBlocking.bsv	Wed May 05 14:40:48 2010 -0400
@@ -132,9 +132,10 @@
 
   Reg#(Bool)     statsEn        <- mkReg(False);
 
-  STAT num_accesses <- mkStatCounter(`STATS_INST_CACHE_NUM_ACCESSES);
-  STAT num_misses <- mkStatCounter(`STATS_INST_CACHE_NUM_MISSES);
-  STAT num_evictions <- mkStatCounter(`STATS_INST_CACHE_NUM_EVICTIONS);
+   //rlm: 
+  //STAT num_accesses <- mkStatCounter(`STATS_INST_CACHE_NUM_ACCESSES);
+  //STAT num_misses <- mkStatCounter(`STATS_INST_CACHE_NUM_MISSES);
+  //STAT num_evictions <- mkStatCounter(`STATS_INST_CACHE_NUM_EVICTIONS);
 
   //-----------------------------------------------------------
   // Name some wires
@@ -162,9 +163,9 @@
   rule access ( (stage == Access) && respQ.notFull() );
 
     // Statistics
-
-    if ( statsEn )
-      num_accesses.incr();
+     //rlm: 
+   // if ( statsEn )
+     // num_accesses.incr();
   
     // Check tag and valid bit to see if this is a hit or a miss
 
@@ -195,11 +196,12 @@
     else 
      begin
        traceTiny("mkInstCacheBlocking", "hitMiss","m");
-       if ( statsEn )
-         num_misses.incr();
-       if ( statsEn )
-         if ( isJust(cacheLineTag) )
-	   num_evictions.incr();	
+       //rlm:
+	//if ( statsEn )
+         //num_misses.incr();
+       //if ( statsEn )
+         //if ( isJust(cacheLineTag) )
+	   //num_evictions.incr();	
 
        MainMemReq rfReq
         = LoadReq { tag  : 0,