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changeset 60:6179c07c21d7 pygar svn.61

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[svn r61] synthesis boundaries
author punk
date Mon, 10 May 2010 20:29:20 -0400
parents 92041177735c
children 74d2fe78f36a
files modules/bluespec/Pygar/lab4/BRegFile.bsv modules/bluespec/Pygar/lab4/DataCacheBlocking.bsv modules/bluespec/Pygar/lab4/InstCacheBlocking.bsv modules/bluespec/Pygar/lab4/data_cache.awb modules/bluespec/Pygar/lab4/instruction_cache.awb
diffstat 5 files changed, 11 insertions(+), 1 deletions(-) [+]
line wrap: on
line diff
     1.1 --- a/modules/bluespec/Pygar/lab4/BRegFile.bsv	Mon May 10 13:50:40 2010 -0400
     1.2 +++ b/modules/bluespec/Pygar/lab4/BRegFile.bsv	Mon May 10 20:29:20 2010 -0400
     1.3 @@ -16,6 +16,9 @@
     1.4     method data_t sub(index_t addr);
     1.5  endinterface
     1.6  
     1.7 +
     1.8 +(* doc = "synthesis attribute ram_style mkBRegFile distributed;" *)
     1.9 +(* synthesize *)
    1.10  module mkBRegFile(RegFile#(index_t, data_t)) 
    1.11     provisos (Bits#(index_t, size_index),
    1.12  	     Bits#(data_t, size_data),

     2.1 --- a/modules/bluespec/Pygar/lab4/DataCacheBlocking.bsv	Mon May 10 13:50:40 2010 -0400
     2.2 +++ b/modules/bluespec/Pygar/lab4/DataCacheBlocking.bsv	Mon May 10 20:29:20 2010 -0400
     2.3 @@ -108,6 +108,8 @@
     2.4  // Main module
     2.5  //----------------------------------------------------------------------
     2.6  
     2.7 +(* doc = "synthesis attribute ram_style mkDataCache distributed;" *)
     2.8 +(* synthesize *)
     2.9  module [CONNECTED_MODULE] mkDataCache( DCache#(DataReq,DataResp) );
    2.10  
    2.11    //-----------------------------------------------------------

     3.1 --- a/modules/bluespec/Pygar/lab4/InstCacheBlocking.bsv	Mon May 10 13:50:40 2010 -0400
     3.2 +++ b/modules/bluespec/Pygar/lab4/InstCacheBlocking.bsv	Mon May 10 20:29:20 2010 -0400
     3.3 @@ -109,6 +109,8 @@
     3.4  // Main module
     3.5  //----------------------------------------------------------------------
     3.6  
     3.7 +(* doc = "synthesis attribute ram_style mkInstCache distributed;" *)
     3.8 +(* synthesize *)
     3.9  module [CONNECTED_MODULE] mkInstCache( ICache#(InstReq,InstResp) );
    3.10  
    3.11    //-----------------------------------------------------------

     4.1 --- a/modules/bluespec/Pygar/lab4/data_cache.awb	Mon May 10 13:50:40 2010 -0400
     4.2 +++ b/modules/bluespec/Pygar/lab4/data_cache.awb	Mon May 10 20:29:20 2010 -0400
     4.3 @@ -8,3 +8,5 @@
     4.4  %public DataCacheBlocking.bsv
     4.5  %public DataCache.dic
     4.6  
     4.7 +%generated -t VERILOG mkDataCache.v
     4.8 +%generated -t BA mkDataCache.ba
     4.9 \ No newline at end of file

     5.1 --- a/modules/bluespec/Pygar/lab4/instruction_cache.awb	Mon May 10 13:50:40 2010 -0400
     5.2 +++ b/modules/bluespec/Pygar/lab4/instruction_cache.awb	Mon May 10 20:29:20 2010 -0400
     5.3 @@ -8,4 +8,5 @@
     5.4  %public InstCacheBlocking.bsv
     5.5  %public InstCache.dic
     5.6  
     5.7 -
     5.8 +%generated -t VERILOG mkInstCache.v
     5.9 +%generated -t BA mkInstCache.ba
    5.10 \ No newline at end of file