# HG changeset patch # User punk # Date 1273537760 14400 # Node ID 6179c07c21d7635a817d303c71f380a7e64018b9 # Parent 92041177735c34180bcacd8acb8239f1c85e3f39 [svn r61] synthesis boundaries diff -r 92041177735c -r 6179c07c21d7 modules/bluespec/Pygar/lab4/BRegFile.bsv --- a/modules/bluespec/Pygar/lab4/BRegFile.bsv Mon May 10 13:50:40 2010 -0400 +++ b/modules/bluespec/Pygar/lab4/BRegFile.bsv Mon May 10 20:29:20 2010 -0400 @@ -16,6 +16,9 @@ method data_t sub(index_t addr); endinterface + +(* doc = "synthesis attribute ram_style mkBRegFile distributed;" *) +(* synthesize *) module mkBRegFile(RegFile#(index_t, data_t)) provisos (Bits#(index_t, size_index), Bits#(data_t, size_data), diff -r 92041177735c -r 6179c07c21d7 modules/bluespec/Pygar/lab4/DataCacheBlocking.bsv --- a/modules/bluespec/Pygar/lab4/DataCacheBlocking.bsv Mon May 10 13:50:40 2010 -0400 +++ b/modules/bluespec/Pygar/lab4/DataCacheBlocking.bsv Mon May 10 20:29:20 2010 -0400 @@ -108,6 +108,8 @@ // Main module //---------------------------------------------------------------------- +(* doc = "synthesis attribute ram_style mkDataCache distributed;" *) +(* synthesize *) module [CONNECTED_MODULE] mkDataCache( DCache#(DataReq,DataResp) ); //----------------------------------------------------------- diff -r 92041177735c -r 6179c07c21d7 modules/bluespec/Pygar/lab4/InstCacheBlocking.bsv --- a/modules/bluespec/Pygar/lab4/InstCacheBlocking.bsv Mon May 10 13:50:40 2010 -0400 +++ b/modules/bluespec/Pygar/lab4/InstCacheBlocking.bsv Mon May 10 20:29:20 2010 -0400 @@ -109,6 +109,8 @@ // Main module //---------------------------------------------------------------------- +(* doc = "synthesis attribute ram_style mkInstCache distributed;" *) +(* synthesize *) module [CONNECTED_MODULE] mkInstCache( ICache#(InstReq,InstResp) ); //----------------------------------------------------------- diff -r 92041177735c -r 6179c07c21d7 modules/bluespec/Pygar/lab4/data_cache.awb --- a/modules/bluespec/Pygar/lab4/data_cache.awb Mon May 10 13:50:40 2010 -0400 +++ b/modules/bluespec/Pygar/lab4/data_cache.awb Mon May 10 20:29:20 2010 -0400 @@ -8,3 +8,5 @@ %public DataCacheBlocking.bsv %public DataCache.dic +%generated -t VERILOG mkDataCache.v +%generated -t BA mkDataCache.ba \ No newline at end of file diff -r 92041177735c -r 6179c07c21d7 modules/bluespec/Pygar/lab4/instruction_cache.awb --- a/modules/bluespec/Pygar/lab4/instruction_cache.awb Mon May 10 13:50:40 2010 -0400 +++ b/modules/bluespec/Pygar/lab4/instruction_cache.awb Mon May 10 20:29:20 2010 -0400 @@ -8,4 +8,5 @@ %public InstCacheBlocking.bsv %public InstCache.dic - +%generated -t VERILOG mkInstCache.v +%generated -t BA mkInstCache.ba \ No newline at end of file