Mercurial > pygar
changeset 43:4d87fa55a776 pygar svn.44
[svn r44] processor largely working and mixer in good status
| author | punk |
|---|---|
| date | Wed, 05 May 2010 12:28:07 -0400 |
| parents | ced2ebd41347 |
| children | 9b0dfce52c29 |
| files | modules/bluespec/Pygar/core/AudioCoreSystem.cpp modules/bluespec/Pygar/core/PathTypes.bsv modules/bluespec/Pygar/core/Processor.bsv modules/bluespec/Pygar/core/audioCorePipeline.bsv |
| diffstat | 4 files changed, 24 insertions(+), 27 deletions(-) [+] |
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1.1 --- a/modules/bluespec/Pygar/core/AudioCoreSystem.cpp Wed May 05 01:09:09 2010 -0400 1.2 +++ b/modules/bluespec/Pygar/core/AudioCoreSystem.cpp Wed May 05 12:28:07 2010 -0400 1.3 @@ -132,7 +132,7 @@ 1.4 1.5 //rlm: two files. 1.6 // clientStub->SendUnprocessedStream( Data,(UINT32)sample); 1.7 - clientStub->SendUnprocessedStream((UINT32)channel0 , Data,(UINT32)sample); 1.8 + clientStub->SendUnprocessedStream((UINT32)channel0 , Data,(UINT32)sample); 1.9 //clientStub->SendUnprocessedStream(channel1 , Data,(UINT32)sample1); 1.10 1.11 }
2.1 --- a/modules/bluespec/Pygar/core/PathTypes.bsv Wed May 05 01:09:09 2010 -0400 2.2 +++ b/modules/bluespec/Pygar/core/PathTypes.bsv Wed May 05 12:28:07 2010 -0400 2.3 @@ -14,7 +14,7 @@ 2.4 typedef Int#(TLog#(`MAX_PATH_IDS)) PathId; 2.5 //typedef Int#(16) Sample; 2.6 typedef Int#(TLog#(`MAX_VOICES)) VoiceId; 2.7 -typedef Bit#(8) Volume; // This is arbitrarily set to 8 bits or max val 256 2.8 +typedef Int#(8) Volume; // This is arbitrarily set to 8 bits or max val 256 2.9 2.10 //The mixer is identified as PathId 0, path end is max 2.11 PathId mixerId = 0;
3.1 --- a/modules/bluespec/Pygar/core/Processor.bsv Wed May 05 01:09:09 2010 -0400 3.2 +++ b/modules/bluespec/Pygar/core/Processor.bsv Wed May 05 12:28:07 2010 -0400 3.3 @@ -252,7 +252,7 @@ 3.4 FIFO#(DataResp) dataRespQ <- mkFIFO(); 3.5 3.6 // Audio I/O 3.7 - FIFO#(AudioProcessorUnit) inAudioFifo <- mkFIFO; 3.8 + FIFO#(AudioProcessorUnit) inAudioFifo <- mkSizedFIFO(512); 3.9 FIFO#(AudioProcessorUnit) outAudioFifo <- mkFIFO; 3.10 3.11 3.12 @@ -372,7 +372,6 @@ 3.13 end 3.14 tagged LUI .it : 3.15 begin 3.16 - $display("PROCESSOR Instr LUI\n"); 3.17 Bit#(32) zext_it_imm = zext(it.imm); 3.18 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(zext_it_imm << 32'd16) }); 3.19 end 3.20 @@ -458,14 +457,12 @@ 3.21 3.22 tagged JR .it : 3.23 begin 3.24 - $display("PROCESSOR inst JR\n"); 3.25 newPC = rf.rd1(it.rsrc); 3.26 branchTaken = True; 3.27 end 3.28 3.29 tagged JAL .it : 3.30 begin 3.31 - $display("PROCESSOR inst JAL\n"); 3.32 wbQ.enq(tagged WB_ALU {dest:31, data:pc_plus4 }); 3.33 newPC = { pc_plus4[31:28], it.target, 2'b0 }; 3.34 branchTaken = True; 3.35 @@ -482,7 +479,7 @@ 3.36 3.37 tagged MTC0 .it : //Recieve things from host computer 3.38 begin 3.39 - $display( " PROCESSOR MTC0 call\n"); 3.40 +// $display( " PROCESSOR MTC0 call\n"); 3.41 case ( it.cop0dst ) 3.42 5'd10 : cp0_statsEn <= unpack(truncate(rf.rd1(it.rsrc))); 3.43 5'd21 : cp0_tohost <= truncate(rf.rd1(it.rsrc)); 3.44 @@ -497,22 +494,21 @@ 3.45 //this is host stuff? 3.46 tagged MFC0 .it : //Things out 3.47 begin 3.48 - $display( " PROCESSOR MFC0 call\n"); 3.49 case ( it.cop0src ) 3.50 // not actually an ALU instruction but don't have the format otherwise 3.51 5'd10 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(cp0_statsEn)) }); 3.52 5'd20 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_fromhost }); 3.53 5'd21 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_tohost }); 3.54 5'd25 : begin 3.55 - $display( "**** EOF Requested\n "); 3.56 +// $display( "**** EOF Requested\n "); 3.57 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(cp0_audioEOF)) }); // Reading clears bit 3.58 cp0_audioEOF <= False; 3.59 end 3.60 5'd28 : begin 3.61 - $display( "***** Reqesting Sample \n"); 3.62 +// $display( "***** Reqesting Sample \n"); 3.63 let sample = inAudioFifo.first(); // is this going to cause perf. delay? 3.64 if (sample matches tagged Sample .audio) // if it is EOF another rule sets the cp0_audioEOF 3.65 - wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(audio)) }); // do I need pack? 3.66 + wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(audio)) }); // do I need pack? 3.67 else $display ( "Audio File EOF Reached. Invalid sample request."); 3.68 inAudioFifo.deq(); 3.69 end 3.70 @@ -570,26 +566,27 @@ 3.71 num_cycles.incr(); 3.72 endrule 3.73 3.74 - 3.75 +/* 3.76 // for now, we don't do anything. 3.77 -// rule connectAudioReqResp; 3.78 -// $display("rlm: PROCESSOR copies a datum\n"); 3.79 -// outAudioFifo.enq(inAudioFifo.first()); 3.80 -// inAudioFifo.deq; 3.81 -// endrule 3.82 + rule connectAudioReqResp; 3.83 + $display("rlm: PROCESSOR copies a datum\n"); 3.84 + outAudioFifo.enq(inAudioFifo.first()); 3.85 + inAudioFifo.deq; 3.86 + endrule 3.87 +*/ 3.88 3.89 rule flagAudioEnd (inAudioFifo.first() matches tagged EndOfFile); 3.90 $display (" PROCESSOR End Audio Flag Set "); 3.91 cp0_audioEOF <= True; 3.92 inAudioFifo.deq; 3.93 endrule 3.94 -/* 3.95 + 3.96 rule sendAudioEnd (cp0_progComp); 3.97 $display (" PROCESSOR Says Program Complete "); 3.98 outAudioFifo.enq(tagged EndOfFile); 3.99 cp0_progComp <= False; //only send one. And functions to reset 3.100 endrule 3.101 -*/ 3.102 + 3.103 3.104 //----------------------------------------------------------- 3.105 // Methods
4.1 --- a/modules/bluespec/Pygar/core/audioCorePipeline.bsv Wed May 05 01:09:09 2010 -0400 4.2 +++ b/modules/bluespec/Pygar/core/audioCorePipeline.bsv Wed May 05 12:28:07 2010 -0400 4.3 @@ -37,7 +37,7 @@ 4.4 `include "asim/provides/audio_pipe_types.bsh" //provides Audio Pipeline interface 4.5 `include "asim/provides/path_types.bsh" 4.6 `include "asim/provides/core.bsh" 4.7 -//`include "asim/provides/mixer.bsh" 4.8 +`include "asim/provides/mixer.bsh" 4.9 `include "asim/provides/processor_library.bsh" 4.10 `include "asim/provides/fpga_components.bsh" 4.11 `include "asim/provides/scratchpad_memory.bsh" 4.12 @@ -79,13 +79,13 @@ 4.13 let coreReq <- core.mmem_client.request.get; 4.14 case (coreReq) matches 4.15 tagged LoadReq .load: begin 4.16 - $display("PIPE Load Addr Req %x", load.addr); 4.17 +// $display("PIPE Load Addr Req %h", load.addr); 4.18 //Allocate ROB space 4.19 memory.readReq(truncate(load.addr>>2)); 4.20 tags.enq(load.tag); 4.21 end 4.22 tagged StoreReq .store: begin 4.23 - $display("PIPE Write Addr Req %x", store.addr); 4.24 +// $display("PIPE Write Addr Req %h", store.addr); 4.25 memory.write(truncate(store.addr>>2),store.data); 4.26 end 4.27 endcase 4.28 @@ -96,7 +96,7 @@ 4.29 tags.deq; 4.30 core.mmem_client.response.put(tagged LoadResp {data:memResp, 4.31 tag: tags.first}); 4.32 - $display("PIPE Receive MemReq %x", memResp); 4.33 +// $display("PIPE Receive MemReq %x", memResp); 4.34 endrule 4.35 4.36 rule feedOutput; 4.37 @@ -131,13 +131,13 @@ 4.38 4.39 if(ctrl == EndOfFile) 4.40 begin 4.41 - $display("lsp: PROCESSOR received EOF "); 4.42 - core.sampleInput.put(tagged EndOfFile); 4.43 + $display("lsp: PIPE received EOF "); 4.44 + core.sampleInput.put(tagged EndOfFile); 4.45 end 4.46 else 4.47 begin 4.48 - $display("lsp: PROCESSOR received Data "); 4.49 - core.sampleInput.put(tagged Sample unpack(truncate(command.sample))); 4.50 +// $display("lsp: PIPE received Data "); 4.51 + core.sampleInput.put(tagged Sample unpack(truncate(command.sample))); 4.52 end 4.53 endrule 4.54 endmodule