# HG changeset patch # User punk # Date 1273076887 14400 # Node ID 4d87fa55a776f7f9c0166297bf97f075a9880fc1 # Parent ced2ebd41347e5dbd2ada2ca25c5c21fbb80bb7d [svn r44] processor largely working and mixer in good status diff -r ced2ebd41347 -r 4d87fa55a776 modules/bluespec/Pygar/core/AudioCoreSystem.cpp --- a/modules/bluespec/Pygar/core/AudioCoreSystem.cpp Wed May 05 01:09:09 2010 -0400 +++ b/modules/bluespec/Pygar/core/AudioCoreSystem.cpp Wed May 05 12:28:07 2010 -0400 @@ -132,7 +132,7 @@ //rlm: two files. // clientStub->SendUnprocessedStream( Data,(UINT32)sample); - clientStub->SendUnprocessedStream((UINT32)channel0 , Data,(UINT32)sample); + clientStub->SendUnprocessedStream((UINT32)channel0 , Data,(UINT32)sample); //clientStub->SendUnprocessedStream(channel1 , Data,(UINT32)sample1); } diff -r ced2ebd41347 -r 4d87fa55a776 modules/bluespec/Pygar/core/PathTypes.bsv --- a/modules/bluespec/Pygar/core/PathTypes.bsv Wed May 05 01:09:09 2010 -0400 +++ b/modules/bluespec/Pygar/core/PathTypes.bsv Wed May 05 12:28:07 2010 -0400 @@ -14,7 +14,7 @@ typedef Int#(TLog#(`MAX_PATH_IDS)) PathId; //typedef Int#(16) Sample; typedef Int#(TLog#(`MAX_VOICES)) VoiceId; -typedef Bit#(8) Volume; // This is arbitrarily set to 8 bits or max val 256 +typedef Int#(8) Volume; // This is arbitrarily set to 8 bits or max val 256 //The mixer is identified as PathId 0, path end is max PathId mixerId = 0; diff -r ced2ebd41347 -r 4d87fa55a776 modules/bluespec/Pygar/core/Processor.bsv --- a/modules/bluespec/Pygar/core/Processor.bsv Wed May 05 01:09:09 2010 -0400 +++ b/modules/bluespec/Pygar/core/Processor.bsv Wed May 05 12:28:07 2010 -0400 @@ -252,7 +252,7 @@ FIFO#(DataResp) dataRespQ <- mkFIFO(); // Audio I/O - FIFO#(AudioProcessorUnit) inAudioFifo <- mkFIFO; + FIFO#(AudioProcessorUnit) inAudioFifo <- mkSizedFIFO(512); FIFO#(AudioProcessorUnit) outAudioFifo <- mkFIFO; @@ -372,7 +372,6 @@ end tagged LUI .it : begin - $display("PROCESSOR Instr LUI\n"); Bit#(32) zext_it_imm = zext(it.imm); wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(zext_it_imm << 32'd16) }); end @@ -458,14 +457,12 @@ tagged JR .it : begin - $display("PROCESSOR inst JR\n"); newPC = rf.rd1(it.rsrc); branchTaken = True; end tagged JAL .it : begin - $display("PROCESSOR inst JAL\n"); wbQ.enq(tagged WB_ALU {dest:31, data:pc_plus4 }); newPC = { pc_plus4[31:28], it.target, 2'b0 }; branchTaken = True; @@ -482,7 +479,7 @@ tagged MTC0 .it : //Recieve things from host computer begin - $display( " PROCESSOR MTC0 call\n"); +// $display( " PROCESSOR MTC0 call\n"); case ( it.cop0dst ) 5'd10 : cp0_statsEn <= unpack(truncate(rf.rd1(it.rsrc))); 5'd21 : cp0_tohost <= truncate(rf.rd1(it.rsrc)); @@ -497,22 +494,21 @@ //this is host stuff? tagged MFC0 .it : //Things out begin - $display( " PROCESSOR MFC0 call\n"); case ( it.cop0src ) // not actually an ALU instruction but don't have the format otherwise 5'd10 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(cp0_statsEn)) }); 5'd20 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_fromhost }); 5'd21 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_tohost }); 5'd25 : begin - $display( "**** EOF Requested\n "); +// $display( "**** EOF Requested\n "); wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(cp0_audioEOF)) }); // Reading clears bit cp0_audioEOF <= False; end 5'd28 : begin - $display( "***** Reqesting Sample \n"); +// $display( "***** Reqesting Sample \n"); let sample = inAudioFifo.first(); // is this going to cause perf. delay? if (sample matches tagged Sample .audio) // if it is EOF another rule sets the cp0_audioEOF - wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(audio)) }); // do I need pack? + wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(audio)) }); // do I need pack? else $display ( "Audio File EOF Reached. Invalid sample request."); inAudioFifo.deq(); end @@ -570,26 +566,27 @@ num_cycles.incr(); endrule - +/* // for now, we don't do anything. -// rule connectAudioReqResp; -// $display("rlm: PROCESSOR copies a datum\n"); -// outAudioFifo.enq(inAudioFifo.first()); -// inAudioFifo.deq; -// endrule + rule connectAudioReqResp; + $display("rlm: PROCESSOR copies a datum\n"); + outAudioFifo.enq(inAudioFifo.first()); + inAudioFifo.deq; + endrule +*/ rule flagAudioEnd (inAudioFifo.first() matches tagged EndOfFile); $display (" PROCESSOR End Audio Flag Set "); cp0_audioEOF <= True; inAudioFifo.deq; endrule -/* + rule sendAudioEnd (cp0_progComp); $display (" PROCESSOR Says Program Complete "); outAudioFifo.enq(tagged EndOfFile); cp0_progComp <= False; //only send one. And functions to reset endrule -*/ + //----------------------------------------------------------- // Methods diff -r ced2ebd41347 -r 4d87fa55a776 modules/bluespec/Pygar/core/audioCorePipeline.bsv --- a/modules/bluespec/Pygar/core/audioCorePipeline.bsv Wed May 05 01:09:09 2010 -0400 +++ b/modules/bluespec/Pygar/core/audioCorePipeline.bsv Wed May 05 12:28:07 2010 -0400 @@ -37,7 +37,7 @@ `include "asim/provides/audio_pipe_types.bsh" //provides Audio Pipeline interface `include "asim/provides/path_types.bsh" `include "asim/provides/core.bsh" -//`include "asim/provides/mixer.bsh" +`include "asim/provides/mixer.bsh" `include "asim/provides/processor_library.bsh" `include "asim/provides/fpga_components.bsh" `include "asim/provides/scratchpad_memory.bsh" @@ -79,13 +79,13 @@ let coreReq <- core.mmem_client.request.get; case (coreReq) matches tagged LoadReq .load: begin - $display("PIPE Load Addr Req %x", load.addr); +// $display("PIPE Load Addr Req %h", load.addr); //Allocate ROB space memory.readReq(truncate(load.addr>>2)); tags.enq(load.tag); end tagged StoreReq .store: begin - $display("PIPE Write Addr Req %x", store.addr); +// $display("PIPE Write Addr Req %h", store.addr); memory.write(truncate(store.addr>>2),store.data); end endcase @@ -96,7 +96,7 @@ tags.deq; core.mmem_client.response.put(tagged LoadResp {data:memResp, tag: tags.first}); - $display("PIPE Receive MemReq %x", memResp); +// $display("PIPE Receive MemReq %x", memResp); endrule rule feedOutput; @@ -131,13 +131,13 @@ if(ctrl == EndOfFile) begin - $display("lsp: PROCESSOR received EOF "); - core.sampleInput.put(tagged EndOfFile); + $display("lsp: PIPE received EOF "); + core.sampleInput.put(tagged EndOfFile); end else begin - $display("lsp: PROCESSOR received Data "); - core.sampleInput.put(tagged Sample unpack(truncate(command.sample))); +// $display("lsp: PIPE received Data "); + core.sampleInput.put(tagged Sample unpack(truncate(command.sample))); end endrule endmodule