Mercurial > pygar
view modules/bluespec/Pygar/lab4/InstCacheBlocking.bsv @ 50:2b18894f75e2 pygar svn.51
[svn r51] fixed processor- it works
author | punk |
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date | Wed, 05 May 2010 15:19:32 -0400 |
parents | 61f6267cb3db |
children | 9fe5ed4af92d |
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1 // The MIT License3 // Copyright (c) 2009 Massachusetts Institute of Technology5 // Permission is hereby granted, free of charge, to any person obtaining a copy6 // of this software and associated documentation files (the "Software"), to deal7 // in the Software without restriction, including without limitation the rights8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell9 // copies of the Software, and to permit persons to whom the Software is10 // furnished to do so, subject to the following conditions:12 // The above copyright notice and this permission notice shall be included in13 // all copies or substantial portions of the Software.15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN21 // THE SOFTWARE.23 import Connectable::*;24 import GetPut::*;25 import ClientServer::*;26 import RegFile::*;27 import FIFO::*;28 import FIFOF::*;29 import RWire::*;30 import Trace::*;32 // Local includes33 `include "asim/provides/low_level_platform_interface.bsh"34 `include "asim/provides/soft_connections.bsh"35 `include "asim/provides/processor_library.bsh"36 `include "asim/provides/fpga_components.bsh"37 `include "asim/provides/common_services.bsh"38 `include "asim/dict/STATS_INST_CACHE.bsh"40 interface ICache#( type req_t, type resp_t );42 // Interface from processor to cache43 interface Server#(req_t,resp_t) proc_server;45 // Interface from cache to main memory46 interface Client#(MainMemReq,MainMemResp) mmem_client;48 // Interface for enabling/disabling statistics49 interface Put#(Bool) statsEn_put;51 endinterface53 //----------------------------------------------------------------------54 // Cache Types55 //----------------------------------------------------------------------57 typedef 10 CacheLineIndexSz;58 typedef 20 CacheLineTagSz;59 typedef 32 CacheLineSz;61 typedef Bit#(CacheLineIndexSz) CacheLineIndex;62 typedef Bit#(CacheLineTagSz) CacheLineTag;63 typedef Bit#(CacheLineSz) CacheLine;65 typedef enum66 {67 Init,68 Access,69 Evict,70 RefillReq,71 RefillResp72 }73 CacheStage74 deriving (Eq,Bits);76 //----------------------------------------------------------------------77 // Helper functions78 //----------------------------------------------------------------------80 function Bit#(AddrSz) getAddr( InstReq req );82 Bit#(AddrSz) addr = ?;83 case ( req ) matches84 tagged LoadReq .ld : addr = ld.addr;85 tagged StoreReq .st : addr = st.addr;86 endcase88 return addr;90 endfunction92 function CacheLineIndex getCacheLineIndex( InstReq req );93 Bit#(AddrSz) addr = getAddr(req);94 Bit#(CacheLineIndexSz) index = truncate( addr >> 2 );95 return index;96 endfunction98 function CacheLineTag getCacheLineTag( InstReq req );99 Bit#(AddrSz) addr = getAddr(req);100 Bit#(CacheLineTagSz) tag = truncate( addr >> fromInteger(valueOf(CacheLineIndexSz)) >> 2 );101 return tag;102 endfunction104 function Bit#(AddrSz) getCacheLineAddr( InstReq req );105 Bit#(AddrSz) addr = getAddr(req);106 return ((addr >> 2) << 2);107 endfunction109 //----------------------------------------------------------------------110 // Main module111 //----------------------------------------------------------------------113 module [CONNECTED_MODULE] mkInstCache( ICache#(InstReq,InstResp) );115 //-----------------------------------------------------------116 // State118 Reg#(CacheStage) stage <- mkReg(Init);120 LUTRAM#(CacheLineIndex,Maybe#(CacheLineTag)) cacheTagRam <- mkLUTRAMU_RegFile();121 LUTRAM#(CacheLineIndex,CacheLine) cacheDataRam <- mkLUTRAMU_RegFile();123 FIFO#(InstReq) reqQ <- mkFIFO();124 FIFOF#(InstResp) respQ <- mkBFIFOF1();126 FIFO#(MainMemReq) mainMemReqQ <- mkBFIFO1();127 FIFO#(MainMemResp) mainMemRespQ <- mkFIFO();129 Reg#(CacheLineIndex) initCounter <- mkReg(1);131 // Statistics state133 Reg#(Bool) statsEn <- mkReg(False);135 //rlm:136 //STAT num_accesses <- mkStatCounter(`STATS_INST_CACHE_NUM_ACCESSES);137 //STAT num_misses <- mkStatCounter(`STATS_INST_CACHE_NUM_MISSES);138 //STAT num_evictions <- mkStatCounter(`STATS_INST_CACHE_NUM_EVICTIONS);140 //-----------------------------------------------------------141 // Name some wires143 let req = reqQ.first();144 let reqIndex = getCacheLineIndex(req);145 let reqTag = getCacheLineTag(req);146 let reqCacheLineAddr = getCacheLineAddr(req);147 let refill = mainMemRespQ.first();149 //-----------------------------------------------------------150 // Initialize152 rule init ( stage == Init );153 traceTiny("mkInstCacheBlocking", "stage","i");154 initCounter <= initCounter + 1;155 cacheTagRam.upd(initCounter,Invalid);156 if ( initCounter == 0 )157 stage <= Access;158 endrule160 //-----------------------------------------------------------161 // Cache access rule163 rule access ( (stage == Access) && respQ.notFull() );165 // Statistics166 //rlm:167 // if ( statsEn )168 // num_accesses.incr();170 // Check tag and valid bit to see if this is a hit or a miss172 Maybe#(CacheLineTag) cacheLineTag = cacheTagRam.sub(reqIndex);174 // Handle cache hits ...176 if ( isValid(cacheLineTag) && ( unJust(cacheLineTag) == reqTag ) )177 begin178 traceTiny("mkInstCacheBlocking", "hitMiss","h");179 reqQ.deq();181 case ( req ) matches183 tagged LoadReq .ld :184 respQ.enq( LoadResp { tag : ld.tag, data : cacheDataRam.sub(reqIndex) } );186 tagged StoreReq .st :187 $display( " RTL-ERROR : %m : Stores are not allowed on the inst port!" );189 endcase191 end193 // Handle cache misses - since lines in instruction cache are194 // never dirty we can always immediately issue a refill request196 else197 begin198 traceTiny("mkInstCacheBlocking", "hitMiss","m");199 //rlm:200 //if ( statsEn )201 //num_misses.incr();202 //if ( statsEn )203 //if ( isJust(cacheLineTag) )204 //num_evictions.incr();206 MainMemReq rfReq207 = LoadReq { tag : 0,208 addr : reqCacheLineAddr };210 mainMemReqQ.enq(rfReq);211 stage <= RefillResp;212 end214 endrule216 //-----------------------------------------------------------217 // Refill response rule219 rule refillResp ( stage == RefillResp );220 traceTiny("mkInstCacheBlocking", "stage","R");221 traceTiny("mkInstCacheBlocking", "refill",refill);223 // Write the new data into the cache and update the tag225 mainMemRespQ.deq();226 case ( mainMemRespQ.first() ) matches228 tagged LoadResp .ld :229 begin230 cacheTagRam.upd(reqIndex,Valid(reqTag));231 cacheDataRam.upd(reqIndex,ld.data);232 end234 tagged StoreResp .st :235 noAction;237 endcase239 stage <= Access;240 endrule242 //-----------------------------------------------------------243 // Methods245 interface Client mmem_client;246 interface Get request = fifoToGet(mainMemReqQ);247 interface Put response = fifoToPut(mainMemRespQ);248 endinterface250 interface Server proc_server;251 interface Put request = tracePut("mkInstCacheBlocking", "reqTiny",fifoToPut(reqQ));252 interface Get response = traceGet("mkInstCacheBlocking", "respTiny",fifofToGet(respQ));253 endinterface255 interface Put statsEn_put = regToPut(statsEn);257 endmodule