view core/sim/bdir_dut/BRegFile.bi @ 25:220c14f5963c pygar svn.26

[svn r26] Not fully connected but passes audio successfully
author punk
date Wed, 28 Apr 2010 12:01:37 -0400
parents 91a1f76ddd62
children
line wrap: on
line source
1 signature BRegFile where {
2 import ¶Counter®¶;
4 import ¶FIFOF_®¶;
6 import ¶FIFOF®¶;
8 import ¶FIFO®¶;
10 import ¶Inout®¶;
12 import ¶List®¶;
14 import ¶Clocks®¶;
16 import ¶ListN®¶;
18 import ¶PrimArray®¶;
20 import ¶RWire®¶;
22 import ¶RegFile®¶;
24 import ¶Vector®¶;
26 import ¶Connectable®¶;
28 import ¶GetPut®¶;
30 import ¶ClientServer®¶;
32 import Trace;
34 import ProcTypes;
36 interface (BRegFile.BRegFile :: * -> * -> *) index_t data_t = {
37 BRegFile.upd :: index_t -> data_t -> ¶Prelude®¶.¶Action®¶ {-# arg_names = [addr, ¡data¡] #-};
38 BRegFile.sub :: index_t -> data_t {-# arg_names = [addr] #-}
39 };
41 instance BRegFile (¶Prelude®¶.¶PrimMakeUndefined®¶ data_t) =>
42 ¶Prelude®¶.¶PrimMakeUndefined®¶ (BRegFile.BRegFile index_t data_t);
44 instance BRegFile ¶Prelude®¶.¶PrimDeepSeqCond®¶ (BRegFile.BRegFile index_t data_t);
46 instance BRegFile ¶Prelude®¶.¶PrimMakeUninitialized®¶ (BRegFile.BRegFile index_t data_t);
48 BRegFile.mkBRegFile :: (¶Prelude®¶.¶Bounded®¶ index_t,
49 ¶Prelude®¶.¶Eq®¶ index_t,
50 ¶Prelude®¶.¶Bits®¶ data_t size_data,
51 ¶Prelude®¶.¶Bits®¶ index_t size_index,
52 ¶Prelude®¶.¶IsModule®¶ _m__ _c__) =>
53 _m__ (¶RegFile®¶.¶RegFile®¶ index_t data_t)
54 }