Mercurial > pygar
view core/sim/bdir_dut/DataCacheBlocking.bi @ 63:1d5cbb5343d2 pygar svn.64
[svn r64] mods to compile correctly for FPGA
author | punk |
---|---|
date | Mon, 10 May 2010 22:54:54 -0400 |
parents | 91a1f76ddd62 |
children |
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1 signature DataCacheBlocking where {2 import ¶Assert®¶;4 import ¶Counter®¶;6 import ¶FIFOF_®¶;8 import ¶FIFOF®¶;10 import ¶FIFO®¶;12 import ¶Inout®¶;14 import ¶List®¶;16 import BFIFO;18 import ¶Clocks®¶;20 import ¶ListN®¶;22 import ¶PrimArray®¶;24 import ¶RegFile®¶;26 import ¶Vector®¶;28 import ¶Connectable®¶;30 import ¶GetPut®¶;32 import ¶ClientServer®¶;34 import Trace;36 import MemTypes;38 import ProcTypes;40 interface (DataCacheBlocking.DCacheStats :: *) = {41 DataCacheBlocking.num_accesses :: ¶GetPut®¶.¶Get®¶ ProcTypes.Stat;42 DataCacheBlocking.num_misses :: ¶GetPut®¶.¶Get®¶ ProcTypes.Stat;43 DataCacheBlocking.num_writebacks :: ¶GetPut®¶.¶Get®¶ ProcTypes.Stat44 };46 instance DataCacheBlocking ¶Prelude®¶.¶PrimMakeUndefined®¶ DataCacheBlocking.DCacheStats;48 instance DataCacheBlocking ¶Prelude®¶.¶PrimDeepSeqCond®¶ DataCacheBlocking.DCacheStats;50 instance DataCacheBlocking ¶Prelude®¶.¶PrimMakeUninitialized®¶ DataCacheBlocking.DCacheStats;52 interface (DataCacheBlocking.DCache :: * -> * -> *) req_t resp_t = {53 DataCacheBlocking.proc_server :: ¶ClientServer®¶.¶Server®¶ req_t resp_t;54 DataCacheBlocking.mmem_client :: ¶ClientServer®¶.¶Client®¶ MemTypes.MainMemReq MemTypes.MainMemResp;55 DataCacheBlocking.statsEn_put :: ¶GetPut®¶.¶Put®¶ ¶Prelude®¶.¶Bool®¶;56 DataCacheBlocking.stats :: DataCacheBlocking.DCacheStats57 };59 instance DataCacheBlocking (¶Prelude®¶.¶PrimMakeUndefined®¶ resp_t) =>60 ¶Prelude®¶.¶PrimMakeUndefined®¶ (DataCacheBlocking.DCache req_t resp_t);62 instance DataCacheBlocking (¶Prelude®¶.¶PrimDeepSeqCond®¶ resp_t) =>63 ¶Prelude®¶.¶PrimDeepSeqCond®¶ (DataCacheBlocking.DCache req_t resp_t);65 instance DataCacheBlocking ¶Prelude®¶.¶PrimMakeUninitialized®¶66 (DataCacheBlocking.DCache req_t resp_t);68 type (DataCacheBlocking.CacheLineIndexSz :: #) = 10;70 type (DataCacheBlocking.CacheLineTagSz :: #) = 20;72 type (DataCacheBlocking.CacheLineSz :: #) = 32;74 type (DataCacheBlocking.CacheLineIndex :: *) = ¶Prelude®¶.¶Bit®¶ DataCacheBlocking.CacheLineIndexSz;76 type (DataCacheBlocking.CacheLineTag :: *) = ¶Prelude®¶.¶Bit®¶ DataCacheBlocking.CacheLineTagSz;78 type (DataCacheBlocking.CacheLine :: *) = ¶Prelude®¶.¶Bit®¶ DataCacheBlocking.CacheLineSz;80 data (DataCacheBlocking.CacheStage :: *) =81 DataCacheBlocking.Init () |82 DataCacheBlocking.Access () |83 DataCacheBlocking.RefillReq () |84 DataCacheBlocking.RefillResp ();86 instance DataCacheBlocking ¶Prelude®¶.¶PrimMakeUndefined®¶ DataCacheBlocking.CacheStage;88 instance DataCacheBlocking ¶Prelude®¶.¶PrimDeepSeqCond®¶ DataCacheBlocking.CacheStage;90 instance DataCacheBlocking ¶Prelude®¶.¶PrimMakeUninitialized®¶ DataCacheBlocking.CacheStage;92 instance DataCacheBlocking ¶Prelude®¶.¶Eq®¶ DataCacheBlocking.CacheStage;94 instance DataCacheBlocking ¶Prelude®¶.¶Bits®¶ DataCacheBlocking.CacheStage 2;96 DataCacheBlocking.getAddr :: MemTypes.DataReq -> ¶Prelude®¶.¶Bit®¶ MemTypes.AddrSz;98 DataCacheBlocking.getCacheLineIndex :: MemTypes.DataReq -> DataCacheBlocking.CacheLineIndex;100 DataCacheBlocking.getCacheLineTag :: MemTypes.DataReq -> DataCacheBlocking.CacheLineTag;102 DataCacheBlocking.getCacheLineAddr :: MemTypes.DataReq -> ¶Prelude®¶.¶Bit®¶ MemTypes.AddrSz;104 DataCacheBlocking.mkDataCache :: (¶Prelude®¶.¶IsModule®¶ _m__ _c__) =>105 _m__ (DataCacheBlocking.DCache MemTypes.DataReq MemTypes.DataResp)106 }