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view core/sim/bdir_dut/BFIFO.bi @ 63:1d5cbb5343d2 pygar svn.64

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[svn r64] mods to compile correctly for FPGA
author punk
date Mon, 10 May 2010 22:54:54 -0400
parents 91a1f76ddd62
children
line wrap: on
line source
     1 signature BFIFO where {



     2 import ¶Assert®¶;



     3 		



     4 import ¶FIFOF_®¶;



     5 		



     6 import ¶FIFOF®¶;



     7 	       



     8 import ¶FIFO®¶;



     9 	      



    10 import ¶List®¶;



    11 	      



    12 BFIFO.mkBFIFO1 :: (¶Prelude®¶.¶Bits®¶ item_t item_sz, ¶Prelude®¶.¶IsModule®¶ _m__ _c__) =>



    13 		  _m__ (¶FIFO®¶.¶FIFO®¶ item_t);



    14 					       



    15 BFIFO.mkSizedBFIFO :: (¶Prelude®¶.¶Bits®¶ item_t item_sz, ¶Prelude®¶.¶IsModule®¶ _m__ _c__) =>



    16 		      ¶Prelude®¶.¶Integer®¶ -> _m__ (¶FIFO®¶.¶FIFO®¶ item_t);



    17 									    



    18 BFIFO.mkBFIFOF1 :: (¶Prelude®¶.¶Bits®¶ item_t item_sz, ¶Prelude®¶.¶IsModule®¶ _m__ _c__) =>



    19 		   _m__ (¶FIFOF®¶.¶FIFOF®¶ item_t);



    20 						  



    21 BFIFO.mkBFIFO_16 :: (¶Prelude®¶.¶IsModule®¶ _m__ _c__) =>



    22 		    _m__ (¶FIFO®¶.¶FIFO®¶ (¶Prelude®¶.¶Bit®¶ 16))



    23 }