1.1 --- a/modules/bluespec/Pygar/core/audioCorePipeline.bsv	Tue May 04 22:32:52 2010 -0400
     1.2 +++ b/modules/bluespec/Pygar/core/audioCorePipeline.bsv	Wed May 05 01:09:09 2010 -0400
     1.3 @@ -37,6 +37,7 @@
     1.4  `include "asim/provides/audio_pipe_types.bsh"  //provides Audio Pipeline interface
     1.5  `include "asim/provides/path_types.bsh"
     1.6  `include "asim/provides/core.bsh"
     1.7 +//`include "asim/provides/mixer.bsh"
     1.8  `include "asim/provides/processor_library.bsh"
     1.9  `include "asim/provides/fpga_components.bsh"
    1.10  `include "asim/provides/scratchpad_memory.bsh"
    1.11 @@ -78,11 +79,13 @@
    1.12      let coreReq <- core.mmem_client.request.get;
    1.13      case (coreReq) matches 
    1.14        tagged LoadReq .load: begin
    1.15 +	                      $display("PIPE Load Addr Req %x", load.addr); 
    1.16                                //Allocate ROB space
    1.17                                memory.readReq(truncate(load.addr>>2));
    1.18                                tags.enq(load.tag);
    1.19                              end
    1.20 -      tagged StoreReq .store: begin
    1.21 +       tagged StoreReq .store: begin
    1.22 +	  	              $display("PIPE Write Addr Req %x", store.addr); 
    1.23  	                      memory.write(truncate(store.addr>>2),store.data);
    1.24                                end
    1.25      endcase
    1.26 @@ -93,6 +96,7 @@
    1.27      tags.deq;
    1.28      core.mmem_client.response.put(tagged LoadResp {data:memResp,
    1.29                                                     tag: tags.first});
    1.30 +     	                $display("PIPE Receive MemReq %x", memResp); 
    1.31    endrule
    1.32  
    1.33     rule feedOutput;