1.1 --- a/modules/bluespec/Pygar/core/audioCorePipeline.bsv	Wed May 05 13:23:58 2010 -0400
     1.2 +++ b/modules/bluespec/Pygar/core/audioCorePipeline.bsv	Wed May 05 13:42:07 2010 -0400
     1.3 @@ -40,9 +40,6 @@
     1.4  `include "asim/provides/mixer.bsh"
     1.5  `include "asim/provides/processor_library.bsh"
     1.6  `include "asim/provides/fpga_components.bsh"
     1.7 -`include "asim/provides/scratchpad_memory.bsh"
     1.8 -`include "asim/provides/mem_services.bsh"
     1.9 -`include "asim/dict/VDEV_SCRATCH.bsh"
    1.10  
    1.11  `include "asim/rrr/remote_client_stub_AUDIOCORERRR.bsh"
    1.12  `include "asim/rrr/remote_server_stub_AUDIOCORERRR.bsh"
    1.13 @@ -61,12 +58,10 @@
    1.14    //External memory 
    1.15    // I'm not comfortable assuming that the memory subsystem is in order  
    1.16    // So I'll insert a completion buffer here.
    1.17 -  MEMORY_IFC#(Bit#(18), Bit#(32)) memory <- mkScratchpad(`VDEV_SCRATCH_MEMORY, SCRATCHPAD_CACHED);   //Services Memory items
    1.18  
    1.19    // Services Samples 
    1.20    ClientStub_AUDIOCORERRR client_stub <- mkClientStub_AUDIOCORERRR();   
    1.21 -  // Make this big enough so that several outstanding requests may be supported
    1.22 -  FIFO#(Bit#(MainMemTagSz)) tags <- mkSizedFIFO(8);
    1.23 +  
    1.24  
    1.25     //-----------------------------------------------------------
    1.26     // Debug port
    1.27 @@ -80,31 +75,7 @@
    1.28      $fdisplay(stderr, " => Cycle = %d", cycle);
    1.29    endrule
    1.30  
    1.31 -  rule sendMemReq;
    1.32 -    let coreReq <- core.mmem_client.request.get;
    1.33 -    case (coreReq) matches 
    1.34 -      tagged LoadReq .load: begin
    1.35 -//	                      $display("PIPE Load Addr Req %h", load.addr); 
    1.36 -                              //Allocate ROB space
    1.37 -                              memory.readReq(truncate(load.addr>>2));
    1.38 -                              tags.enq(load.tag);
    1.39 -                            end
    1.40 -       tagged StoreReq .store: begin
    1.41 -//	  	              $display("PIPE Write Addr Req %h", store.addr); 
    1.42 -	                      memory.write(truncate(store.addr>>2),store.data);
    1.43 -                              end
    1.44 -    endcase
    1.45 -  endrule
    1.46 -  
    1.47 -  rule receiveMemResp;
    1.48 -    let memResp <- memory.readRsp();
    1.49 -    tags.deq;
    1.50 -    core.mmem_client.response.put(tagged LoadResp {data:memResp,
    1.51 -                                                   tag: tags.first});
    1.52 -//   	                $display("PIPE Receive MemReq %x", memResp); 
    1.53 -  endrule
    1.54 -
    1.55 -   rule feedOutput;
    1.56 +  rule feedOutput;
    1.57       let pipelineData <- core.sampleOutput.get();
    1.58       AudioProcessorControl endOfFileTag = EndOfFile;
    1.59       AudioProcessorControl sampleTag = Data;
    1.60 @@ -131,7 +102,7 @@
    1.61       AudioProcessorControl ctrl = unpack(truncate(command.ctrl));
    1.62  
    1.63        Bit#(32) test = unpack(truncate(command.channel));
    1.64 -      $display("rlm: %x", test);
    1.65 +//      $display("rlm: %x", test);
    1.66  	   
    1.67  
    1.68        if(ctrl == EndOfFile)