1.1 --- a/modules/bluespec/Pygar/core/audioCore.bsv	Wed May 05 13:23:58 2010 -0400
     1.2 +++ b/modules/bluespec/Pygar/core/audioCore.bsv	Wed May 05 13:42:07 2010 -0400
     1.3 @@ -26,6 +26,7 @@
     1.4  import Processor::*;
     1.5  import MemArb::*;
     1.6  import MemTypes::*;
     1.7 +import FIFO::*;
     1.8  
     1.9  //AWB includes
    1.10  `include "asim/provides/low_level_platform_interface.bsh"
    1.11 @@ -40,11 +41,13 @@
    1.12  `include "asim/provides/processor.bsh"
    1.13  `include "asim/provides/audio_pipe_types.bsh"
    1.14  
    1.15 +// Scratchpad includes
    1.16 +`include "asim/provides/scratchpad_memory.bsh"
    1.17 +`include "asim/provides/mem_services.bsh"
    1.18 +`include "asim/dict/VDEV_SCRATCH.bsh"
    1.19 +
    1.20  interface Core;
    1.21  
    1.22 -  // Interface from core to main memory
    1.23 -   interface Client#(MainMemReq,MainMemResp) mmem_client;
    1.24 -
    1.25     interface Get#(AudioProcessorUnit) sampleOutput;
    1.26     interface Put#(AudioProcessorUnit) sampleInput;
    1.27  	 
    1.28 @@ -53,6 +56,7 @@
    1.29  endinterface
    1.30  
    1.31  module   [CONNECTED_MODULE]  mkCore( Core );
    1.32 +   
    1.33  
    1.34    // Instantiate the modules
    1.35  
    1.36 @@ -60,7 +64,11 @@
    1.37    ICache#(InstReq,InstResp) icache <- mkInstCache();
    1.38    DCache#(DataReq,DataResp) dcache <- mkDataCache();
    1.39    MemArb marb <- mkMemArb();
    1.40 +  MEMORY_IFC#(Bit#(18), Bit#(32)) memory <- mkScratchpad(`VDEV_SCRATCH_MEMORY, SCRATCHPAD_CACHED);   //Services Memory items
    1.41  
    1.42 +  // Make this big enough so that several outstanding requests may be supported
    1.43 +  FIFO#(Bit#(MainMemTagSz)) tags <- mkSizedFIFO(8);
    1.44 +   
    1.45    // Internal connections
    1.46  
    1.47    mkConnection( proc.statsEn_get,   icache.statsEn_put );
    1.48 @@ -70,10 +78,33 @@
    1.49    mkConnection( icache.mmem_client, marb.cache0_server );
    1.50    mkConnection( dcache.mmem_client, marb.cache1_server );
    1.51  
    1.52 +  // Memory Access
    1.53 +  rule sendMemReq;
    1.54 +    let coreReq <- marb.mmem_client.request.get;
    1.55 +    case (coreReq) matches 
    1.56 +      tagged LoadReq .load: begin
    1.57 +//	                      $display("PIPE Load Addr Req %h", load.addr); 
    1.58 +                              //Allocate ROB space
    1.59 +                              memory.readReq(truncate(load.addr>>2));
    1.60 +                              tags.enq(load.tag);
    1.61 +                            end
    1.62 +      tagged StoreReq .store: begin
    1.63 +//	  	              $display("PIPE Write Addr Req %h", store.addr); 
    1.64 +	                      memory.write(truncate(store.addr>>2),store.data);
    1.65 +                              end
    1.66 +    endcase
    1.67 +  endrule
    1.68 +  
    1.69 +  rule receiveMemResp;
    1.70 +    let memResp <- memory.readRsp();
    1.71 +    tags.deq;
    1.72 +    marb.mmem_client.response.put(tagged LoadResp {data:memResp,
    1.73 +                                                   tag: tags.first});
    1.74 +//   	                $display("PIPE Receive MemReq %x", memResp); 
    1.75 +  endrule
    1.76 +
    1.77    // Methods
    1.78 -
    1.79 -   interface mmem_client = marb.mmem_client;
    1.80 -      
    1.81 +     
    1.82     interface sampleOutput = proc.sampleOutput;
    1.83     interface sampleInput = proc.sampleInput;
    1.84