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comparison modules/bluespec/Pygar/core/audioCore.bsv @ 48:a139cc07b773 pygar svn.49

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[svn r49] moved memory into core
author punk
date Wed, 05 May 2010 13:42:07 -0400
parents 99519a031813
children 9fe5ed4af92d
comparison
equal deleted inserted replaced
47:97d1959f7c5c 48:a139cc07b773
24 import GetPut::*; 24 import GetPut::*;
25 import ClientServer::*; 25 import ClientServer::*;
26 import Processor::*; 26 import Processor::*;
27 import MemArb::*; 27 import MemArb::*;
28 import MemTypes::*; 28 import MemTypes::*;
29 import FIFO::*;
29 30
30 //AWB includes 31 //AWB includes
31 `include "asim/provides/low_level_platform_interface.bsh" 32 `include "asim/provides/low_level_platform_interface.bsh"
32 `include "asim/provides/soft_connections.bsh" 33 `include "asim/provides/soft_connections.bsh"
33 `include "asim/provides/common_services.bsh" 34 `include "asim/provides/common_services.bsh"
38 `include "asim/provides/instruction_cache.bsh" 39 `include "asim/provides/instruction_cache.bsh"
39 `include "asim/provides/data_cache.bsh" 40 `include "asim/provides/data_cache.bsh"
40 `include "asim/provides/processor.bsh" 41 `include "asim/provides/processor.bsh"
41 `include "asim/provides/audio_pipe_types.bsh" 42 `include "asim/provides/audio_pipe_types.bsh"
42 43
44 // Scratchpad includes
45 `include "asim/provides/scratchpad_memory.bsh"
46 `include "asim/provides/mem_services.bsh"
47 `include "asim/dict/VDEV_SCRATCH.bsh"
48
43 interface Core; 49 interface Core;
44
45 // Interface from core to main memory
46 interface Client#(MainMemReq,MainMemResp) mmem_client;
47 50
48 interface Get#(AudioProcessorUnit) sampleOutput; 51 interface Get#(AudioProcessorUnit) sampleOutput;
49 interface Put#(AudioProcessorUnit) sampleInput; 52 interface Put#(AudioProcessorUnit) sampleInput;
50 53
51 // interface CPUToHost tohost; 54 // interface CPUToHost tohost;
52 55
53 endinterface 56 endinterface
54 57
55 module [CONNECTED_MODULE] mkCore( Core ); 58 module [CONNECTED_MODULE] mkCore( Core );
59
56 60
57 // Instantiate the modules 61 // Instantiate the modules
58 62
59 Proc proc <- mkProc(); 63 Proc proc <- mkProc();
60 ICache#(InstReq,InstResp) icache <- mkInstCache(); 64 ICache#(InstReq,InstResp) icache <- mkInstCache();
61 DCache#(DataReq,DataResp) dcache <- mkDataCache(); 65 DCache#(DataReq,DataResp) dcache <- mkDataCache();
62 MemArb marb <- mkMemArb(); 66 MemArb marb <- mkMemArb();
67 MEMORY_IFC#(Bit#(18), Bit#(32)) memory <- mkScratchpad(`VDEV_SCRATCH_MEMORY, SCRATCHPAD_CACHED); //Services Memory items
63 68
69 // Make this big enough so that several outstanding requests may be supported
70 FIFO#(Bit#(MainMemTagSz)) tags <- mkSizedFIFO(8);
71
64 // Internal connections 72 // Internal connections
65 73
66 mkConnection( proc.statsEn_get, icache.statsEn_put ); 74 mkConnection( proc.statsEn_get, icache.statsEn_put );
67 mkConnection( proc.statsEn_get, dcache.statsEn_put ); 75 mkConnection( proc.statsEn_get, dcache.statsEn_put );
68 mkConnection( proc.imem_client, icache.proc_server ); 76 mkConnection( proc.imem_client, icache.proc_server );
69 mkConnection( proc.dmem_client, dcache.proc_server ); 77 mkConnection( proc.dmem_client, dcache.proc_server );
70 mkConnection( icache.mmem_client, marb.cache0_server ); 78 mkConnection( icache.mmem_client, marb.cache0_server );
71 mkConnection( dcache.mmem_client, marb.cache1_server ); 79 mkConnection( dcache.mmem_client, marb.cache1_server );
72 80
81 // Memory Access
82 rule sendMemReq;
83 let coreReq <- marb.mmem_client.request.get;
84 case (coreReq) matches
85 tagged LoadReq .load: begin
86 // $display("PIPE Load Addr Req %h", load.addr);
87 //Allocate ROB space
88 memory.readReq(truncate(load.addr>>2));
89 tags.enq(load.tag);
90 end
91 tagged StoreReq .store: begin
92 // $display("PIPE Write Addr Req %h", store.addr);
93 memory.write(truncate(store.addr>>2),store.data);
94 end
95 endcase
96 endrule
97
98 rule receiveMemResp;
99 let memResp <- memory.readRsp();
100 tags.deq;
101 marb.mmem_client.response.put(tagged LoadResp {data:memResp,
102 tag: tags.first});
103 // $display("PIPE Receive MemReq %x", memResp);
104 endrule
105
73 // Methods 106 // Methods
74 107
75 interface mmem_client = marb.mmem_client;
76
77 interface sampleOutput = proc.sampleOutput; 108 interface sampleOutput = proc.sampleOutput;
78 interface sampleInput = proc.sampleInput; 109 interface sampleInput = proc.sampleInput;
79 110
80 // interface CPUToHost tohost = proc.tohost; 111 // interface CPUToHost tohost = proc.tohost;
81 112